430 lines
12 KiB
C
430 lines
12 KiB
C
/******************************************************************************
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* Copyright (c) 2004, 2008 IBM Corporation
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* All rights reserved.
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* This program and the accompanying materials
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* are made available under the terms of the BSD License
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* which accompanies this distribution, and is available at
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* http://www.opensource.org/licenses/bsd-license.php
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*
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* Contributors:
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* IBM Corporation - initial implementation
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*****************************************************************************/
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#include <stdio.h>
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#include <cpu.h>
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#include <pci.h>
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#include "device.h"
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#include "rtas.h"
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#include "debug.h"
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#include "device.h"
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#include <stdint.h>
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#include <x86emu/x86emu.h>
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#include <time.h>
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//defined in net-snk/kernel/timer.c
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extern uint64_t get_time(void);
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// these are not used, only needed for linking, must be overridden using X86emu_setupPioFuncs
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// with the functions and struct below
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void
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outb(uint8_t val, uint16_t port)
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{
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printf("WARNING: outb not implemented!\n");
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HALT_SYS();
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}
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void
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outw(uint16_t val, uint16_t port)
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{
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printf("WARNING: outw not implemented!\n");
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HALT_SYS();
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}
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void
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outl(uint32_t val, uint16_t port)
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{
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printf("WARNING: outl not implemented!\n");
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HALT_SYS();
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}
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uint8_t
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inb(uint16_t port)
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{
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printf("WARNING: inb not implemented!\n");
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HALT_SYS();
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return 0;
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}
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uint16_t
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inw(uint16_t port)
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{
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printf("WARNING: inw not implemented!\n");
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HALT_SYS();
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return 0;
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}
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uint32_t
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inl(uint16_t port)
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{
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printf("WARNING: inl not implemented!\n");
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HALT_SYS();
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return 0;
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}
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uint32_t pci_cfg_read(X86EMU_pioAddr addr, uint8_t size);
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void pci_cfg_write(X86EMU_pioAddr addr, uint32_t val, uint8_t size);
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uint8_t handle_port_61h();
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uint8_t
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my_inb(X86EMU_pioAddr addr)
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{
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uint8_t rval = 0xFF;
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uint64_t translated_addr = addr;
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uint8_t translated = dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successful, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __FUNCTION__,
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addr);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __FUNCTION__, addr, translated_addr);
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rval = read_io((void *)translated_addr, 1);
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DEBUG_PRINTF_IO("%s(%04x) Device I/O --> %02x\n", __FUNCTION__,
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addr, rval);
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return rval;
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} else {
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switch (addr) {
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case 0x61:
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//8254 KB Controller / Timer Port
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rval = handle_port_61h();
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//DEBUG_PRINTF_IO("%s(%04x) KB / Timer Port B --> %02x\n", __FUNCTION__, addr, rval);
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return rval;
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break;
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case 0xCFC:
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case 0xCFD:
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case 0xCFE:
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case 0xCFF:
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// PCI Config Mechanism 1 Ports
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return (uint8_t) pci_cfg_read(addr, 1);
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break;
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case 0x0a:
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CHECK_DBG(DEBUG_INTR) {
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X86EMU_trace_on();
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}
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M.x86.debug &= ~DEBUG_DECODE_NOPRINT_F;
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//HALT_SYS();
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// no break, intentional fall-through to default!!
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default:
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DEBUG_PRINTF_IO
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("%s(%04x) reading from bios_device.io_buffer\n",
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__FUNCTION__, addr);
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rval = *((uint8_t *) (bios_device.io_buffer + addr));
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DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %02x\n",
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__FUNCTION__, addr, rval);
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return rval;
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break;
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}
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}
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}
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uint16_t
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my_inw(X86EMU_pioAddr addr)
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{
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uint64_t translated_addr = addr;
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uint8_t translated = dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successful, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __FUNCTION__,
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addr);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __FUNCTION__, addr, translated_addr);
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uint16_t rval;
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if ((translated_addr & (uint64_t) 0x1) == 0) {
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// 16 bit aligned access...
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uint16_t tempval = read_io((void *)translated_addr, 2);
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//little endian conversion
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rval = in16le((void *) &tempval);
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} else {
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// unaligned access, read single bytes, little-endian
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rval = (read_io((void *)translated_addr, 1) << 8)
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| (read_io((void *)(translated_addr + 1), 1));
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O --> %04x\n", __FUNCTION__,
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addr, rval);
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return rval;
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} else {
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switch (addr) {
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case 0xCFC:
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case 0xCFE:
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//PCI Config Mechanism 1
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return (uint16_t) pci_cfg_read(addr, 2);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x) reading from bios_device.io_buffer\n",
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__FUNCTION__, addr);
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uint16_t rval =
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in16le((void *) bios_device.io_buffer + addr);
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DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %04x\n",
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__FUNCTION__, addr, rval);
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return rval;
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break;
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}
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}
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}
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uint32_t
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my_inl(X86EMU_pioAddr addr)
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{
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uint64_t translated_addr = addr;
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uint8_t translated = dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successful, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x): access to Device I/O\n", __FUNCTION__,
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addr);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __FUNCTION__, addr, translated_addr);
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uint32_t rval;
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if ((translated_addr & (uint64_t) 0x3) == 0) {
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// 32 bit aligned access...
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uint32_t tempval = read_io((void *) translated_addr, 4);
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//little endian conversion
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rval = in32le((void *) &tempval);
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} else {
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// unaligned access, read single bytes, little-endian
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rval = (read_io((void *)(translated_addr), 1) << 24)
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| (read_io((void *)(translated_addr + 1), 1) << 16)
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| (read_io((void *)(translated_addr + 2), 1) << 8)
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O --> %08x\n", __FUNCTION__,
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addr, rval);
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return rval;
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} else {
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switch (addr) {
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case 0xCFC:
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//PCI Config Mechanism 1
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return pci_cfg_read(addr, 4);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x) reading from bios_device.io_buffer\n",
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__FUNCTION__, addr);
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uint32_t rval =
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in32le((void *) bios_device.io_buffer + addr);
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DEBUG_PRINTF_IO("%s(%04x) I/O Buffer --> %08x\n",
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__FUNCTION__, addr, rval);
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return rval;
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break;
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}
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}
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}
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void
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my_outb(X86EMU_pioAddr addr, uint8_t val)
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{
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uint64_t translated_addr = addr;
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uint8_t translated = dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successful, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n",
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__FUNCTION__, addr, val);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __FUNCTION__, addr, translated_addr);
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write_io((void *) translated_addr, val, 1);
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DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %02x\n", __FUNCTION__,
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addr, val);
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} else {
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switch (addr) {
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case 0xCFC:
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case 0xCFD:
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case 0xCFE:
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case 0xCFF:
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// PCI Config Mechanism 1 Ports
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pci_cfg_write(addr, val, 1);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x,%02x) writing to bios_device.io_buffer\n",
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__FUNCTION__, addr, val);
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*((uint8_t *) (bios_device.io_buffer + addr)) = val;
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break;
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}
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}
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}
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void
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my_outw(X86EMU_pioAddr addr, uint16_t val)
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{
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uint64_t translated_addr = addr;
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uint8_t translated = dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successful, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n",
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__FUNCTION__, addr, val);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __FUNCTION__, addr, translated_addr);
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if ((translated_addr & (uint64_t) 0x1) == 0) {
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// little-endian conversion
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uint16_t tempval = in16le((void *) &val);
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// 16 bit aligned access...
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write_io((void *) translated_addr, tempval, 2);
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} else {
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// unaligned access, write single bytes, little-endian
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write_io(((void *) (translated_addr + 1)),
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(uint8_t) ((val & 0xFF00) >> 8), 1);
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write_io(((void *) translated_addr),
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(uint8_t) (val & 0x00FF), 1);
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %04x\n", __FUNCTION__,
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addr, val);
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} else {
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switch (addr) {
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case 0xCFC:
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case 0xCFE:
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// PCI Config Mechanism 1 Ports
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pci_cfg_write(addr, val, 2);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x,%04x) writing to bios_device.io_buffer\n",
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__FUNCTION__, addr, val);
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out16le((void *) bios_device.io_buffer + addr, val);
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break;
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}
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}
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}
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void
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my_outl(X86EMU_pioAddr addr, uint32_t val)
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{
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uint64_t translated_addr = addr;
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uint8_t translated = dev_translate_address(&translated_addr);
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if (translated != 0) {
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//translation successful, access Device I/O (BAR or Legacy...)
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DEBUG_PRINTF_IO("%s(%x, %x): access to Device I/O\n",
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__FUNCTION__, addr, val);
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//DEBUG_PRINTF_IO("%s(%04x): translated_addr: %llx\n", __FUNCTION__, addr, translated_addr);
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if ((translated_addr & (uint64_t) 0x3) == 0) {
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// little-endian conversion
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uint32_t tempval = in32le((void *) &val);
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// 32 bit aligned access...
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write_io((void *) translated_addr, tempval, 4);
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} else {
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// unaligned access, write single bytes, little-endian
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write_io(((void *) translated_addr + 3),
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(uint8_t) ((val & 0xFF000000) >> 24), 1);
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write_io(((void *) translated_addr + 2),
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(uint8_t) ((val & 0x00FF0000) >> 16), 1);
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write_io(((void *) translated_addr + 1),
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(uint8_t) ((val & 0x0000FF00) >> 8), 1);
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write_io(((void *) translated_addr),
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(uint8_t) (val & 0x000000FF), 1);
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}
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DEBUG_PRINTF_IO("%s(%04x) Device I/O <-- %08x\n", __FUNCTION__,
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addr, val);
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} else {
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switch (addr) {
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case 0xCFC:
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// PCI Config Mechanism 1 Ports
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pci_cfg_write(addr, val, 4);
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break;
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default:
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DEBUG_PRINTF_IO
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("%s(%04x,%08x) writing to bios_device.io_buffer\n",
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__FUNCTION__, addr, val);
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out32le((void *) bios_device.io_buffer + addr, val);
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break;
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}
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}
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}
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uint32_t
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pci_cfg_read(X86EMU_pioAddr addr, uint8_t size)
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{
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uint32_t rval = 0xFFFFFFFF;
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if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) {
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later read from 0xCFC-0xCFF returns the value...
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uint8_t bus, devfn, offs;
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uint32_t port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) != 0) {
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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printf
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("Config access invalid! bus: %x, devfn: %x, offs: %x\n",
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bus, devfn, offs);
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HALT_SYS();
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} else {
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rval =
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(uint32_t) rtas_pci_config_read(bios_device.
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puid, size,
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bus, devfn,
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offs);
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Read @%02x, size: %d --> 0x%08x\n",
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__FUNCTION__, addr, offs, size, rval);
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}
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}
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}
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return rval;
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}
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void
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pci_cfg_write(X86EMU_pioAddr addr, uint32_t val, uint8_t size)
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{
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if ((addr >= 0xCFC) && ((addr + size) <= 0xCFF)) {
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// PCI Configuration Mechanism 1 step 1
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// write to 0xCF8, sets bus, device, function and Config Space offset
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// later write to 0xCFC-0xCFF sets the value...
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uint8_t bus, devfn, offs;
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uint32_t port_cf8_val = my_inl(0xCF8);
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if ((port_cf8_val & 0x80000000) != 0) {
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//highest bit enables config space mapping
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bus = (port_cf8_val & 0x00FF0000) >> 16;
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devfn = (port_cf8_val & 0x0000FF00) >> 8;
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offs = (port_cf8_val & 0x000000FF);
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offs += (addr - 0xCFC); // if addr is not 0xcfc, the offset is moved accordingly
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if ((bus != bios_device.bus)
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|| (devfn != bios_device.devfn)) {
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// fail accesses to any device but ours...
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printf
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("Config access invalid! bus: %x, devfn: %x, offs: %x\n",
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bus, devfn, offs);
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HALT_SYS();
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} else {
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rtas_pci_config_write(bios_device.puid,
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size, bus, devfn, offs,
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val);
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DEBUG_PRINTF_IO
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("%s(%04x) PCI Config Write @%02x, size: %d <-- 0x%08x\n",
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__FUNCTION__, addr, offs, size, val);
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}
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}
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}
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}
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uint8_t
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handle_port_61h()
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{
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static uint64_t last_time = 0;
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uint64_t curr_time = get_time();
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uint64_t time_diff; // time since last call
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uint32_t period_ticks; // length of a period in ticks
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uint32_t nr_periods; //number of periods passed since last call
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// bit 4 should toggle with every (DRAM) refresh cycle... (66kHz??)
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time_diff = curr_time - last_time;
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// at 66kHz a period is ~ 15 ns long, converted to ticks: (tb_freq is ticks/second)
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// TODO: as long as the frequency does not change, we should not calculate this every time
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period_ticks = (15 * tb_freq) / 1000000;
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nr_periods = time_diff / period_ticks;
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// if the number if ticks passed since last call is odd, we toggle bit 4
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if ((nr_periods % 2) != 0) {
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*((uint8_t *) (bios_device.io_buffer + 0x61)) ^= 0x10;
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}
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//finally read the value from the io_buffer
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return *((uint8_t *) (bios_device.io_buffer + 0x61));
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}
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