71a351956a
add typedef for exceptionflags enumeration
2023-11-06 17:31:22 +08:00
bef5a34e1b
adding two empty placeholder source file required for RISCV specialization on Linux-x86_64-GCC
2023-10-12 21:07:58 -07:00
b2341032da
review feedback: 16-bit floating-point -> BF16
2023-09-30 20:57:08 -07:00
b1bbccf04d
fixing bf16_to_f32 for subnormal numbers
2023-09-22 18:30:13 -07:00
1172fb3e0a
Adding support for BF16 / BF16 <-> conversions in 8086-SSE
2023-09-19 12:54:43 -07:00
aac867e874
Fixing bf32_to_bf16 conversions
2023-09-17 17:00:08 -07:00
54da0e1be7
Fixing dummy bf16_to_f32 conversion
2023-08-12 10:34:58 +02:00
fab20258f0
Continuing f32_to_bf16 development
2023-08-12 08:00:12 +02:00
ac8688db85
Adding more bf16 support function + skeleton for f32_to_bf16
2023-08-12 06:52:03 +02:00
3d0376df7b
adding initial bf16 support
2023-08-12 04:13:37 +02:00
b64af41c32
Fix typo in function 'softfloat_propagateNaNF128M' for RISC-V.
2018-07-26 13:52:23 -07:00
f74b1e4811
Release 3e. See "doc/SoftFloat-history.html".
2018-01-26 12:51:15 -08:00
db047c521e
Release 3d. See "doc/SoftFloat-history.html".
2017-08-10 16:26:24 -07:00
9d731d45e8
Release 3c. See "doc/SoftFloat-history.html".
2017-02-10 12:35:21 -08:00
cb5087cd74
Release 3b. See "doc/SoftFloat-history.html".
2016-07-22 18:03:04 -07:00
45fdcf1c65
Added the ability to specify the result values delivered when conversions
...
from floating-point to an integer format raise an invalid exception.
For the provided specializations (8086 and RISC-V), changed the result
of converting a negative floating-point value to an unsigned integer
format to now be zero. (Also renamed `shiftCount' inside functions to
`shiftDist'.)
2016-02-22 15:51:12 -08:00
9dc9d10297
For "source/RISCV/specialize.h", updated year in copyright notice to 2016.
2016-01-23 17:56:10 -08:00
ab8e0920d5
Employ new RISC-V NaN encoding
2016-01-16 21:22:46 -08:00
ad6be28b38
Release 3a.
2015-11-03 14:38:58 -08:00
19c55bae5e
Corrected the name of the subdirectory for RISC-V specialization from
...
"RISC-V" to "RISCV". (In the names of machines, compilers, targets, etc.,
hyphens are intended for specifying variations and for forming compound
names from multiple such components. While some arbitrariness in the
application of this rule is inevitable, clearly RISC-V is not a "V"
variation of an existing "RISC" architecture but rather an entirely new
architecture.)
2015-03-12 12:43:06 -07:00
c07232ca9e
Fixed some bugs affecting a few processors. Reboot the official release
...
date (for the last time) to be 2015 Feb 16.
2015-02-19 14:09:32 -08:00
db70c4ef62
Added specialization support for U.C. Berkeley's RISC-V.
2015-01-29 16:18:13 -08:00
17ab1f4a0a
Fixed conflicts over definitions of inline functions for non-GCC compilers.
...
Reboot official release date to be 2015 Jan 9.
2015-01-15 16:04:25 -08:00
437d9b9fb2
Fixed issues with specialization for x86, with and without SSE.
2014-12-11 19:34:37 -08:00
5c93163afa
Update in RC for Release 3, fixing some bugs and adding to the documentation.
2014-12-11 14:27:41 -08:00
8f59d92535
First draft of RC for Release 3, to start review process.
2014-11-28 19:49:28 -08:00
Yanqi Yang