/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|*Target Instruction Enum Values                                              *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */


#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM

enum {
    ARM_PHI	= 0,
    ARM_INLINEASM	= 1,
    ARM_PROLOG_LABEL	= 2,
    ARM_EH_LABEL	= 3,
    ARM_GC_LABEL	= 4,
    ARM_KILL	= 5,
    ARM_EXTRACT_SUBREG	= 6,
    ARM_INSERT_SUBREG	= 7,
    ARM_IMPLICIT_DEF	= 8,
    ARM_SUBREG_TO_REG	= 9,
    ARM_COPY_TO_REGCLASS	= 10,
    ARM_DBG_VALUE	= 11,
    ARM_REG_SEQUENCE	= 12,
    ARM_COPY	= 13,
    ARM_BUNDLE	= 14,
    ARM_LIFETIME_START	= 15,
    ARM_LIFETIME_END	= 16,
    ARM_STACKMAP	= 17,
    ARM_PATCHPOINT	= 18,
    ARM_ABS	= 19,
    ARM_ADCri	= 20,
    ARM_ADCrr	= 21,
    ARM_ADCrsi	= 22,
    ARM_ADCrsr	= 23,
    ARM_ADDSri	= 24,
    ARM_ADDSrr	= 25,
    ARM_ADDSrsi	= 26,
    ARM_ADDSrsr	= 27,
    ARM_ADDri	= 28,
    ARM_ADDrr	= 29,
    ARM_ADDrsi	= 30,
    ARM_ADDrsr	= 31,
    ARM_ADJCALLSTACKDOWN	= 32,
    ARM_ADJCALLSTACKUP	= 33,
    ARM_ADR	= 34,
    ARM_AESD	= 35,
    ARM_AESE	= 36,
    ARM_AESIMC	= 37,
    ARM_AESMC	= 38,
    ARM_ANDri	= 39,
    ARM_ANDrr	= 40,
    ARM_ANDrsi	= 41,
    ARM_ANDrsr	= 42,
    ARM_ASRi	= 43,
    ARM_ASRr	= 44,
    ARM_ATOMIC_CMP_SWAP_I16	= 45,
    ARM_ATOMIC_CMP_SWAP_I32	= 46,
    ARM_ATOMIC_CMP_SWAP_I64	= 47,
    ARM_ATOMIC_CMP_SWAP_I8	= 48,
    ARM_ATOMIC_LOAD_ADD_I16	= 49,
    ARM_ATOMIC_LOAD_ADD_I32	= 50,
    ARM_ATOMIC_LOAD_ADD_I64	= 51,
    ARM_ATOMIC_LOAD_ADD_I8	= 52,
    ARM_ATOMIC_LOAD_AND_I16	= 53,
    ARM_ATOMIC_LOAD_AND_I32	= 54,
    ARM_ATOMIC_LOAD_AND_I64	= 55,
    ARM_ATOMIC_LOAD_AND_I8	= 56,
    ARM_ATOMIC_LOAD_I64	= 57,
    ARM_ATOMIC_LOAD_MAX_I16	= 58,
    ARM_ATOMIC_LOAD_MAX_I32	= 59,
    ARM_ATOMIC_LOAD_MAX_I64	= 60,
    ARM_ATOMIC_LOAD_MAX_I8	= 61,
    ARM_ATOMIC_LOAD_MIN_I16	= 62,
    ARM_ATOMIC_LOAD_MIN_I32	= 63,
    ARM_ATOMIC_LOAD_MIN_I64	= 64,
    ARM_ATOMIC_LOAD_MIN_I8	= 65,
    ARM_ATOMIC_LOAD_NAND_I16	= 66,
    ARM_ATOMIC_LOAD_NAND_I32	= 67,
    ARM_ATOMIC_LOAD_NAND_I64	= 68,
    ARM_ATOMIC_LOAD_NAND_I8	= 69,
    ARM_ATOMIC_LOAD_OR_I16	= 70,
    ARM_ATOMIC_LOAD_OR_I32	= 71,
    ARM_ATOMIC_LOAD_OR_I64	= 72,
    ARM_ATOMIC_LOAD_OR_I8	= 73,
    ARM_ATOMIC_LOAD_SUB_I16	= 74,
    ARM_ATOMIC_LOAD_SUB_I32	= 75,
    ARM_ATOMIC_LOAD_SUB_I64	= 76,
    ARM_ATOMIC_LOAD_SUB_I8	= 77,
    ARM_ATOMIC_LOAD_UMAX_I16	= 78,
    ARM_ATOMIC_LOAD_UMAX_I32	= 79,
    ARM_ATOMIC_LOAD_UMAX_I64	= 80,
    ARM_ATOMIC_LOAD_UMAX_I8	= 81,
    ARM_ATOMIC_LOAD_UMIN_I16	= 82,
    ARM_ATOMIC_LOAD_UMIN_I32	= 83,
    ARM_ATOMIC_LOAD_UMIN_I64	= 84,
    ARM_ATOMIC_LOAD_UMIN_I8	= 85,
    ARM_ATOMIC_LOAD_XOR_I16	= 86,
    ARM_ATOMIC_LOAD_XOR_I32	= 87,
    ARM_ATOMIC_LOAD_XOR_I64	= 88,
    ARM_ATOMIC_LOAD_XOR_I8	= 89,
    ARM_ATOMIC_STORE_I64	= 90,
    ARM_ATOMIC_SWAP_I16	= 91,
    ARM_ATOMIC_SWAP_I32	= 92,
    ARM_ATOMIC_SWAP_I64	= 93,
    ARM_ATOMIC_SWAP_I8	= 94,
    ARM_B	= 95,
    ARM_BCCZi64	= 96,
    ARM_BCCi64	= 97,
    ARM_BFC	= 98,
    ARM_BFI	= 99,
    ARM_BICri	= 100,
    ARM_BICrr	= 101,
    ARM_BICrsi	= 102,
    ARM_BICrsr	= 103,
    ARM_BKPT	= 104,
    ARM_BL	= 105,
    ARM_BLX	= 106,
    ARM_BLX_pred	= 107,
    ARM_BLXi	= 108,
    ARM_BL_pred	= 109,
    ARM_BMOVPCB_CALL	= 110,
    ARM_BMOVPCRX_CALL	= 111,
    ARM_BR_JTadd	= 112,
    ARM_BR_JTm	= 113,
    ARM_BR_JTr	= 114,
    ARM_BX	= 115,
    ARM_BXJ	= 116,
    ARM_BX_CALL	= 117,
    ARM_BX_RET	= 118,
    ARM_BX_pred	= 119,
    ARM_Bcc	= 120,
    ARM_CDP	= 121,
    ARM_CDP2	= 122,
    ARM_CLREX	= 123,
    ARM_CLZ	= 124,
    ARM_CMNri	= 125,
    ARM_CMNzrr	= 126,
    ARM_CMNzrsi	= 127,
    ARM_CMNzrsr	= 128,
    ARM_CMPri	= 129,
    ARM_CMPrr	= 130,
    ARM_CMPrsi	= 131,
    ARM_CMPrsr	= 132,
    ARM_CONSTPOOL_ENTRY	= 133,
    ARM_COPY_STRUCT_BYVAL_I32	= 134,
    ARM_CPS1p	= 135,
    ARM_CPS2p	= 136,
    ARM_CPS3p	= 137,
    ARM_CRC32B	= 138,
    ARM_CRC32CB	= 139,
    ARM_CRC32CH	= 140,
    ARM_CRC32CW	= 141,
    ARM_CRC32H	= 142,
    ARM_CRC32W	= 143,
    ARM_DBG	= 144,
    ARM_DMB	= 145,
    ARM_DSB	= 146,
    ARM_EORri	= 147,
    ARM_EORrr	= 148,
    ARM_EORrsi	= 149,
    ARM_EORrsr	= 150,
    ARM_FCONSTD	= 151,
    ARM_FCONSTS	= 152,
    ARM_FLDMXDB_UPD	= 153,
    ARM_FLDMXIA	= 154,
    ARM_FLDMXIA_UPD	= 155,
    ARM_FMSTAT	= 156,
    ARM_FSTMXDB_UPD	= 157,
    ARM_FSTMXIA	= 158,
    ARM_FSTMXIA_UPD	= 159,
    ARM_HINT	= 160,
    ARM_HLT	= 161,
    ARM_ISB	= 162,
    ARM_ITasm	= 163,
    ARM_Int_eh_sjlj_dispatchsetup	= 164,
    ARM_Int_eh_sjlj_longjmp	= 165,
    ARM_Int_eh_sjlj_setjmp	= 166,
    ARM_Int_eh_sjlj_setjmp_nofp	= 167,
    ARM_LDA	= 168,
    ARM_LDAB	= 169,
    ARM_LDAEX	= 170,
    ARM_LDAEXB	= 171,
    ARM_LDAEXD	= 172,
    ARM_LDAEXH	= 173,
    ARM_LDAH	= 174,
    ARM_LDC2L_OFFSET	= 175,
    ARM_LDC2L_OPTION	= 176,
    ARM_LDC2L_POST	= 177,
    ARM_LDC2L_PRE	= 178,
    ARM_LDC2_OFFSET	= 179,
    ARM_LDC2_OPTION	= 180,
    ARM_LDC2_POST	= 181,
    ARM_LDC2_PRE	= 182,
    ARM_LDCL_OFFSET	= 183,
    ARM_LDCL_OPTION	= 184,
    ARM_LDCL_POST	= 185,
    ARM_LDCL_PRE	= 186,
    ARM_LDC_OFFSET	= 187,
    ARM_LDC_OPTION	= 188,
    ARM_LDC_POST	= 189,
    ARM_LDC_PRE	= 190,
    ARM_LDMDA	= 191,
    ARM_LDMDA_UPD	= 192,
    ARM_LDMDB	= 193,
    ARM_LDMDB_UPD	= 194,
    ARM_LDMIA	= 195,
    ARM_LDMIA_RET	= 196,
    ARM_LDMIA_UPD	= 197,
    ARM_LDMIB	= 198,
    ARM_LDMIB_UPD	= 199,
    ARM_LDRBT_POST	= 200,
    ARM_LDRBT_POST_IMM	= 201,
    ARM_LDRBT_POST_REG	= 202,
    ARM_LDRB_POST_IMM	= 203,
    ARM_LDRB_POST_REG	= 204,
    ARM_LDRB_PRE_IMM	= 205,
    ARM_LDRB_PRE_REG	= 206,
    ARM_LDRBi12	= 207,
    ARM_LDRBrs	= 208,
    ARM_LDRD	= 209,
    ARM_LDRD_PAIR	= 210,
    ARM_LDRD_POST	= 211,
    ARM_LDRD_PRE	= 212,
    ARM_LDREX	= 213,
    ARM_LDREXB	= 214,
    ARM_LDREXD	= 215,
    ARM_LDREXH	= 216,
    ARM_LDRH	= 217,
    ARM_LDRHTi	= 218,
    ARM_LDRHTr	= 219,
    ARM_LDRH_POST	= 220,
    ARM_LDRH_PRE	= 221,
    ARM_LDRLIT_ga_abs	= 222,
    ARM_LDRLIT_ga_pcrel	= 223,
    ARM_LDRLIT_ga_pcrel_ldr	= 224,
    ARM_LDRSB	= 225,
    ARM_LDRSBTi	= 226,
    ARM_LDRSBTr	= 227,
    ARM_LDRSB_POST	= 228,
    ARM_LDRSB_PRE	= 229,
    ARM_LDRSH	= 230,
    ARM_LDRSHTi	= 231,
    ARM_LDRSHTr	= 232,
    ARM_LDRSH_POST	= 233,
    ARM_LDRSH_PRE	= 234,
    ARM_LDRT_POST	= 235,
    ARM_LDRT_POST_IMM	= 236,
    ARM_LDRT_POST_REG	= 237,
    ARM_LDR_POST_IMM	= 238,
    ARM_LDR_POST_REG	= 239,
    ARM_LDR_PRE_IMM	= 240,
    ARM_LDR_PRE_REG	= 241,
    ARM_LDRcp	= 242,
    ARM_LDRi12	= 243,
    ARM_LDRrs	= 244,
    ARM_LEApcrel	= 245,
    ARM_LEApcrelJT	= 246,
    ARM_LSLi	= 247,
    ARM_LSLr	= 248,
    ARM_LSRi	= 249,
    ARM_LSRr	= 250,
    ARM_MCR	= 251,
    ARM_MCR2	= 252,
    ARM_MCRR	= 253,
    ARM_MCRR2	= 254,
    ARM_MLA	= 255,
    ARM_MLAv5	= 256,
    ARM_MLS	= 257,
    ARM_MOVCCi	= 258,
    ARM_MOVCCi16	= 259,
    ARM_MOVCCi32imm	= 260,
    ARM_MOVCCr	= 261,
    ARM_MOVCCsi	= 262,
    ARM_MOVCCsr	= 263,
    ARM_MOVPCLR	= 264,
    ARM_MOVPCRX	= 265,
    ARM_MOVTi16	= 266,
    ARM_MOVTi16_ga_pcrel	= 267,
    ARM_MOV_ga_pcrel	= 268,
    ARM_MOV_ga_pcrel_ldr	= 269,
    ARM_MOVi	= 270,
    ARM_MOVi16	= 271,
    ARM_MOVi16_ga_pcrel	= 272,
    ARM_MOVi32imm	= 273,
    ARM_MOVr	= 274,
    ARM_MOVr_TC	= 275,
    ARM_MOVsi	= 276,
    ARM_MOVsr	= 277,
    ARM_MOVsra_flag	= 278,
    ARM_MOVsrl_flag	= 279,
    ARM_MRC	= 280,
    ARM_MRC2	= 281,
    ARM_MRRC	= 282,
    ARM_MRRC2	= 283,
    ARM_MRS	= 284,
    ARM_MRSsys	= 285,
    ARM_MSR	= 286,
    ARM_MSRi	= 287,
    ARM_MUL	= 288,
    ARM_MULv5	= 289,
    ARM_MVNCCi	= 290,
    ARM_MVNi	= 291,
    ARM_MVNr	= 292,
    ARM_MVNsi	= 293,
    ARM_MVNsr	= 294,
    ARM_ORRri	= 295,
    ARM_ORRrr	= 296,
    ARM_ORRrsi	= 297,
    ARM_ORRrsr	= 298,
    ARM_PICADD	= 299,
    ARM_PICLDR	= 300,
    ARM_PICLDRB	= 301,
    ARM_PICLDRH	= 302,
    ARM_PICLDRSB	= 303,
    ARM_PICLDRSH	= 304,
    ARM_PICSTR	= 305,
    ARM_PICSTRB	= 306,
    ARM_PICSTRH	= 307,
    ARM_PKHBT	= 308,
    ARM_PKHTB	= 309,
    ARM_PLDWi12	= 310,
    ARM_PLDWrs	= 311,
    ARM_PLDi12	= 312,
    ARM_PLDrs	= 313,
    ARM_PLIi12	= 314,
    ARM_PLIrs	= 315,
    ARM_QADD	= 316,
    ARM_QADD16	= 317,
    ARM_QADD8	= 318,
    ARM_QASX	= 319,
    ARM_QDADD	= 320,
    ARM_QDSUB	= 321,
    ARM_QSAX	= 322,
    ARM_QSUB	= 323,
    ARM_QSUB16	= 324,
    ARM_QSUB8	= 325,
    ARM_RBIT	= 326,
    ARM_REV	= 327,
    ARM_REV16	= 328,
    ARM_REVSH	= 329,
    ARM_RFEDA	= 330,
    ARM_RFEDA_UPD	= 331,
    ARM_RFEDB	= 332,
    ARM_RFEDB_UPD	= 333,
    ARM_RFEIA	= 334,
    ARM_RFEIA_UPD	= 335,
    ARM_RFEIB	= 336,
    ARM_RFEIB_UPD	= 337,
    ARM_RORi	= 338,
    ARM_RORr	= 339,
    ARM_RRX	= 340,
    ARM_RRXi	= 341,
    ARM_RSBSri	= 342,
    ARM_RSBSrsi	= 343,
    ARM_RSBSrsr	= 344,
    ARM_RSBri	= 345,
    ARM_RSBrr	= 346,
    ARM_RSBrsi	= 347,
    ARM_RSBrsr	= 348,
    ARM_RSCri	= 349,
    ARM_RSCrr	= 350,
    ARM_RSCrsi	= 351,
    ARM_RSCrsr	= 352,
    ARM_SADD16	= 353,
    ARM_SADD8	= 354,
    ARM_SASX	= 355,
    ARM_SBCri	= 356,
    ARM_SBCrr	= 357,
    ARM_SBCrsi	= 358,
    ARM_SBCrsr	= 359,
    ARM_SBFX	= 360,
    ARM_SDIV	= 361,
    ARM_SEL	= 362,
    ARM_SETEND	= 363,
    ARM_SHA1C	= 364,
    ARM_SHA1H	= 365,
    ARM_SHA1M	= 366,
    ARM_SHA1P	= 367,
    ARM_SHA1SU0	= 368,
    ARM_SHA1SU1	= 369,
    ARM_SHA256H	= 370,
    ARM_SHA256H2	= 371,
    ARM_SHA256SU0	= 372,
    ARM_SHA256SU1	= 373,
    ARM_SHADD16	= 374,
    ARM_SHADD8	= 375,
    ARM_SHASX	= 376,
    ARM_SHSAX	= 377,
    ARM_SHSUB16	= 378,
    ARM_SHSUB8	= 379,
    ARM_SMC	= 380,
    ARM_SMLABB	= 381,
    ARM_SMLABT	= 382,
    ARM_SMLAD	= 383,
    ARM_SMLADX	= 384,
    ARM_SMLAL	= 385,
    ARM_SMLALBB	= 386,
    ARM_SMLALBT	= 387,
    ARM_SMLALD	= 388,
    ARM_SMLALDX	= 389,
    ARM_SMLALTB	= 390,
    ARM_SMLALTT	= 391,
    ARM_SMLALv5	= 392,
    ARM_SMLATB	= 393,
    ARM_SMLATT	= 394,
    ARM_SMLAWB	= 395,
    ARM_SMLAWT	= 396,
    ARM_SMLSD	= 397,
    ARM_SMLSDX	= 398,
    ARM_SMLSLD	= 399,
    ARM_SMLSLDX	= 400,
    ARM_SMMLA	= 401,
    ARM_SMMLAR	= 402,
    ARM_SMMLS	= 403,
    ARM_SMMLSR	= 404,
    ARM_SMMUL	= 405,
    ARM_SMMULR	= 406,
    ARM_SMUAD	= 407,
    ARM_SMUADX	= 408,
    ARM_SMULBB	= 409,
    ARM_SMULBT	= 410,
    ARM_SMULL	= 411,
    ARM_SMULLv5	= 412,
    ARM_SMULTB	= 413,
    ARM_SMULTT	= 414,
    ARM_SMULWB	= 415,
    ARM_SMULWT	= 416,
    ARM_SMUSD	= 417,
    ARM_SMUSDX	= 418,
    ARM_SRSDA	= 419,
    ARM_SRSDA_UPD	= 420,
    ARM_SRSDB	= 421,
    ARM_SRSDB_UPD	= 422,
    ARM_SRSIA	= 423,
    ARM_SRSIA_UPD	= 424,
    ARM_SRSIB	= 425,
    ARM_SRSIB_UPD	= 426,
    ARM_SSAT	= 427,
    ARM_SSAT16	= 428,
    ARM_SSAX	= 429,
    ARM_SSUB16	= 430,
    ARM_SSUB8	= 431,
    ARM_STC2L_OFFSET	= 432,
    ARM_STC2L_OPTION	= 433,
    ARM_STC2L_POST	= 434,
    ARM_STC2L_PRE	= 435,
    ARM_STC2_OFFSET	= 436,
    ARM_STC2_OPTION	= 437,
    ARM_STC2_POST	= 438,
    ARM_STC2_PRE	= 439,
    ARM_STCL_OFFSET	= 440,
    ARM_STCL_OPTION	= 441,
    ARM_STCL_POST	= 442,
    ARM_STCL_PRE	= 443,
    ARM_STC_OFFSET	= 444,
    ARM_STC_OPTION	= 445,
    ARM_STC_POST	= 446,
    ARM_STC_PRE	= 447,
    ARM_STL	= 448,
    ARM_STLB	= 449,
    ARM_STLEX	= 450,
    ARM_STLEXB	= 451,
    ARM_STLEXD	= 452,
    ARM_STLEXH	= 453,
    ARM_STLH	= 454,
    ARM_STMDA	= 455,
    ARM_STMDA_UPD	= 456,
    ARM_STMDB	= 457,
    ARM_STMDB_UPD	= 458,
    ARM_STMIA	= 459,
    ARM_STMIA_UPD	= 460,
    ARM_STMIB	= 461,
    ARM_STMIB_UPD	= 462,
    ARM_STRBT_POST	= 463,
    ARM_STRBT_POST_IMM	= 464,
    ARM_STRBT_POST_REG	= 465,
    ARM_STRB_POST_IMM	= 466,
    ARM_STRB_POST_REG	= 467,
    ARM_STRB_PRE_IMM	= 468,
    ARM_STRB_PRE_REG	= 469,
    ARM_STRBi12	= 470,
    ARM_STRBi_preidx	= 471,
    ARM_STRBr_preidx	= 472,
    ARM_STRBrs	= 473,
    ARM_STRD	= 474,
    ARM_STRD_PAIR	= 475,
    ARM_STRD_POST	= 476,
    ARM_STRD_PRE	= 477,
    ARM_STREX	= 478,
    ARM_STREXB	= 479,
    ARM_STREXD	= 480,
    ARM_STREXH	= 481,
    ARM_STRH	= 482,
    ARM_STRHTi	= 483,
    ARM_STRHTr	= 484,
    ARM_STRH_POST	= 485,
    ARM_STRH_PRE	= 486,
    ARM_STRH_preidx	= 487,
    ARM_STRT_POST	= 488,
    ARM_STRT_POST_IMM	= 489,
    ARM_STRT_POST_REG	= 490,
    ARM_STR_POST_IMM	= 491,
    ARM_STR_POST_REG	= 492,
    ARM_STR_PRE_IMM	= 493,
    ARM_STR_PRE_REG	= 494,
    ARM_STRi12	= 495,
    ARM_STRi_preidx	= 496,
    ARM_STRr_preidx	= 497,
    ARM_STRrs	= 498,
    ARM_SUBS_PC_LR	= 499,
    ARM_SUBSri	= 500,
    ARM_SUBSrr	= 501,
    ARM_SUBSrsi	= 502,
    ARM_SUBSrsr	= 503,
    ARM_SUBri	= 504,
    ARM_SUBrr	= 505,
    ARM_SUBrsi	= 506,
    ARM_SUBrsr	= 507,
    ARM_SVC	= 508,
    ARM_SWP	= 509,
    ARM_SWPB	= 510,
    ARM_SXTAB	= 511,
    ARM_SXTAB16	= 512,
    ARM_SXTAH	= 513,
    ARM_SXTB	= 514,
    ARM_SXTB16	= 515,
    ARM_SXTH	= 516,
    ARM_TAILJMPd	= 517,
    ARM_TAILJMPr	= 518,
    ARM_TCRETURNdi	= 519,
    ARM_TCRETURNri	= 520,
    ARM_TEQri	= 521,
    ARM_TEQrr	= 522,
    ARM_TEQrsi	= 523,
    ARM_TEQrsr	= 524,
    ARM_TPsoft	= 525,
    ARM_TRAP	= 526,
    ARM_TRAPNaCl	= 527,
    ARM_TSTri	= 528,
    ARM_TSTrr	= 529,
    ARM_TSTrsi	= 530,
    ARM_TSTrsr	= 531,
    ARM_UADD16	= 532,
    ARM_UADD8	= 533,
    ARM_UASX	= 534,
    ARM_UBFX	= 535,
    ARM_UDIV	= 536,
    ARM_UHADD16	= 537,
    ARM_UHADD8	= 538,
    ARM_UHASX	= 539,
    ARM_UHSAX	= 540,
    ARM_UHSUB16	= 541,
    ARM_UHSUB8	= 542,
    ARM_UMAAL	= 543,
    ARM_UMLAL	= 544,
    ARM_UMLALv5	= 545,
    ARM_UMULL	= 546,
    ARM_UMULLv5	= 547,
    ARM_UQADD16	= 548,
    ARM_UQADD8	= 549,
    ARM_UQASX	= 550,
    ARM_UQSAX	= 551,
    ARM_UQSUB16	= 552,
    ARM_UQSUB8	= 553,
    ARM_USAD8	= 554,
    ARM_USADA8	= 555,
    ARM_USAT	= 556,
    ARM_USAT16	= 557,
    ARM_USAX	= 558,
    ARM_USUB16	= 559,
    ARM_USUB8	= 560,
    ARM_UXTAB	= 561,
    ARM_UXTAB16	= 562,
    ARM_UXTAH	= 563,
    ARM_UXTB	= 564,
    ARM_UXTB16	= 565,
    ARM_UXTH	= 566,
    ARM_VABALsv2i64	= 567,
    ARM_VABALsv4i32	= 568,
    ARM_VABALsv8i16	= 569,
    ARM_VABALuv2i64	= 570,
    ARM_VABALuv4i32	= 571,
    ARM_VABALuv8i16	= 572,
    ARM_VABAsv16i8	= 573,
    ARM_VABAsv2i32	= 574,
    ARM_VABAsv4i16	= 575,
    ARM_VABAsv4i32	= 576,
    ARM_VABAsv8i16	= 577,
    ARM_VABAsv8i8	= 578,
    ARM_VABAuv16i8	= 579,
    ARM_VABAuv2i32	= 580,
    ARM_VABAuv4i16	= 581,
    ARM_VABAuv4i32	= 582,
    ARM_VABAuv8i16	= 583,
    ARM_VABAuv8i8	= 584,
    ARM_VABDLsv2i64	= 585,
    ARM_VABDLsv4i32	= 586,
    ARM_VABDLsv8i16	= 587,
    ARM_VABDLuv2i64	= 588,
    ARM_VABDLuv4i32	= 589,
    ARM_VABDLuv8i16	= 590,
    ARM_VABDfd	= 591,
    ARM_VABDfq	= 592,
    ARM_VABDsv16i8	= 593,
    ARM_VABDsv2i32	= 594,
    ARM_VABDsv4i16	= 595,
    ARM_VABDsv4i32	= 596,
    ARM_VABDsv8i16	= 597,
    ARM_VABDsv8i8	= 598,
    ARM_VABDuv16i8	= 599,
    ARM_VABDuv2i32	= 600,
    ARM_VABDuv4i16	= 601,
    ARM_VABDuv4i32	= 602,
    ARM_VABDuv8i16	= 603,
    ARM_VABDuv8i8	= 604,
    ARM_VABSD	= 605,
    ARM_VABSS	= 606,
    ARM_VABSfd	= 607,
    ARM_VABSfq	= 608,
    ARM_VABSv16i8	= 609,
    ARM_VABSv2i32	= 610,
    ARM_VABSv4i16	= 611,
    ARM_VABSv4i32	= 612,
    ARM_VABSv8i16	= 613,
    ARM_VABSv8i8	= 614,
    ARM_VACGEd	= 615,
    ARM_VACGEq	= 616,
    ARM_VACGTd	= 617,
    ARM_VACGTq	= 618,
    ARM_VADDD	= 619,
    ARM_VADDHNv2i32	= 620,
    ARM_VADDHNv4i16	= 621,
    ARM_VADDHNv8i8	= 622,
    ARM_VADDLsv2i64	= 623,
    ARM_VADDLsv4i32	= 624,
    ARM_VADDLsv8i16	= 625,
    ARM_VADDLuv2i64	= 626,
    ARM_VADDLuv4i32	= 627,
    ARM_VADDLuv8i16	= 628,
    ARM_VADDS	= 629,
    ARM_VADDWsv2i64	= 630,
    ARM_VADDWsv4i32	= 631,
    ARM_VADDWsv8i16	= 632,
    ARM_VADDWuv2i64	= 633,
    ARM_VADDWuv4i32	= 634,
    ARM_VADDWuv8i16	= 635,
    ARM_VADDfd	= 636,
    ARM_VADDfq	= 637,
    ARM_VADDv16i8	= 638,
    ARM_VADDv1i64	= 639,
    ARM_VADDv2i32	= 640,
    ARM_VADDv2i64	= 641,
    ARM_VADDv4i16	= 642,
    ARM_VADDv4i32	= 643,
    ARM_VADDv8i16	= 644,
    ARM_VADDv8i8	= 645,
    ARM_VANDd	= 646,
    ARM_VANDq	= 647,
    ARM_VBICd	= 648,
    ARM_VBICiv2i32	= 649,
    ARM_VBICiv4i16	= 650,
    ARM_VBICiv4i32	= 651,
    ARM_VBICiv8i16	= 652,
    ARM_VBICq	= 653,
    ARM_VBIFd	= 654,
    ARM_VBIFq	= 655,
    ARM_VBITd	= 656,
    ARM_VBITq	= 657,
    ARM_VBSLd	= 658,
    ARM_VBSLq	= 659,
    ARM_VCEQfd	= 660,
    ARM_VCEQfq	= 661,
    ARM_VCEQv16i8	= 662,
    ARM_VCEQv2i32	= 663,
    ARM_VCEQv4i16	= 664,
    ARM_VCEQv4i32	= 665,
    ARM_VCEQv8i16	= 666,
    ARM_VCEQv8i8	= 667,
    ARM_VCEQzv16i8	= 668,
    ARM_VCEQzv2f32	= 669,
    ARM_VCEQzv2i32	= 670,
    ARM_VCEQzv4f32	= 671,
    ARM_VCEQzv4i16	= 672,
    ARM_VCEQzv4i32	= 673,
    ARM_VCEQzv8i16	= 674,
    ARM_VCEQzv8i8	= 675,
    ARM_VCGEfd	= 676,
    ARM_VCGEfq	= 677,
    ARM_VCGEsv16i8	= 678,
    ARM_VCGEsv2i32	= 679,
    ARM_VCGEsv4i16	= 680,
    ARM_VCGEsv4i32	= 681,
    ARM_VCGEsv8i16	= 682,
    ARM_VCGEsv8i8	= 683,
    ARM_VCGEuv16i8	= 684,
    ARM_VCGEuv2i32	= 685,
    ARM_VCGEuv4i16	= 686,
    ARM_VCGEuv4i32	= 687,
    ARM_VCGEuv8i16	= 688,
    ARM_VCGEuv8i8	= 689,
    ARM_VCGEzv16i8	= 690,
    ARM_VCGEzv2f32	= 691,
    ARM_VCGEzv2i32	= 692,
    ARM_VCGEzv4f32	= 693,
    ARM_VCGEzv4i16	= 694,
    ARM_VCGEzv4i32	= 695,
    ARM_VCGEzv8i16	= 696,
    ARM_VCGEzv8i8	= 697,
    ARM_VCGTfd	= 698,
    ARM_VCGTfq	= 699,
    ARM_VCGTsv16i8	= 700,
    ARM_VCGTsv2i32	= 701,
    ARM_VCGTsv4i16	= 702,
    ARM_VCGTsv4i32	= 703,
    ARM_VCGTsv8i16	= 704,
    ARM_VCGTsv8i8	= 705,
    ARM_VCGTuv16i8	= 706,
    ARM_VCGTuv2i32	= 707,
    ARM_VCGTuv4i16	= 708,
    ARM_VCGTuv4i32	= 709,
    ARM_VCGTuv8i16	= 710,
    ARM_VCGTuv8i8	= 711,
    ARM_VCGTzv16i8	= 712,
    ARM_VCGTzv2f32	= 713,
    ARM_VCGTzv2i32	= 714,
    ARM_VCGTzv4f32	= 715,
    ARM_VCGTzv4i16	= 716,
    ARM_VCGTzv4i32	= 717,
    ARM_VCGTzv8i16	= 718,
    ARM_VCGTzv8i8	= 719,
    ARM_VCLEzv16i8	= 720,
    ARM_VCLEzv2f32	= 721,
    ARM_VCLEzv2i32	= 722,
    ARM_VCLEzv4f32	= 723,
    ARM_VCLEzv4i16	= 724,
    ARM_VCLEzv4i32	= 725,
    ARM_VCLEzv8i16	= 726,
    ARM_VCLEzv8i8	= 727,
    ARM_VCLSv16i8	= 728,
    ARM_VCLSv2i32	= 729,
    ARM_VCLSv4i16	= 730,
    ARM_VCLSv4i32	= 731,
    ARM_VCLSv8i16	= 732,
    ARM_VCLSv8i8	= 733,
    ARM_VCLTzv16i8	= 734,
    ARM_VCLTzv2f32	= 735,
    ARM_VCLTzv2i32	= 736,
    ARM_VCLTzv4f32	= 737,
    ARM_VCLTzv4i16	= 738,
    ARM_VCLTzv4i32	= 739,
    ARM_VCLTzv8i16	= 740,
    ARM_VCLTzv8i8	= 741,
    ARM_VCLZv16i8	= 742,
    ARM_VCLZv2i32	= 743,
    ARM_VCLZv4i16	= 744,
    ARM_VCLZv4i32	= 745,
    ARM_VCLZv8i16	= 746,
    ARM_VCLZv8i8	= 747,
    ARM_VCMPD	= 748,
    ARM_VCMPED	= 749,
    ARM_VCMPES	= 750,
    ARM_VCMPEZD	= 751,
    ARM_VCMPEZS	= 752,
    ARM_VCMPS	= 753,
    ARM_VCMPZD	= 754,
    ARM_VCMPZS	= 755,
    ARM_VCNTd	= 756,
    ARM_VCNTq	= 757,
    ARM_VCVTANSD	= 758,
    ARM_VCVTANSQ	= 759,
    ARM_VCVTANUD	= 760,
    ARM_VCVTANUQ	= 761,
    ARM_VCVTASD	= 762,
    ARM_VCVTASS	= 763,
    ARM_VCVTAUD	= 764,
    ARM_VCVTAUS	= 765,
    ARM_VCVTBDH	= 766,
    ARM_VCVTBHD	= 767,
    ARM_VCVTBHS	= 768,
    ARM_VCVTBSH	= 769,
    ARM_VCVTDS	= 770,
    ARM_VCVTMNSD	= 771,
    ARM_VCVTMNSQ	= 772,
    ARM_VCVTMNUD	= 773,
    ARM_VCVTMNUQ	= 774,
    ARM_VCVTMSD	= 775,
    ARM_VCVTMSS	= 776,
    ARM_VCVTMUD	= 777,
    ARM_VCVTMUS	= 778,
    ARM_VCVTNNSD	= 779,
    ARM_VCVTNNSQ	= 780,
    ARM_VCVTNNUD	= 781,
    ARM_VCVTNNUQ	= 782,
    ARM_VCVTNSD	= 783,
    ARM_VCVTNSS	= 784,
    ARM_VCVTNUD	= 785,
    ARM_VCVTNUS	= 786,
    ARM_VCVTPNSD	= 787,
    ARM_VCVTPNSQ	= 788,
    ARM_VCVTPNUD	= 789,
    ARM_VCVTPNUQ	= 790,
    ARM_VCVTPSD	= 791,
    ARM_VCVTPSS	= 792,
    ARM_VCVTPUD	= 793,
    ARM_VCVTPUS	= 794,
    ARM_VCVTSD	= 795,
    ARM_VCVTTDH	= 796,
    ARM_VCVTTHD	= 797,
    ARM_VCVTTHS	= 798,
    ARM_VCVTTSH	= 799,
    ARM_VCVTf2h	= 800,
    ARM_VCVTf2sd	= 801,
    ARM_VCVTf2sq	= 802,
    ARM_VCVTf2ud	= 803,
    ARM_VCVTf2uq	= 804,
    ARM_VCVTf2xsd	= 805,
    ARM_VCVTf2xsq	= 806,
    ARM_VCVTf2xud	= 807,
    ARM_VCVTf2xuq	= 808,
    ARM_VCVTh2f	= 809,
    ARM_VCVTs2fd	= 810,
    ARM_VCVTs2fq	= 811,
    ARM_VCVTu2fd	= 812,
    ARM_VCVTu2fq	= 813,
    ARM_VCVTxs2fd	= 814,
    ARM_VCVTxs2fq	= 815,
    ARM_VCVTxu2fd	= 816,
    ARM_VCVTxu2fq	= 817,
    ARM_VDIVD	= 818,
    ARM_VDIVS	= 819,
    ARM_VDUP16d	= 820,
    ARM_VDUP16q	= 821,
    ARM_VDUP32d	= 822,
    ARM_VDUP32q	= 823,
    ARM_VDUP8d	= 824,
    ARM_VDUP8q	= 825,
    ARM_VDUPLN16d	= 826,
    ARM_VDUPLN16q	= 827,
    ARM_VDUPLN32d	= 828,
    ARM_VDUPLN32q	= 829,
    ARM_VDUPLN8d	= 830,
    ARM_VDUPLN8q	= 831,
    ARM_VDUPfdf	= 832,
    ARM_VDUPfqf	= 833,
    ARM_VEORd	= 834,
    ARM_VEORq	= 835,
    ARM_VEXTd16	= 836,
    ARM_VEXTd32	= 837,
    ARM_VEXTd8	= 838,
    ARM_VEXTq16	= 839,
    ARM_VEXTq32	= 840,
    ARM_VEXTq64	= 841,
    ARM_VEXTq8	= 842,
    ARM_VFMAD	= 843,
    ARM_VFMAS	= 844,
    ARM_VFMAfd	= 845,
    ARM_VFMAfq	= 846,
    ARM_VFMSD	= 847,
    ARM_VFMSS	= 848,
    ARM_VFMSfd	= 849,
    ARM_VFMSfq	= 850,
    ARM_VFNMAD	= 851,
    ARM_VFNMAS	= 852,
    ARM_VFNMSD	= 853,
    ARM_VFNMSS	= 854,
    ARM_VGETLNi32	= 855,
    ARM_VGETLNs16	= 856,
    ARM_VGETLNs8	= 857,
    ARM_VGETLNu16	= 858,
    ARM_VGETLNu8	= 859,
    ARM_VHADDsv16i8	= 860,
    ARM_VHADDsv2i32	= 861,
    ARM_VHADDsv4i16	= 862,
    ARM_VHADDsv4i32	= 863,
    ARM_VHADDsv8i16	= 864,
    ARM_VHADDsv8i8	= 865,
    ARM_VHADDuv16i8	= 866,
    ARM_VHADDuv2i32	= 867,
    ARM_VHADDuv4i16	= 868,
    ARM_VHADDuv4i32	= 869,
    ARM_VHADDuv8i16	= 870,
    ARM_VHADDuv8i8	= 871,
    ARM_VHSUBsv16i8	= 872,
    ARM_VHSUBsv2i32	= 873,
    ARM_VHSUBsv4i16	= 874,
    ARM_VHSUBsv4i32	= 875,
    ARM_VHSUBsv8i16	= 876,
    ARM_VHSUBsv8i8	= 877,
    ARM_VHSUBuv16i8	= 878,
    ARM_VHSUBuv2i32	= 879,
    ARM_VHSUBuv4i16	= 880,
    ARM_VHSUBuv4i32	= 881,
    ARM_VHSUBuv8i16	= 882,
    ARM_VHSUBuv8i8	= 883,
    ARM_VLD1DUPd16	= 884,
    ARM_VLD1DUPd16wb_fixed	= 885,
    ARM_VLD1DUPd16wb_register	= 886,
    ARM_VLD1DUPd32	= 887,
    ARM_VLD1DUPd32wb_fixed	= 888,
    ARM_VLD1DUPd32wb_register	= 889,
    ARM_VLD1DUPd8	= 890,
    ARM_VLD1DUPd8wb_fixed	= 891,
    ARM_VLD1DUPd8wb_register	= 892,
    ARM_VLD1DUPq16	= 893,
    ARM_VLD1DUPq16wb_fixed	= 894,
    ARM_VLD1DUPq16wb_register	= 895,
    ARM_VLD1DUPq32	= 896,
    ARM_VLD1DUPq32wb_fixed	= 897,
    ARM_VLD1DUPq32wb_register	= 898,
    ARM_VLD1DUPq8	= 899,
    ARM_VLD1DUPq8wb_fixed	= 900,
    ARM_VLD1DUPq8wb_register	= 901,
    ARM_VLD1LNd16	= 902,
    ARM_VLD1LNd16_UPD	= 903,
    ARM_VLD1LNd32	= 904,
    ARM_VLD1LNd32_UPD	= 905,
    ARM_VLD1LNd8	= 906,
    ARM_VLD1LNd8_UPD	= 907,
    ARM_VLD1LNdAsm_16	= 908,
    ARM_VLD1LNdAsm_32	= 909,
    ARM_VLD1LNdAsm_8	= 910,
    ARM_VLD1LNdWB_fixed_Asm_16	= 911,
    ARM_VLD1LNdWB_fixed_Asm_32	= 912,
    ARM_VLD1LNdWB_fixed_Asm_8	= 913,
    ARM_VLD1LNdWB_register_Asm_16	= 914,
    ARM_VLD1LNdWB_register_Asm_32	= 915,
    ARM_VLD1LNdWB_register_Asm_8	= 916,
    ARM_VLD1LNq16Pseudo	= 917,
    ARM_VLD1LNq16Pseudo_UPD	= 918,
    ARM_VLD1LNq32Pseudo	= 919,
    ARM_VLD1LNq32Pseudo_UPD	= 920,
    ARM_VLD1LNq8Pseudo	= 921,
    ARM_VLD1LNq8Pseudo_UPD	= 922,
    ARM_VLD1d16	= 923,
    ARM_VLD1d16Q	= 924,
    ARM_VLD1d16Qwb_fixed	= 925,
    ARM_VLD1d16Qwb_register	= 926,
    ARM_VLD1d16T	= 927,
    ARM_VLD1d16Twb_fixed	= 928,
    ARM_VLD1d16Twb_register	= 929,
    ARM_VLD1d16wb_fixed	= 930,
    ARM_VLD1d16wb_register	= 931,
    ARM_VLD1d32	= 932,
    ARM_VLD1d32Q	= 933,
    ARM_VLD1d32Qwb_fixed	= 934,
    ARM_VLD1d32Qwb_register	= 935,
    ARM_VLD1d32T	= 936,
    ARM_VLD1d32Twb_fixed	= 937,
    ARM_VLD1d32Twb_register	= 938,
    ARM_VLD1d32wb_fixed	= 939,
    ARM_VLD1d32wb_register	= 940,
    ARM_VLD1d64	= 941,
    ARM_VLD1d64Q	= 942,
    ARM_VLD1d64QPseudo	= 943,
    ARM_VLD1d64Qwb_fixed	= 944,
    ARM_VLD1d64Qwb_register	= 945,
    ARM_VLD1d64T	= 946,
    ARM_VLD1d64TPseudo	= 947,
    ARM_VLD1d64Twb_fixed	= 948,
    ARM_VLD1d64Twb_register	= 949,
    ARM_VLD1d64wb_fixed	= 950,
    ARM_VLD1d64wb_register	= 951,
    ARM_VLD1d8	= 952,
    ARM_VLD1d8Q	= 953,
    ARM_VLD1d8Qwb_fixed	= 954,
    ARM_VLD1d8Qwb_register	= 955,
    ARM_VLD1d8T	= 956,
    ARM_VLD1d8Twb_fixed	= 957,
    ARM_VLD1d8Twb_register	= 958,
    ARM_VLD1d8wb_fixed	= 959,
    ARM_VLD1d8wb_register	= 960,
    ARM_VLD1q16	= 961,
    ARM_VLD1q16wb_fixed	= 962,
    ARM_VLD1q16wb_register	= 963,
    ARM_VLD1q32	= 964,
    ARM_VLD1q32wb_fixed	= 965,
    ARM_VLD1q32wb_register	= 966,
    ARM_VLD1q64	= 967,
    ARM_VLD1q64wb_fixed	= 968,
    ARM_VLD1q64wb_register	= 969,
    ARM_VLD1q8	= 970,
    ARM_VLD1q8wb_fixed	= 971,
    ARM_VLD1q8wb_register	= 972,
    ARM_VLD2DUPd16	= 973,
    ARM_VLD2DUPd16wb_fixed	= 974,
    ARM_VLD2DUPd16wb_register	= 975,
    ARM_VLD2DUPd16x2	= 976,
    ARM_VLD2DUPd16x2wb_fixed	= 977,
    ARM_VLD2DUPd16x2wb_register	= 978,
    ARM_VLD2DUPd32	= 979,
    ARM_VLD2DUPd32wb_fixed	= 980,
    ARM_VLD2DUPd32wb_register	= 981,
    ARM_VLD2DUPd32x2	= 982,
    ARM_VLD2DUPd32x2wb_fixed	= 983,
    ARM_VLD2DUPd32x2wb_register	= 984,
    ARM_VLD2DUPd8	= 985,
    ARM_VLD2DUPd8wb_fixed	= 986,
    ARM_VLD2DUPd8wb_register	= 987,
    ARM_VLD2DUPd8x2	= 988,
    ARM_VLD2DUPd8x2wb_fixed	= 989,
    ARM_VLD2DUPd8x2wb_register	= 990,
    ARM_VLD2LNd16	= 991,
    ARM_VLD2LNd16Pseudo	= 992,
    ARM_VLD2LNd16Pseudo_UPD	= 993,
    ARM_VLD2LNd16_UPD	= 994,
    ARM_VLD2LNd32	= 995,
    ARM_VLD2LNd32Pseudo	= 996,
    ARM_VLD2LNd32Pseudo_UPD	= 997,
    ARM_VLD2LNd32_UPD	= 998,
    ARM_VLD2LNd8	= 999,
    ARM_VLD2LNd8Pseudo	= 1000,
    ARM_VLD2LNd8Pseudo_UPD	= 1001,
    ARM_VLD2LNd8_UPD	= 1002,
    ARM_VLD2LNdAsm_16	= 1003,
    ARM_VLD2LNdAsm_32	= 1004,
    ARM_VLD2LNdAsm_8	= 1005,
    ARM_VLD2LNdWB_fixed_Asm_16	= 1006,
    ARM_VLD2LNdWB_fixed_Asm_32	= 1007,
    ARM_VLD2LNdWB_fixed_Asm_8	= 1008,
    ARM_VLD2LNdWB_register_Asm_16	= 1009,
    ARM_VLD2LNdWB_register_Asm_32	= 1010,
    ARM_VLD2LNdWB_register_Asm_8	= 1011,
    ARM_VLD2LNq16	= 1012,
    ARM_VLD2LNq16Pseudo	= 1013,
    ARM_VLD2LNq16Pseudo_UPD	= 1014,
    ARM_VLD2LNq16_UPD	= 1015,
    ARM_VLD2LNq32	= 1016,
    ARM_VLD2LNq32Pseudo	= 1017,
    ARM_VLD2LNq32Pseudo_UPD	= 1018,
    ARM_VLD2LNq32_UPD	= 1019,
    ARM_VLD2LNqAsm_16	= 1020,
    ARM_VLD2LNqAsm_32	= 1021,
    ARM_VLD2LNqWB_fixed_Asm_16	= 1022,
    ARM_VLD2LNqWB_fixed_Asm_32	= 1023,
    ARM_VLD2LNqWB_register_Asm_16	= 1024,
    ARM_VLD2LNqWB_register_Asm_32	= 1025,
    ARM_VLD2b16	= 1026,
    ARM_VLD2b16wb_fixed	= 1027,
    ARM_VLD2b16wb_register	= 1028,
    ARM_VLD2b32	= 1029,
    ARM_VLD2b32wb_fixed	= 1030,
    ARM_VLD2b32wb_register	= 1031,
    ARM_VLD2b8	= 1032,
    ARM_VLD2b8wb_fixed	= 1033,
    ARM_VLD2b8wb_register	= 1034,
    ARM_VLD2d16	= 1035,
    ARM_VLD2d16wb_fixed	= 1036,
    ARM_VLD2d16wb_register	= 1037,
    ARM_VLD2d32	= 1038,
    ARM_VLD2d32wb_fixed	= 1039,
    ARM_VLD2d32wb_register	= 1040,
    ARM_VLD2d8	= 1041,
    ARM_VLD2d8wb_fixed	= 1042,
    ARM_VLD2d8wb_register	= 1043,
    ARM_VLD2q16	= 1044,
    ARM_VLD2q16Pseudo	= 1045,
    ARM_VLD2q16PseudoWB_fixed	= 1046,
    ARM_VLD2q16PseudoWB_register	= 1047,
    ARM_VLD2q16wb_fixed	= 1048,
    ARM_VLD2q16wb_register	= 1049,
    ARM_VLD2q32	= 1050,
    ARM_VLD2q32Pseudo	= 1051,
    ARM_VLD2q32PseudoWB_fixed	= 1052,
    ARM_VLD2q32PseudoWB_register	= 1053,
    ARM_VLD2q32wb_fixed	= 1054,
    ARM_VLD2q32wb_register	= 1055,
    ARM_VLD2q8	= 1056,
    ARM_VLD2q8Pseudo	= 1057,
    ARM_VLD2q8PseudoWB_fixed	= 1058,
    ARM_VLD2q8PseudoWB_register	= 1059,
    ARM_VLD2q8wb_fixed	= 1060,
    ARM_VLD2q8wb_register	= 1061,
    ARM_VLD3DUPd16	= 1062,
    ARM_VLD3DUPd16Pseudo	= 1063,
    ARM_VLD3DUPd16Pseudo_UPD	= 1064,
    ARM_VLD3DUPd16_UPD	= 1065,
    ARM_VLD3DUPd32	= 1066,
    ARM_VLD3DUPd32Pseudo	= 1067,
    ARM_VLD3DUPd32Pseudo_UPD	= 1068,
    ARM_VLD3DUPd32_UPD	= 1069,
    ARM_VLD3DUPd8	= 1070,
    ARM_VLD3DUPd8Pseudo	= 1071,
    ARM_VLD3DUPd8Pseudo_UPD	= 1072,
    ARM_VLD3DUPd8_UPD	= 1073,
    ARM_VLD3DUPdAsm_16	= 1074,
    ARM_VLD3DUPdAsm_32	= 1075,
    ARM_VLD3DUPdAsm_8	= 1076,
    ARM_VLD3DUPdWB_fixed_Asm_16	= 1077,
    ARM_VLD3DUPdWB_fixed_Asm_32	= 1078,
    ARM_VLD3DUPdWB_fixed_Asm_8	= 1079,
    ARM_VLD3DUPdWB_register_Asm_16	= 1080,
    ARM_VLD3DUPdWB_register_Asm_32	= 1081,
    ARM_VLD3DUPdWB_register_Asm_8	= 1082,
    ARM_VLD3DUPq16	= 1083,
    ARM_VLD3DUPq16_UPD	= 1084,
    ARM_VLD3DUPq32	= 1085,
    ARM_VLD3DUPq32_UPD	= 1086,
    ARM_VLD3DUPq8	= 1087,
    ARM_VLD3DUPq8_UPD	= 1088,
    ARM_VLD3DUPqAsm_16	= 1089,
    ARM_VLD3DUPqAsm_32	= 1090,
    ARM_VLD3DUPqAsm_8	= 1091,
    ARM_VLD3DUPqWB_fixed_Asm_16	= 1092,
    ARM_VLD3DUPqWB_fixed_Asm_32	= 1093,
    ARM_VLD3DUPqWB_fixed_Asm_8	= 1094,
    ARM_VLD3DUPqWB_register_Asm_16	= 1095,
    ARM_VLD3DUPqWB_register_Asm_32	= 1096,
    ARM_VLD3DUPqWB_register_Asm_8	= 1097,
    ARM_VLD3LNd16	= 1098,
    ARM_VLD3LNd16Pseudo	= 1099,
    ARM_VLD3LNd16Pseudo_UPD	= 1100,
    ARM_VLD3LNd16_UPD	= 1101,
    ARM_VLD3LNd32	= 1102,
    ARM_VLD3LNd32Pseudo	= 1103,
    ARM_VLD3LNd32Pseudo_UPD	= 1104,
    ARM_VLD3LNd32_UPD	= 1105,
    ARM_VLD3LNd8	= 1106,
    ARM_VLD3LNd8Pseudo	= 1107,
    ARM_VLD3LNd8Pseudo_UPD	= 1108,
    ARM_VLD3LNd8_UPD	= 1109,
    ARM_VLD3LNdAsm_16	= 1110,
    ARM_VLD3LNdAsm_32	= 1111,
    ARM_VLD3LNdAsm_8	= 1112,
    ARM_VLD3LNdWB_fixed_Asm_16	= 1113,
    ARM_VLD3LNdWB_fixed_Asm_32	= 1114,
    ARM_VLD3LNdWB_fixed_Asm_8	= 1115,
    ARM_VLD3LNdWB_register_Asm_16	= 1116,
    ARM_VLD3LNdWB_register_Asm_32	= 1117,
    ARM_VLD3LNdWB_register_Asm_8	= 1118,
    ARM_VLD3LNq16	= 1119,
    ARM_VLD3LNq16Pseudo	= 1120,
    ARM_VLD3LNq16Pseudo_UPD	= 1121,
    ARM_VLD3LNq16_UPD	= 1122,
    ARM_VLD3LNq32	= 1123,
    ARM_VLD3LNq32Pseudo	= 1124,
    ARM_VLD3LNq32Pseudo_UPD	= 1125,
    ARM_VLD3LNq32_UPD	= 1126,
    ARM_VLD3LNqAsm_16	= 1127,
    ARM_VLD3LNqAsm_32	= 1128,
    ARM_VLD3LNqWB_fixed_Asm_16	= 1129,
    ARM_VLD3LNqWB_fixed_Asm_32	= 1130,
    ARM_VLD3LNqWB_register_Asm_16	= 1131,
    ARM_VLD3LNqWB_register_Asm_32	= 1132,
    ARM_VLD3d16	= 1133,
    ARM_VLD3d16Pseudo	= 1134,
    ARM_VLD3d16Pseudo_UPD	= 1135,
    ARM_VLD3d16_UPD	= 1136,
    ARM_VLD3d32	= 1137,
    ARM_VLD3d32Pseudo	= 1138,
    ARM_VLD3d32Pseudo_UPD	= 1139,
    ARM_VLD3d32_UPD	= 1140,
    ARM_VLD3d8	= 1141,
    ARM_VLD3d8Pseudo	= 1142,
    ARM_VLD3d8Pseudo_UPD	= 1143,
    ARM_VLD3d8_UPD	= 1144,
    ARM_VLD3dAsm_16	= 1145,
    ARM_VLD3dAsm_32	= 1146,
    ARM_VLD3dAsm_8	= 1147,
    ARM_VLD3dWB_fixed_Asm_16	= 1148,
    ARM_VLD3dWB_fixed_Asm_32	= 1149,
    ARM_VLD3dWB_fixed_Asm_8	= 1150,
    ARM_VLD3dWB_register_Asm_16	= 1151,
    ARM_VLD3dWB_register_Asm_32	= 1152,
    ARM_VLD3dWB_register_Asm_8	= 1153,
    ARM_VLD3q16	= 1154,
    ARM_VLD3q16Pseudo_UPD	= 1155,
    ARM_VLD3q16_UPD	= 1156,
    ARM_VLD3q16oddPseudo	= 1157,
    ARM_VLD3q16oddPseudo_UPD	= 1158,
    ARM_VLD3q32	= 1159,
    ARM_VLD3q32Pseudo_UPD	= 1160,
    ARM_VLD3q32_UPD	= 1161,
    ARM_VLD3q32oddPseudo	= 1162,
    ARM_VLD3q32oddPseudo_UPD	= 1163,
    ARM_VLD3q8	= 1164,
    ARM_VLD3q8Pseudo_UPD	= 1165,
    ARM_VLD3q8_UPD	= 1166,
    ARM_VLD3q8oddPseudo	= 1167,
    ARM_VLD3q8oddPseudo_UPD	= 1168,
    ARM_VLD3qAsm_16	= 1169,
    ARM_VLD3qAsm_32	= 1170,
    ARM_VLD3qAsm_8	= 1171,
    ARM_VLD3qWB_fixed_Asm_16	= 1172,
    ARM_VLD3qWB_fixed_Asm_32	= 1173,
    ARM_VLD3qWB_fixed_Asm_8	= 1174,
    ARM_VLD3qWB_register_Asm_16	= 1175,
    ARM_VLD3qWB_register_Asm_32	= 1176,
    ARM_VLD3qWB_register_Asm_8	= 1177,
    ARM_VLD4DUPd16	= 1178,
    ARM_VLD4DUPd16Pseudo	= 1179,
    ARM_VLD4DUPd16Pseudo_UPD	= 1180,
    ARM_VLD4DUPd16_UPD	= 1181,
    ARM_VLD4DUPd32	= 1182,
    ARM_VLD4DUPd32Pseudo	= 1183,
    ARM_VLD4DUPd32Pseudo_UPD	= 1184,
    ARM_VLD4DUPd32_UPD	= 1185,
    ARM_VLD4DUPd8	= 1186,
    ARM_VLD4DUPd8Pseudo	= 1187,
    ARM_VLD4DUPd8Pseudo_UPD	= 1188,
    ARM_VLD4DUPd8_UPD	= 1189,
    ARM_VLD4DUPdAsm_16	= 1190,
    ARM_VLD4DUPdAsm_32	= 1191,
    ARM_VLD4DUPdAsm_8	= 1192,
    ARM_VLD4DUPdWB_fixed_Asm_16	= 1193,
    ARM_VLD4DUPdWB_fixed_Asm_32	= 1194,
    ARM_VLD4DUPdWB_fixed_Asm_8	= 1195,
    ARM_VLD4DUPdWB_register_Asm_16	= 1196,
    ARM_VLD4DUPdWB_register_Asm_32	= 1197,
    ARM_VLD4DUPdWB_register_Asm_8	= 1198,
    ARM_VLD4DUPq16	= 1199,
    ARM_VLD4DUPq16_UPD	= 1200,
    ARM_VLD4DUPq32	= 1201,
    ARM_VLD4DUPq32_UPD	= 1202,
    ARM_VLD4DUPq8	= 1203,
    ARM_VLD4DUPq8_UPD	= 1204,
    ARM_VLD4DUPqAsm_16	= 1205,
    ARM_VLD4DUPqAsm_32	= 1206,
    ARM_VLD4DUPqAsm_8	= 1207,
    ARM_VLD4DUPqWB_fixed_Asm_16	= 1208,
    ARM_VLD4DUPqWB_fixed_Asm_32	= 1209,
    ARM_VLD4DUPqWB_fixed_Asm_8	= 1210,
    ARM_VLD4DUPqWB_register_Asm_16	= 1211,
    ARM_VLD4DUPqWB_register_Asm_32	= 1212,
    ARM_VLD4DUPqWB_register_Asm_8	= 1213,
    ARM_VLD4LNd16	= 1214,
    ARM_VLD4LNd16Pseudo	= 1215,
    ARM_VLD4LNd16Pseudo_UPD	= 1216,
    ARM_VLD4LNd16_UPD	= 1217,
    ARM_VLD4LNd32	= 1218,
    ARM_VLD4LNd32Pseudo	= 1219,
    ARM_VLD4LNd32Pseudo_UPD	= 1220,
    ARM_VLD4LNd32_UPD	= 1221,
    ARM_VLD4LNd8	= 1222,
    ARM_VLD4LNd8Pseudo	= 1223,
    ARM_VLD4LNd8Pseudo_UPD	= 1224,
    ARM_VLD4LNd8_UPD	= 1225,
    ARM_VLD4LNdAsm_16	= 1226,
    ARM_VLD4LNdAsm_32	= 1227,
    ARM_VLD4LNdAsm_8	= 1228,
    ARM_VLD4LNdWB_fixed_Asm_16	= 1229,
    ARM_VLD4LNdWB_fixed_Asm_32	= 1230,
    ARM_VLD4LNdWB_fixed_Asm_8	= 1231,
    ARM_VLD4LNdWB_register_Asm_16	= 1232,
    ARM_VLD4LNdWB_register_Asm_32	= 1233,
    ARM_VLD4LNdWB_register_Asm_8	= 1234,
    ARM_VLD4LNq16	= 1235,
    ARM_VLD4LNq16Pseudo	= 1236,
    ARM_VLD4LNq16Pseudo_UPD	= 1237,
    ARM_VLD4LNq16_UPD	= 1238,
    ARM_VLD4LNq32	= 1239,
    ARM_VLD4LNq32Pseudo	= 1240,
    ARM_VLD4LNq32Pseudo_UPD	= 1241,
    ARM_VLD4LNq32_UPD	= 1242,
    ARM_VLD4LNqAsm_16	= 1243,
    ARM_VLD4LNqAsm_32	= 1244,
    ARM_VLD4LNqWB_fixed_Asm_16	= 1245,
    ARM_VLD4LNqWB_fixed_Asm_32	= 1246,
    ARM_VLD4LNqWB_register_Asm_16	= 1247,
    ARM_VLD4LNqWB_register_Asm_32	= 1248,
    ARM_VLD4d16	= 1249,
    ARM_VLD4d16Pseudo	= 1250,
    ARM_VLD4d16Pseudo_UPD	= 1251,
    ARM_VLD4d16_UPD	= 1252,
    ARM_VLD4d32	= 1253,
    ARM_VLD4d32Pseudo	= 1254,
    ARM_VLD4d32Pseudo_UPD	= 1255,
    ARM_VLD4d32_UPD	= 1256,
    ARM_VLD4d8	= 1257,
    ARM_VLD4d8Pseudo	= 1258,
    ARM_VLD4d8Pseudo_UPD	= 1259,
    ARM_VLD4d8_UPD	= 1260,
    ARM_VLD4dAsm_16	= 1261,
    ARM_VLD4dAsm_32	= 1262,
    ARM_VLD4dAsm_8	= 1263,
    ARM_VLD4dWB_fixed_Asm_16	= 1264,
    ARM_VLD4dWB_fixed_Asm_32	= 1265,
    ARM_VLD4dWB_fixed_Asm_8	= 1266,
    ARM_VLD4dWB_register_Asm_16	= 1267,
    ARM_VLD4dWB_register_Asm_32	= 1268,
    ARM_VLD4dWB_register_Asm_8	= 1269,
    ARM_VLD4q16	= 1270,
    ARM_VLD4q16Pseudo_UPD	= 1271,
    ARM_VLD4q16_UPD	= 1272,
    ARM_VLD4q16oddPseudo	= 1273,
    ARM_VLD4q16oddPseudo_UPD	= 1274,
    ARM_VLD4q32	= 1275,
    ARM_VLD4q32Pseudo_UPD	= 1276,
    ARM_VLD4q32_UPD	= 1277,
    ARM_VLD4q32oddPseudo	= 1278,
    ARM_VLD4q32oddPseudo_UPD	= 1279,
    ARM_VLD4q8	= 1280,
    ARM_VLD4q8Pseudo_UPD	= 1281,
    ARM_VLD4q8_UPD	= 1282,
    ARM_VLD4q8oddPseudo	= 1283,
    ARM_VLD4q8oddPseudo_UPD	= 1284,
    ARM_VLD4qAsm_16	= 1285,
    ARM_VLD4qAsm_32	= 1286,
    ARM_VLD4qAsm_8	= 1287,
    ARM_VLD4qWB_fixed_Asm_16	= 1288,
    ARM_VLD4qWB_fixed_Asm_32	= 1289,
    ARM_VLD4qWB_fixed_Asm_8	= 1290,
    ARM_VLD4qWB_register_Asm_16	= 1291,
    ARM_VLD4qWB_register_Asm_32	= 1292,
    ARM_VLD4qWB_register_Asm_8	= 1293,
    ARM_VLDMDDB_UPD	= 1294,
    ARM_VLDMDIA	= 1295,
    ARM_VLDMDIA_UPD	= 1296,
    ARM_VLDMQIA	= 1297,
    ARM_VLDMSDB_UPD	= 1298,
    ARM_VLDMSIA	= 1299,
    ARM_VLDMSIA_UPD	= 1300,
    ARM_VLDRD	= 1301,
    ARM_VLDRS	= 1302,
    ARM_VMAXNMD	= 1303,
    ARM_VMAXNMND	= 1304,
    ARM_VMAXNMNQ	= 1305,
    ARM_VMAXNMS	= 1306,
    ARM_VMAXfd	= 1307,
    ARM_VMAXfq	= 1308,
    ARM_VMAXsv16i8	= 1309,
    ARM_VMAXsv2i32	= 1310,
    ARM_VMAXsv4i16	= 1311,
    ARM_VMAXsv4i32	= 1312,
    ARM_VMAXsv8i16	= 1313,
    ARM_VMAXsv8i8	= 1314,
    ARM_VMAXuv16i8	= 1315,
    ARM_VMAXuv2i32	= 1316,
    ARM_VMAXuv4i16	= 1317,
    ARM_VMAXuv4i32	= 1318,
    ARM_VMAXuv8i16	= 1319,
    ARM_VMAXuv8i8	= 1320,
    ARM_VMINNMD	= 1321,
    ARM_VMINNMND	= 1322,
    ARM_VMINNMNQ	= 1323,
    ARM_VMINNMS	= 1324,
    ARM_VMINfd	= 1325,
    ARM_VMINfq	= 1326,
    ARM_VMINsv16i8	= 1327,
    ARM_VMINsv2i32	= 1328,
    ARM_VMINsv4i16	= 1329,
    ARM_VMINsv4i32	= 1330,
    ARM_VMINsv8i16	= 1331,
    ARM_VMINsv8i8	= 1332,
    ARM_VMINuv16i8	= 1333,
    ARM_VMINuv2i32	= 1334,
    ARM_VMINuv4i16	= 1335,
    ARM_VMINuv4i32	= 1336,
    ARM_VMINuv8i16	= 1337,
    ARM_VMINuv8i8	= 1338,
    ARM_VMLAD	= 1339,
    ARM_VMLALslsv2i32	= 1340,
    ARM_VMLALslsv4i16	= 1341,
    ARM_VMLALsluv2i32	= 1342,
    ARM_VMLALsluv4i16	= 1343,
    ARM_VMLALsv2i64	= 1344,
    ARM_VMLALsv4i32	= 1345,
    ARM_VMLALsv8i16	= 1346,
    ARM_VMLALuv2i64	= 1347,
    ARM_VMLALuv4i32	= 1348,
    ARM_VMLALuv8i16	= 1349,
    ARM_VMLAS	= 1350,
    ARM_VMLAfd	= 1351,
    ARM_VMLAfq	= 1352,
    ARM_VMLAslfd	= 1353,
    ARM_VMLAslfq	= 1354,
    ARM_VMLAslv2i32	= 1355,
    ARM_VMLAslv4i16	= 1356,
    ARM_VMLAslv4i32	= 1357,
    ARM_VMLAslv8i16	= 1358,
    ARM_VMLAv16i8	= 1359,
    ARM_VMLAv2i32	= 1360,
    ARM_VMLAv4i16	= 1361,
    ARM_VMLAv4i32	= 1362,
    ARM_VMLAv8i16	= 1363,
    ARM_VMLAv8i8	= 1364,
    ARM_VMLSD	= 1365,
    ARM_VMLSLslsv2i32	= 1366,
    ARM_VMLSLslsv4i16	= 1367,
    ARM_VMLSLsluv2i32	= 1368,
    ARM_VMLSLsluv4i16	= 1369,
    ARM_VMLSLsv2i64	= 1370,
    ARM_VMLSLsv4i32	= 1371,
    ARM_VMLSLsv8i16	= 1372,
    ARM_VMLSLuv2i64	= 1373,
    ARM_VMLSLuv4i32	= 1374,
    ARM_VMLSLuv8i16	= 1375,
    ARM_VMLSS	= 1376,
    ARM_VMLSfd	= 1377,
    ARM_VMLSfq	= 1378,
    ARM_VMLSslfd	= 1379,
    ARM_VMLSslfq	= 1380,
    ARM_VMLSslv2i32	= 1381,
    ARM_VMLSslv4i16	= 1382,
    ARM_VMLSslv4i32	= 1383,
    ARM_VMLSslv8i16	= 1384,
    ARM_VMLSv16i8	= 1385,
    ARM_VMLSv2i32	= 1386,
    ARM_VMLSv4i16	= 1387,
    ARM_VMLSv4i32	= 1388,
    ARM_VMLSv8i16	= 1389,
    ARM_VMLSv8i8	= 1390,
    ARM_VMOVD	= 1391,
    ARM_VMOVDRR	= 1392,
    ARM_VMOVDcc	= 1393,
    ARM_VMOVLsv2i64	= 1394,
    ARM_VMOVLsv4i32	= 1395,
    ARM_VMOVLsv8i16	= 1396,
    ARM_VMOVLuv2i64	= 1397,
    ARM_VMOVLuv4i32	= 1398,
    ARM_VMOVLuv8i16	= 1399,
    ARM_VMOVNv2i32	= 1400,
    ARM_VMOVNv4i16	= 1401,
    ARM_VMOVNv8i8	= 1402,
    ARM_VMOVRRD	= 1403,
    ARM_VMOVRRS	= 1404,
    ARM_VMOVRS	= 1405,
    ARM_VMOVS	= 1406,
    ARM_VMOVSR	= 1407,
    ARM_VMOVSRR	= 1408,
    ARM_VMOVScc	= 1409,
    ARM_VMOVv16i8	= 1410,
    ARM_VMOVv1i64	= 1411,
    ARM_VMOVv2f32	= 1412,
    ARM_VMOVv2i32	= 1413,
    ARM_VMOVv2i64	= 1414,
    ARM_VMOVv4f32	= 1415,
    ARM_VMOVv4i16	= 1416,
    ARM_VMOVv4i32	= 1417,
    ARM_VMOVv8i16	= 1418,
    ARM_VMOVv8i8	= 1419,
    ARM_VMRS	= 1420,
    ARM_VMRS_FPEXC	= 1421,
    ARM_VMRS_FPINST	= 1422,
    ARM_VMRS_FPINST2	= 1423,
    ARM_VMRS_FPSID	= 1424,
    ARM_VMRS_MVFR0	= 1425,
    ARM_VMRS_MVFR1	= 1426,
    ARM_VMRS_MVFR2	= 1427,
    ARM_VMSR	= 1428,
    ARM_VMSR_FPEXC	= 1429,
    ARM_VMSR_FPINST	= 1430,
    ARM_VMSR_FPINST2	= 1431,
    ARM_VMSR_FPSID	= 1432,
    ARM_VMULD	= 1433,
    ARM_VMULLp64	= 1434,
    ARM_VMULLp8	= 1435,
    ARM_VMULLslsv2i32	= 1436,
    ARM_VMULLslsv4i16	= 1437,
    ARM_VMULLsluv2i32	= 1438,
    ARM_VMULLsluv4i16	= 1439,
    ARM_VMULLsv2i64	= 1440,
    ARM_VMULLsv4i32	= 1441,
    ARM_VMULLsv8i16	= 1442,
    ARM_VMULLuv2i64	= 1443,
    ARM_VMULLuv4i32	= 1444,
    ARM_VMULLuv8i16	= 1445,
    ARM_VMULS	= 1446,
    ARM_VMULfd	= 1447,
    ARM_VMULfq	= 1448,
    ARM_VMULpd	= 1449,
    ARM_VMULpq	= 1450,
    ARM_VMULslfd	= 1451,
    ARM_VMULslfq	= 1452,
    ARM_VMULslv2i32	= 1453,
    ARM_VMULslv4i16	= 1454,
    ARM_VMULslv4i32	= 1455,
    ARM_VMULslv8i16	= 1456,
    ARM_VMULv16i8	= 1457,
    ARM_VMULv2i32	= 1458,
    ARM_VMULv4i16	= 1459,
    ARM_VMULv4i32	= 1460,
    ARM_VMULv8i16	= 1461,
    ARM_VMULv8i8	= 1462,
    ARM_VMVNd	= 1463,
    ARM_VMVNq	= 1464,
    ARM_VMVNv2i32	= 1465,
    ARM_VMVNv4i16	= 1466,
    ARM_VMVNv4i32	= 1467,
    ARM_VMVNv8i16	= 1468,
    ARM_VNEGD	= 1469,
    ARM_VNEGS	= 1470,
    ARM_VNEGf32q	= 1471,
    ARM_VNEGfd	= 1472,
    ARM_VNEGs16d	= 1473,
    ARM_VNEGs16q	= 1474,
    ARM_VNEGs32d	= 1475,
    ARM_VNEGs32q	= 1476,
    ARM_VNEGs8d	= 1477,
    ARM_VNEGs8q	= 1478,
    ARM_VNMLAD	= 1479,
    ARM_VNMLAS	= 1480,
    ARM_VNMLSD	= 1481,
    ARM_VNMLSS	= 1482,
    ARM_VNMULD	= 1483,
    ARM_VNMULS	= 1484,
    ARM_VORNd	= 1485,
    ARM_VORNq	= 1486,
    ARM_VORRd	= 1487,
    ARM_VORRiv2i32	= 1488,
    ARM_VORRiv4i16	= 1489,
    ARM_VORRiv4i32	= 1490,
    ARM_VORRiv8i16	= 1491,
    ARM_VORRq	= 1492,
    ARM_VPADALsv16i8	= 1493,
    ARM_VPADALsv2i32	= 1494,
    ARM_VPADALsv4i16	= 1495,
    ARM_VPADALsv4i32	= 1496,
    ARM_VPADALsv8i16	= 1497,
    ARM_VPADALsv8i8	= 1498,
    ARM_VPADALuv16i8	= 1499,
    ARM_VPADALuv2i32	= 1500,
    ARM_VPADALuv4i16	= 1501,
    ARM_VPADALuv4i32	= 1502,
    ARM_VPADALuv8i16	= 1503,
    ARM_VPADALuv8i8	= 1504,
    ARM_VPADDLsv16i8	= 1505,
    ARM_VPADDLsv2i32	= 1506,
    ARM_VPADDLsv4i16	= 1507,
    ARM_VPADDLsv4i32	= 1508,
    ARM_VPADDLsv8i16	= 1509,
    ARM_VPADDLsv8i8	= 1510,
    ARM_VPADDLuv16i8	= 1511,
    ARM_VPADDLuv2i32	= 1512,
    ARM_VPADDLuv4i16	= 1513,
    ARM_VPADDLuv4i32	= 1514,
    ARM_VPADDLuv8i16	= 1515,
    ARM_VPADDLuv8i8	= 1516,
    ARM_VPADDf	= 1517,
    ARM_VPADDi16	= 1518,
    ARM_VPADDi32	= 1519,
    ARM_VPADDi8	= 1520,
    ARM_VPMAXf	= 1521,
    ARM_VPMAXs16	= 1522,
    ARM_VPMAXs32	= 1523,
    ARM_VPMAXs8	= 1524,
    ARM_VPMAXu16	= 1525,
    ARM_VPMAXu32	= 1526,
    ARM_VPMAXu8	= 1527,
    ARM_VPMINf	= 1528,
    ARM_VPMINs16	= 1529,
    ARM_VPMINs32	= 1530,
    ARM_VPMINs8	= 1531,
    ARM_VPMINu16	= 1532,
    ARM_VPMINu32	= 1533,
    ARM_VPMINu8	= 1534,
    ARM_VQABSv16i8	= 1535,
    ARM_VQABSv2i32	= 1536,
    ARM_VQABSv4i16	= 1537,
    ARM_VQABSv4i32	= 1538,
    ARM_VQABSv8i16	= 1539,
    ARM_VQABSv8i8	= 1540,
    ARM_VQADDsv16i8	= 1541,
    ARM_VQADDsv1i64	= 1542,
    ARM_VQADDsv2i32	= 1543,
    ARM_VQADDsv2i64	= 1544,
    ARM_VQADDsv4i16	= 1545,
    ARM_VQADDsv4i32	= 1546,
    ARM_VQADDsv8i16	= 1547,
    ARM_VQADDsv8i8	= 1548,
    ARM_VQADDuv16i8	= 1549,
    ARM_VQADDuv1i64	= 1550,
    ARM_VQADDuv2i32	= 1551,
    ARM_VQADDuv2i64	= 1552,
    ARM_VQADDuv4i16	= 1553,
    ARM_VQADDuv4i32	= 1554,
    ARM_VQADDuv8i16	= 1555,
    ARM_VQADDuv8i8	= 1556,
    ARM_VQDMLALslv2i32	= 1557,
    ARM_VQDMLALslv4i16	= 1558,
    ARM_VQDMLALv2i64	= 1559,
    ARM_VQDMLALv4i32	= 1560,
    ARM_VQDMLSLslv2i32	= 1561,
    ARM_VQDMLSLslv4i16	= 1562,
    ARM_VQDMLSLv2i64	= 1563,
    ARM_VQDMLSLv4i32	= 1564,
    ARM_VQDMULHslv2i32	= 1565,
    ARM_VQDMULHslv4i16	= 1566,
    ARM_VQDMULHslv4i32	= 1567,
    ARM_VQDMULHslv8i16	= 1568,
    ARM_VQDMULHv2i32	= 1569,
    ARM_VQDMULHv4i16	= 1570,
    ARM_VQDMULHv4i32	= 1571,
    ARM_VQDMULHv8i16	= 1572,
    ARM_VQDMULLslv2i32	= 1573,
    ARM_VQDMULLslv4i16	= 1574,
    ARM_VQDMULLv2i64	= 1575,
    ARM_VQDMULLv4i32	= 1576,
    ARM_VQMOVNsuv2i32	= 1577,
    ARM_VQMOVNsuv4i16	= 1578,
    ARM_VQMOVNsuv8i8	= 1579,
    ARM_VQMOVNsv2i32	= 1580,
    ARM_VQMOVNsv4i16	= 1581,
    ARM_VQMOVNsv8i8	= 1582,
    ARM_VQMOVNuv2i32	= 1583,
    ARM_VQMOVNuv4i16	= 1584,
    ARM_VQMOVNuv8i8	= 1585,
    ARM_VQNEGv16i8	= 1586,
    ARM_VQNEGv2i32	= 1587,
    ARM_VQNEGv4i16	= 1588,
    ARM_VQNEGv4i32	= 1589,
    ARM_VQNEGv8i16	= 1590,
    ARM_VQNEGv8i8	= 1591,
    ARM_VQRDMULHslv2i32	= 1592,
    ARM_VQRDMULHslv4i16	= 1593,
    ARM_VQRDMULHslv4i32	= 1594,
    ARM_VQRDMULHslv8i16	= 1595,
    ARM_VQRDMULHv2i32	= 1596,
    ARM_VQRDMULHv4i16	= 1597,
    ARM_VQRDMULHv4i32	= 1598,
    ARM_VQRDMULHv8i16	= 1599,
    ARM_VQRSHLsv16i8	= 1600,
    ARM_VQRSHLsv1i64	= 1601,
    ARM_VQRSHLsv2i32	= 1602,
    ARM_VQRSHLsv2i64	= 1603,
    ARM_VQRSHLsv4i16	= 1604,
    ARM_VQRSHLsv4i32	= 1605,
    ARM_VQRSHLsv8i16	= 1606,
    ARM_VQRSHLsv8i8	= 1607,
    ARM_VQRSHLuv16i8	= 1608,
    ARM_VQRSHLuv1i64	= 1609,
    ARM_VQRSHLuv2i32	= 1610,
    ARM_VQRSHLuv2i64	= 1611,
    ARM_VQRSHLuv4i16	= 1612,
    ARM_VQRSHLuv4i32	= 1613,
    ARM_VQRSHLuv8i16	= 1614,
    ARM_VQRSHLuv8i8	= 1615,
    ARM_VQRSHRNsv2i32	= 1616,
    ARM_VQRSHRNsv4i16	= 1617,
    ARM_VQRSHRNsv8i8	= 1618,
    ARM_VQRSHRNuv2i32	= 1619,
    ARM_VQRSHRNuv4i16	= 1620,
    ARM_VQRSHRNuv8i8	= 1621,
    ARM_VQRSHRUNv2i32	= 1622,
    ARM_VQRSHRUNv4i16	= 1623,
    ARM_VQRSHRUNv8i8	= 1624,
    ARM_VQSHLsiv16i8	= 1625,
    ARM_VQSHLsiv1i64	= 1626,
    ARM_VQSHLsiv2i32	= 1627,
    ARM_VQSHLsiv2i64	= 1628,
    ARM_VQSHLsiv4i16	= 1629,
    ARM_VQSHLsiv4i32	= 1630,
    ARM_VQSHLsiv8i16	= 1631,
    ARM_VQSHLsiv8i8	= 1632,
    ARM_VQSHLsuv16i8	= 1633,
    ARM_VQSHLsuv1i64	= 1634,
    ARM_VQSHLsuv2i32	= 1635,
    ARM_VQSHLsuv2i64	= 1636,
    ARM_VQSHLsuv4i16	= 1637,
    ARM_VQSHLsuv4i32	= 1638,
    ARM_VQSHLsuv8i16	= 1639,
    ARM_VQSHLsuv8i8	= 1640,
    ARM_VQSHLsv16i8	= 1641,
    ARM_VQSHLsv1i64	= 1642,
    ARM_VQSHLsv2i32	= 1643,
    ARM_VQSHLsv2i64	= 1644,
    ARM_VQSHLsv4i16	= 1645,
    ARM_VQSHLsv4i32	= 1646,
    ARM_VQSHLsv8i16	= 1647,
    ARM_VQSHLsv8i8	= 1648,
    ARM_VQSHLuiv16i8	= 1649,
    ARM_VQSHLuiv1i64	= 1650,
    ARM_VQSHLuiv2i32	= 1651,
    ARM_VQSHLuiv2i64	= 1652,
    ARM_VQSHLuiv4i16	= 1653,
    ARM_VQSHLuiv4i32	= 1654,
    ARM_VQSHLuiv8i16	= 1655,
    ARM_VQSHLuiv8i8	= 1656,
    ARM_VQSHLuv16i8	= 1657,
    ARM_VQSHLuv1i64	= 1658,
    ARM_VQSHLuv2i32	= 1659,
    ARM_VQSHLuv2i64	= 1660,
    ARM_VQSHLuv4i16	= 1661,
    ARM_VQSHLuv4i32	= 1662,
    ARM_VQSHLuv8i16	= 1663,
    ARM_VQSHLuv8i8	= 1664,
    ARM_VQSHRNsv2i32	= 1665,
    ARM_VQSHRNsv4i16	= 1666,
    ARM_VQSHRNsv8i8	= 1667,
    ARM_VQSHRNuv2i32	= 1668,
    ARM_VQSHRNuv4i16	= 1669,
    ARM_VQSHRNuv8i8	= 1670,
    ARM_VQSHRUNv2i32	= 1671,
    ARM_VQSHRUNv4i16	= 1672,
    ARM_VQSHRUNv8i8	= 1673,
    ARM_VQSUBsv16i8	= 1674,
    ARM_VQSUBsv1i64	= 1675,
    ARM_VQSUBsv2i32	= 1676,
    ARM_VQSUBsv2i64	= 1677,
    ARM_VQSUBsv4i16	= 1678,
    ARM_VQSUBsv4i32	= 1679,
    ARM_VQSUBsv8i16	= 1680,
    ARM_VQSUBsv8i8	= 1681,
    ARM_VQSUBuv16i8	= 1682,
    ARM_VQSUBuv1i64	= 1683,
    ARM_VQSUBuv2i32	= 1684,
    ARM_VQSUBuv2i64	= 1685,
    ARM_VQSUBuv4i16	= 1686,
    ARM_VQSUBuv4i32	= 1687,
    ARM_VQSUBuv8i16	= 1688,
    ARM_VQSUBuv8i8	= 1689,
    ARM_VRADDHNv2i32	= 1690,
    ARM_VRADDHNv4i16	= 1691,
    ARM_VRADDHNv8i8	= 1692,
    ARM_VRECPEd	= 1693,
    ARM_VRECPEfd	= 1694,
    ARM_VRECPEfq	= 1695,
    ARM_VRECPEq	= 1696,
    ARM_VRECPSfd	= 1697,
    ARM_VRECPSfq	= 1698,
    ARM_VREV16d8	= 1699,
    ARM_VREV16q8	= 1700,
    ARM_VREV32d16	= 1701,
    ARM_VREV32d8	= 1702,
    ARM_VREV32q16	= 1703,
    ARM_VREV32q8	= 1704,
    ARM_VREV64d16	= 1705,
    ARM_VREV64d32	= 1706,
    ARM_VREV64d8	= 1707,
    ARM_VREV64q16	= 1708,
    ARM_VREV64q32	= 1709,
    ARM_VREV64q8	= 1710,
    ARM_VRHADDsv16i8	= 1711,
    ARM_VRHADDsv2i32	= 1712,
    ARM_VRHADDsv4i16	= 1713,
    ARM_VRHADDsv4i32	= 1714,
    ARM_VRHADDsv8i16	= 1715,
    ARM_VRHADDsv8i8	= 1716,
    ARM_VRHADDuv16i8	= 1717,
    ARM_VRHADDuv2i32	= 1718,
    ARM_VRHADDuv4i16	= 1719,
    ARM_VRHADDuv4i32	= 1720,
    ARM_VRHADDuv8i16	= 1721,
    ARM_VRHADDuv8i8	= 1722,
    ARM_VRINTAD	= 1723,
    ARM_VRINTAND	= 1724,
    ARM_VRINTANQ	= 1725,
    ARM_VRINTAS	= 1726,
    ARM_VRINTMD	= 1727,
    ARM_VRINTMND	= 1728,
    ARM_VRINTMNQ	= 1729,
    ARM_VRINTMS	= 1730,
    ARM_VRINTND	= 1731,
    ARM_VRINTNND	= 1732,
    ARM_VRINTNNQ	= 1733,
    ARM_VRINTNS	= 1734,
    ARM_VRINTPD	= 1735,
    ARM_VRINTPND	= 1736,
    ARM_VRINTPNQ	= 1737,
    ARM_VRINTPS	= 1738,
    ARM_VRINTRD	= 1739,
    ARM_VRINTRS	= 1740,
    ARM_VRINTXD	= 1741,
    ARM_VRINTXND	= 1742,
    ARM_VRINTXNQ	= 1743,
    ARM_VRINTXS	= 1744,
    ARM_VRINTZD	= 1745,
    ARM_VRINTZND	= 1746,
    ARM_VRINTZNQ	= 1747,
    ARM_VRINTZS	= 1748,
    ARM_VRSHLsv16i8	= 1749,
    ARM_VRSHLsv1i64	= 1750,
    ARM_VRSHLsv2i32	= 1751,
    ARM_VRSHLsv2i64	= 1752,
    ARM_VRSHLsv4i16	= 1753,
    ARM_VRSHLsv4i32	= 1754,
    ARM_VRSHLsv8i16	= 1755,
    ARM_VRSHLsv8i8	= 1756,
    ARM_VRSHLuv16i8	= 1757,
    ARM_VRSHLuv1i64	= 1758,
    ARM_VRSHLuv2i32	= 1759,
    ARM_VRSHLuv2i64	= 1760,
    ARM_VRSHLuv4i16	= 1761,
    ARM_VRSHLuv4i32	= 1762,
    ARM_VRSHLuv8i16	= 1763,
    ARM_VRSHLuv8i8	= 1764,
    ARM_VRSHRNv2i32	= 1765,
    ARM_VRSHRNv4i16	= 1766,
    ARM_VRSHRNv8i8	= 1767,
    ARM_VRSHRsv16i8	= 1768,
    ARM_VRSHRsv1i64	= 1769,
    ARM_VRSHRsv2i32	= 1770,
    ARM_VRSHRsv2i64	= 1771,
    ARM_VRSHRsv4i16	= 1772,
    ARM_VRSHRsv4i32	= 1773,
    ARM_VRSHRsv8i16	= 1774,
    ARM_VRSHRsv8i8	= 1775,
    ARM_VRSHRuv16i8	= 1776,
    ARM_VRSHRuv1i64	= 1777,
    ARM_VRSHRuv2i32	= 1778,
    ARM_VRSHRuv2i64	= 1779,
    ARM_VRSHRuv4i16	= 1780,
    ARM_VRSHRuv4i32	= 1781,
    ARM_VRSHRuv8i16	= 1782,
    ARM_VRSHRuv8i8	= 1783,
    ARM_VRSQRTEd	= 1784,
    ARM_VRSQRTEfd	= 1785,
    ARM_VRSQRTEfq	= 1786,
    ARM_VRSQRTEq	= 1787,
    ARM_VRSQRTSfd	= 1788,
    ARM_VRSQRTSfq	= 1789,
    ARM_VRSRAsv16i8	= 1790,
    ARM_VRSRAsv1i64	= 1791,
    ARM_VRSRAsv2i32	= 1792,
    ARM_VRSRAsv2i64	= 1793,
    ARM_VRSRAsv4i16	= 1794,
    ARM_VRSRAsv4i32	= 1795,
    ARM_VRSRAsv8i16	= 1796,
    ARM_VRSRAsv8i8	= 1797,
    ARM_VRSRAuv16i8	= 1798,
    ARM_VRSRAuv1i64	= 1799,
    ARM_VRSRAuv2i32	= 1800,
    ARM_VRSRAuv2i64	= 1801,
    ARM_VRSRAuv4i16	= 1802,
    ARM_VRSRAuv4i32	= 1803,
    ARM_VRSRAuv8i16	= 1804,
    ARM_VRSRAuv8i8	= 1805,
    ARM_VRSUBHNv2i32	= 1806,
    ARM_VRSUBHNv4i16	= 1807,
    ARM_VRSUBHNv8i8	= 1808,
    ARM_VSELEQD	= 1809,
    ARM_VSELEQS	= 1810,
    ARM_VSELGED	= 1811,
    ARM_VSELGES	= 1812,
    ARM_VSELGTD	= 1813,
    ARM_VSELGTS	= 1814,
    ARM_VSELVSD	= 1815,
    ARM_VSELVSS	= 1816,
    ARM_VSETLNi16	= 1817,
    ARM_VSETLNi32	= 1818,
    ARM_VSETLNi8	= 1819,
    ARM_VSHLLi16	= 1820,
    ARM_VSHLLi32	= 1821,
    ARM_VSHLLi8	= 1822,
    ARM_VSHLLsv2i64	= 1823,
    ARM_VSHLLsv4i32	= 1824,
    ARM_VSHLLsv8i16	= 1825,
    ARM_VSHLLuv2i64	= 1826,
    ARM_VSHLLuv4i32	= 1827,
    ARM_VSHLLuv8i16	= 1828,
    ARM_VSHLiv16i8	= 1829,
    ARM_VSHLiv1i64	= 1830,
    ARM_VSHLiv2i32	= 1831,
    ARM_VSHLiv2i64	= 1832,
    ARM_VSHLiv4i16	= 1833,
    ARM_VSHLiv4i32	= 1834,
    ARM_VSHLiv8i16	= 1835,
    ARM_VSHLiv8i8	= 1836,
    ARM_VSHLsv16i8	= 1837,
    ARM_VSHLsv1i64	= 1838,
    ARM_VSHLsv2i32	= 1839,
    ARM_VSHLsv2i64	= 1840,
    ARM_VSHLsv4i16	= 1841,
    ARM_VSHLsv4i32	= 1842,
    ARM_VSHLsv8i16	= 1843,
    ARM_VSHLsv8i8	= 1844,
    ARM_VSHLuv16i8	= 1845,
    ARM_VSHLuv1i64	= 1846,
    ARM_VSHLuv2i32	= 1847,
    ARM_VSHLuv2i64	= 1848,
    ARM_VSHLuv4i16	= 1849,
    ARM_VSHLuv4i32	= 1850,
    ARM_VSHLuv8i16	= 1851,
    ARM_VSHLuv8i8	= 1852,
    ARM_VSHRNv2i32	= 1853,
    ARM_VSHRNv4i16	= 1854,
    ARM_VSHRNv8i8	= 1855,
    ARM_VSHRsv16i8	= 1856,
    ARM_VSHRsv1i64	= 1857,
    ARM_VSHRsv2i32	= 1858,
    ARM_VSHRsv2i64	= 1859,
    ARM_VSHRsv4i16	= 1860,
    ARM_VSHRsv4i32	= 1861,
    ARM_VSHRsv8i16	= 1862,
    ARM_VSHRsv8i8	= 1863,
    ARM_VSHRuv16i8	= 1864,
    ARM_VSHRuv1i64	= 1865,
    ARM_VSHRuv2i32	= 1866,
    ARM_VSHRuv2i64	= 1867,
    ARM_VSHRuv4i16	= 1868,
    ARM_VSHRuv4i32	= 1869,
    ARM_VSHRuv8i16	= 1870,
    ARM_VSHRuv8i8	= 1871,
    ARM_VSHTOD	= 1872,
    ARM_VSHTOS	= 1873,
    ARM_VSITOD	= 1874,
    ARM_VSITOS	= 1875,
    ARM_VSLIv16i8	= 1876,
    ARM_VSLIv1i64	= 1877,
    ARM_VSLIv2i32	= 1878,
    ARM_VSLIv2i64	= 1879,
    ARM_VSLIv4i16	= 1880,
    ARM_VSLIv4i32	= 1881,
    ARM_VSLIv8i16	= 1882,
    ARM_VSLIv8i8	= 1883,
    ARM_VSLTOD	= 1884,
    ARM_VSLTOS	= 1885,
    ARM_VSQRTD	= 1886,
    ARM_VSQRTS	= 1887,
    ARM_VSRAsv16i8	= 1888,
    ARM_VSRAsv1i64	= 1889,
    ARM_VSRAsv2i32	= 1890,
    ARM_VSRAsv2i64	= 1891,
    ARM_VSRAsv4i16	= 1892,
    ARM_VSRAsv4i32	= 1893,
    ARM_VSRAsv8i16	= 1894,
    ARM_VSRAsv8i8	= 1895,
    ARM_VSRAuv16i8	= 1896,
    ARM_VSRAuv1i64	= 1897,
    ARM_VSRAuv2i32	= 1898,
    ARM_VSRAuv2i64	= 1899,
    ARM_VSRAuv4i16	= 1900,
    ARM_VSRAuv4i32	= 1901,
    ARM_VSRAuv8i16	= 1902,
    ARM_VSRAuv8i8	= 1903,
    ARM_VSRIv16i8	= 1904,
    ARM_VSRIv1i64	= 1905,
    ARM_VSRIv2i32	= 1906,
    ARM_VSRIv2i64	= 1907,
    ARM_VSRIv4i16	= 1908,
    ARM_VSRIv4i32	= 1909,
    ARM_VSRIv8i16	= 1910,
    ARM_VSRIv8i8	= 1911,
    ARM_VST1LNd16	= 1912,
    ARM_VST1LNd16_UPD	= 1913,
    ARM_VST1LNd32	= 1914,
    ARM_VST1LNd32_UPD	= 1915,
    ARM_VST1LNd8	= 1916,
    ARM_VST1LNd8_UPD	= 1917,
    ARM_VST1LNdAsm_16	= 1918,
    ARM_VST1LNdAsm_32	= 1919,
    ARM_VST1LNdAsm_8	= 1920,
    ARM_VST1LNdWB_fixed_Asm_16	= 1921,
    ARM_VST1LNdWB_fixed_Asm_32	= 1922,
    ARM_VST1LNdWB_fixed_Asm_8	= 1923,
    ARM_VST1LNdWB_register_Asm_16	= 1924,
    ARM_VST1LNdWB_register_Asm_32	= 1925,
    ARM_VST1LNdWB_register_Asm_8	= 1926,
    ARM_VST1LNq16Pseudo	= 1927,
    ARM_VST1LNq16Pseudo_UPD	= 1928,
    ARM_VST1LNq32Pseudo	= 1929,
    ARM_VST1LNq32Pseudo_UPD	= 1930,
    ARM_VST1LNq8Pseudo	= 1931,
    ARM_VST1LNq8Pseudo_UPD	= 1932,
    ARM_VST1d16	= 1933,
    ARM_VST1d16Q	= 1934,
    ARM_VST1d16Qwb_fixed	= 1935,
    ARM_VST1d16Qwb_register	= 1936,
    ARM_VST1d16T	= 1937,
    ARM_VST1d16Twb_fixed	= 1938,
    ARM_VST1d16Twb_register	= 1939,
    ARM_VST1d16wb_fixed	= 1940,
    ARM_VST1d16wb_register	= 1941,
    ARM_VST1d32	= 1942,
    ARM_VST1d32Q	= 1943,
    ARM_VST1d32Qwb_fixed	= 1944,
    ARM_VST1d32Qwb_register	= 1945,
    ARM_VST1d32T	= 1946,
    ARM_VST1d32Twb_fixed	= 1947,
    ARM_VST1d32Twb_register	= 1948,
    ARM_VST1d32wb_fixed	= 1949,
    ARM_VST1d32wb_register	= 1950,
    ARM_VST1d64	= 1951,
    ARM_VST1d64Q	= 1952,
    ARM_VST1d64QPseudo	= 1953,
    ARM_VST1d64QPseudoWB_fixed	= 1954,
    ARM_VST1d64QPseudoWB_register	= 1955,
    ARM_VST1d64Qwb_fixed	= 1956,
    ARM_VST1d64Qwb_register	= 1957,
    ARM_VST1d64T	= 1958,
    ARM_VST1d64TPseudo	= 1959,
    ARM_VST1d64TPseudoWB_fixed	= 1960,
    ARM_VST1d64TPseudoWB_register	= 1961,
    ARM_VST1d64Twb_fixed	= 1962,
    ARM_VST1d64Twb_register	= 1963,
    ARM_VST1d64wb_fixed	= 1964,
    ARM_VST1d64wb_register	= 1965,
    ARM_VST1d8	= 1966,
    ARM_VST1d8Q	= 1967,
    ARM_VST1d8Qwb_fixed	= 1968,
    ARM_VST1d8Qwb_register	= 1969,
    ARM_VST1d8T	= 1970,
    ARM_VST1d8Twb_fixed	= 1971,
    ARM_VST1d8Twb_register	= 1972,
    ARM_VST1d8wb_fixed	= 1973,
    ARM_VST1d8wb_register	= 1974,
    ARM_VST1q16	= 1975,
    ARM_VST1q16wb_fixed	= 1976,
    ARM_VST1q16wb_register	= 1977,
    ARM_VST1q32	= 1978,
    ARM_VST1q32wb_fixed	= 1979,
    ARM_VST1q32wb_register	= 1980,
    ARM_VST1q64	= 1981,
    ARM_VST1q64wb_fixed	= 1982,
    ARM_VST1q64wb_register	= 1983,
    ARM_VST1q8	= 1984,
    ARM_VST1q8wb_fixed	= 1985,
    ARM_VST1q8wb_register	= 1986,
    ARM_VST2LNd16	= 1987,
    ARM_VST2LNd16Pseudo	= 1988,
    ARM_VST2LNd16Pseudo_UPD	= 1989,
    ARM_VST2LNd16_UPD	= 1990,
    ARM_VST2LNd32	= 1991,
    ARM_VST2LNd32Pseudo	= 1992,
    ARM_VST2LNd32Pseudo_UPD	= 1993,
    ARM_VST2LNd32_UPD	= 1994,
    ARM_VST2LNd8	= 1995,
    ARM_VST2LNd8Pseudo	= 1996,
    ARM_VST2LNd8Pseudo_UPD	= 1997,
    ARM_VST2LNd8_UPD	= 1998,
    ARM_VST2LNdAsm_16	= 1999,
    ARM_VST2LNdAsm_32	= 2000,
    ARM_VST2LNdAsm_8	= 2001,
    ARM_VST2LNdWB_fixed_Asm_16	= 2002,
    ARM_VST2LNdWB_fixed_Asm_32	= 2003,
    ARM_VST2LNdWB_fixed_Asm_8	= 2004,
    ARM_VST2LNdWB_register_Asm_16	= 2005,
    ARM_VST2LNdWB_register_Asm_32	= 2006,
    ARM_VST2LNdWB_register_Asm_8	= 2007,
    ARM_VST2LNq16	= 2008,
    ARM_VST2LNq16Pseudo	= 2009,
    ARM_VST2LNq16Pseudo_UPD	= 2010,
    ARM_VST2LNq16_UPD	= 2011,
    ARM_VST2LNq32	= 2012,
    ARM_VST2LNq32Pseudo	= 2013,
    ARM_VST2LNq32Pseudo_UPD	= 2014,
    ARM_VST2LNq32_UPD	= 2015,
    ARM_VST2LNqAsm_16	= 2016,
    ARM_VST2LNqAsm_32	= 2017,
    ARM_VST2LNqWB_fixed_Asm_16	= 2018,
    ARM_VST2LNqWB_fixed_Asm_32	= 2019,
    ARM_VST2LNqWB_register_Asm_16	= 2020,
    ARM_VST2LNqWB_register_Asm_32	= 2021,
    ARM_VST2b16	= 2022,
    ARM_VST2b16wb_fixed	= 2023,
    ARM_VST2b16wb_register	= 2024,
    ARM_VST2b32	= 2025,
    ARM_VST2b32wb_fixed	= 2026,
    ARM_VST2b32wb_register	= 2027,
    ARM_VST2b8	= 2028,
    ARM_VST2b8wb_fixed	= 2029,
    ARM_VST2b8wb_register	= 2030,
    ARM_VST2d16	= 2031,
    ARM_VST2d16wb_fixed	= 2032,
    ARM_VST2d16wb_register	= 2033,
    ARM_VST2d32	= 2034,
    ARM_VST2d32wb_fixed	= 2035,
    ARM_VST2d32wb_register	= 2036,
    ARM_VST2d8	= 2037,
    ARM_VST2d8wb_fixed	= 2038,
    ARM_VST2d8wb_register	= 2039,
    ARM_VST2q16	= 2040,
    ARM_VST2q16Pseudo	= 2041,
    ARM_VST2q16PseudoWB_fixed	= 2042,
    ARM_VST2q16PseudoWB_register	= 2043,
    ARM_VST2q16wb_fixed	= 2044,
    ARM_VST2q16wb_register	= 2045,
    ARM_VST2q32	= 2046,
    ARM_VST2q32Pseudo	= 2047,
    ARM_VST2q32PseudoWB_fixed	= 2048,
    ARM_VST2q32PseudoWB_register	= 2049,
    ARM_VST2q32wb_fixed	= 2050,
    ARM_VST2q32wb_register	= 2051,
    ARM_VST2q8	= 2052,
    ARM_VST2q8Pseudo	= 2053,
    ARM_VST2q8PseudoWB_fixed	= 2054,
    ARM_VST2q8PseudoWB_register	= 2055,
    ARM_VST2q8wb_fixed	= 2056,
    ARM_VST2q8wb_register	= 2057,
    ARM_VST3LNd16	= 2058,
    ARM_VST3LNd16Pseudo	= 2059,
    ARM_VST3LNd16Pseudo_UPD	= 2060,
    ARM_VST3LNd16_UPD	= 2061,
    ARM_VST3LNd32	= 2062,
    ARM_VST3LNd32Pseudo	= 2063,
    ARM_VST3LNd32Pseudo_UPD	= 2064,
    ARM_VST3LNd32_UPD	= 2065,
    ARM_VST3LNd8	= 2066,
    ARM_VST3LNd8Pseudo	= 2067,
    ARM_VST3LNd8Pseudo_UPD	= 2068,
    ARM_VST3LNd8_UPD	= 2069,
    ARM_VST3LNdAsm_16	= 2070,
    ARM_VST3LNdAsm_32	= 2071,
    ARM_VST3LNdAsm_8	= 2072,
    ARM_VST3LNdWB_fixed_Asm_16	= 2073,
    ARM_VST3LNdWB_fixed_Asm_32	= 2074,
    ARM_VST3LNdWB_fixed_Asm_8	= 2075,
    ARM_VST3LNdWB_register_Asm_16	= 2076,
    ARM_VST3LNdWB_register_Asm_32	= 2077,
    ARM_VST3LNdWB_register_Asm_8	= 2078,
    ARM_VST3LNq16	= 2079,
    ARM_VST3LNq16Pseudo	= 2080,
    ARM_VST3LNq16Pseudo_UPD	= 2081,
    ARM_VST3LNq16_UPD	= 2082,
    ARM_VST3LNq32	= 2083,
    ARM_VST3LNq32Pseudo	= 2084,
    ARM_VST3LNq32Pseudo_UPD	= 2085,
    ARM_VST3LNq32_UPD	= 2086,
    ARM_VST3LNqAsm_16	= 2087,
    ARM_VST3LNqAsm_32	= 2088,
    ARM_VST3LNqWB_fixed_Asm_16	= 2089,
    ARM_VST3LNqWB_fixed_Asm_32	= 2090,
    ARM_VST3LNqWB_register_Asm_16	= 2091,
    ARM_VST3LNqWB_register_Asm_32	= 2092,
    ARM_VST3d16	= 2093,
    ARM_VST3d16Pseudo	= 2094,
    ARM_VST3d16Pseudo_UPD	= 2095,
    ARM_VST3d16_UPD	= 2096,
    ARM_VST3d32	= 2097,
    ARM_VST3d32Pseudo	= 2098,
    ARM_VST3d32Pseudo_UPD	= 2099,
    ARM_VST3d32_UPD	= 2100,
    ARM_VST3d8	= 2101,
    ARM_VST3d8Pseudo	= 2102,
    ARM_VST3d8Pseudo_UPD	= 2103,
    ARM_VST3d8_UPD	= 2104,
    ARM_VST3dAsm_16	= 2105,
    ARM_VST3dAsm_32	= 2106,
    ARM_VST3dAsm_8	= 2107,
    ARM_VST3dWB_fixed_Asm_16	= 2108,
    ARM_VST3dWB_fixed_Asm_32	= 2109,
    ARM_VST3dWB_fixed_Asm_8	= 2110,
    ARM_VST3dWB_register_Asm_16	= 2111,
    ARM_VST3dWB_register_Asm_32	= 2112,
    ARM_VST3dWB_register_Asm_8	= 2113,
    ARM_VST3q16	= 2114,
    ARM_VST3q16Pseudo_UPD	= 2115,
    ARM_VST3q16_UPD	= 2116,
    ARM_VST3q16oddPseudo	= 2117,
    ARM_VST3q16oddPseudo_UPD	= 2118,
    ARM_VST3q32	= 2119,
    ARM_VST3q32Pseudo_UPD	= 2120,
    ARM_VST3q32_UPD	= 2121,
    ARM_VST3q32oddPseudo	= 2122,
    ARM_VST3q32oddPseudo_UPD	= 2123,
    ARM_VST3q8	= 2124,
    ARM_VST3q8Pseudo_UPD	= 2125,
    ARM_VST3q8_UPD	= 2126,
    ARM_VST3q8oddPseudo	= 2127,
    ARM_VST3q8oddPseudo_UPD	= 2128,
    ARM_VST3qAsm_16	= 2129,
    ARM_VST3qAsm_32	= 2130,
    ARM_VST3qAsm_8	= 2131,
    ARM_VST3qWB_fixed_Asm_16	= 2132,
    ARM_VST3qWB_fixed_Asm_32	= 2133,
    ARM_VST3qWB_fixed_Asm_8	= 2134,
    ARM_VST3qWB_register_Asm_16	= 2135,
    ARM_VST3qWB_register_Asm_32	= 2136,
    ARM_VST3qWB_register_Asm_8	= 2137,
    ARM_VST4LNd16	= 2138,
    ARM_VST4LNd16Pseudo	= 2139,
    ARM_VST4LNd16Pseudo_UPD	= 2140,
    ARM_VST4LNd16_UPD	= 2141,
    ARM_VST4LNd32	= 2142,
    ARM_VST4LNd32Pseudo	= 2143,
    ARM_VST4LNd32Pseudo_UPD	= 2144,
    ARM_VST4LNd32_UPD	= 2145,
    ARM_VST4LNd8	= 2146,
    ARM_VST4LNd8Pseudo	= 2147,
    ARM_VST4LNd8Pseudo_UPD	= 2148,
    ARM_VST4LNd8_UPD	= 2149,
    ARM_VST4LNdAsm_16	= 2150,
    ARM_VST4LNdAsm_32	= 2151,
    ARM_VST4LNdAsm_8	= 2152,
    ARM_VST4LNdWB_fixed_Asm_16	= 2153,
    ARM_VST4LNdWB_fixed_Asm_32	= 2154,
    ARM_VST4LNdWB_fixed_Asm_8	= 2155,
    ARM_VST4LNdWB_register_Asm_16	= 2156,
    ARM_VST4LNdWB_register_Asm_32	= 2157,
    ARM_VST4LNdWB_register_Asm_8	= 2158,
    ARM_VST4LNq16	= 2159,
    ARM_VST4LNq16Pseudo	= 2160,
    ARM_VST4LNq16Pseudo_UPD	= 2161,
    ARM_VST4LNq16_UPD	= 2162,
    ARM_VST4LNq32	= 2163,
    ARM_VST4LNq32Pseudo	= 2164,
    ARM_VST4LNq32Pseudo_UPD	= 2165,
    ARM_VST4LNq32_UPD	= 2166,
    ARM_VST4LNqAsm_16	= 2167,
    ARM_VST4LNqAsm_32	= 2168,
    ARM_VST4LNqWB_fixed_Asm_16	= 2169,
    ARM_VST4LNqWB_fixed_Asm_32	= 2170,
    ARM_VST4LNqWB_register_Asm_16	= 2171,
    ARM_VST4LNqWB_register_Asm_32	= 2172,
    ARM_VST4d16	= 2173,
    ARM_VST4d16Pseudo	= 2174,
    ARM_VST4d16Pseudo_UPD	= 2175,
    ARM_VST4d16_UPD	= 2176,
    ARM_VST4d32	= 2177,
    ARM_VST4d32Pseudo	= 2178,
    ARM_VST4d32Pseudo_UPD	= 2179,
    ARM_VST4d32_UPD	= 2180,
    ARM_VST4d8	= 2181,
    ARM_VST4d8Pseudo	= 2182,
    ARM_VST4d8Pseudo_UPD	= 2183,
    ARM_VST4d8_UPD	= 2184,
    ARM_VST4dAsm_16	= 2185,
    ARM_VST4dAsm_32	= 2186,
    ARM_VST4dAsm_8	= 2187,
    ARM_VST4dWB_fixed_Asm_16	= 2188,
    ARM_VST4dWB_fixed_Asm_32	= 2189,
    ARM_VST4dWB_fixed_Asm_8	= 2190,
    ARM_VST4dWB_register_Asm_16	= 2191,
    ARM_VST4dWB_register_Asm_32	= 2192,
    ARM_VST4dWB_register_Asm_8	= 2193,
    ARM_VST4q16	= 2194,
    ARM_VST4q16Pseudo_UPD	= 2195,
    ARM_VST4q16_UPD	= 2196,
    ARM_VST4q16oddPseudo	= 2197,
    ARM_VST4q16oddPseudo_UPD	= 2198,
    ARM_VST4q32	= 2199,
    ARM_VST4q32Pseudo_UPD	= 2200,
    ARM_VST4q32_UPD	= 2201,
    ARM_VST4q32oddPseudo	= 2202,
    ARM_VST4q32oddPseudo_UPD	= 2203,
    ARM_VST4q8	= 2204,
    ARM_VST4q8Pseudo_UPD	= 2205,
    ARM_VST4q8_UPD	= 2206,
    ARM_VST4q8oddPseudo	= 2207,
    ARM_VST4q8oddPseudo_UPD	= 2208,
    ARM_VST4qAsm_16	= 2209,
    ARM_VST4qAsm_32	= 2210,
    ARM_VST4qAsm_8	= 2211,
    ARM_VST4qWB_fixed_Asm_16	= 2212,
    ARM_VST4qWB_fixed_Asm_32	= 2213,
    ARM_VST4qWB_fixed_Asm_8	= 2214,
    ARM_VST4qWB_register_Asm_16	= 2215,
    ARM_VST4qWB_register_Asm_32	= 2216,
    ARM_VST4qWB_register_Asm_8	= 2217,
    ARM_VSTMDDB_UPD	= 2218,
    ARM_VSTMDIA	= 2219,
    ARM_VSTMDIA_UPD	= 2220,
    ARM_VSTMQIA	= 2221,
    ARM_VSTMSDB_UPD	= 2222,
    ARM_VSTMSIA	= 2223,
    ARM_VSTMSIA_UPD	= 2224,
    ARM_VSTRD	= 2225,
    ARM_VSTRS	= 2226,
    ARM_VSUBD	= 2227,
    ARM_VSUBHNv2i32	= 2228,
    ARM_VSUBHNv4i16	= 2229,
    ARM_VSUBHNv8i8	= 2230,
    ARM_VSUBLsv2i64	= 2231,
    ARM_VSUBLsv4i32	= 2232,
    ARM_VSUBLsv8i16	= 2233,
    ARM_VSUBLuv2i64	= 2234,
    ARM_VSUBLuv4i32	= 2235,
    ARM_VSUBLuv8i16	= 2236,
    ARM_VSUBS	= 2237,
    ARM_VSUBWsv2i64	= 2238,
    ARM_VSUBWsv4i32	= 2239,
    ARM_VSUBWsv8i16	= 2240,
    ARM_VSUBWuv2i64	= 2241,
    ARM_VSUBWuv4i32	= 2242,
    ARM_VSUBWuv8i16	= 2243,
    ARM_VSUBfd	= 2244,
    ARM_VSUBfq	= 2245,
    ARM_VSUBv16i8	= 2246,
    ARM_VSUBv1i64	= 2247,
    ARM_VSUBv2i32	= 2248,
    ARM_VSUBv2i64	= 2249,
    ARM_VSUBv4i16	= 2250,
    ARM_VSUBv4i32	= 2251,
    ARM_VSUBv8i16	= 2252,
    ARM_VSUBv8i8	= 2253,
    ARM_VSWPd	= 2254,
    ARM_VSWPq	= 2255,
    ARM_VTBL1	= 2256,
    ARM_VTBL2	= 2257,
    ARM_VTBL3	= 2258,
    ARM_VTBL3Pseudo	= 2259,
    ARM_VTBL4	= 2260,
    ARM_VTBL4Pseudo	= 2261,
    ARM_VTBX1	= 2262,
    ARM_VTBX2	= 2263,
    ARM_VTBX3	= 2264,
    ARM_VTBX3Pseudo	= 2265,
    ARM_VTBX4	= 2266,
    ARM_VTBX4Pseudo	= 2267,
    ARM_VTOSHD	= 2268,
    ARM_VTOSHS	= 2269,
    ARM_VTOSIRD	= 2270,
    ARM_VTOSIRS	= 2271,
    ARM_VTOSIZD	= 2272,
    ARM_VTOSIZS	= 2273,
    ARM_VTOSLD	= 2274,
    ARM_VTOSLS	= 2275,
    ARM_VTOUHD	= 2276,
    ARM_VTOUHS	= 2277,
    ARM_VTOUIRD	= 2278,
    ARM_VTOUIRS	= 2279,
    ARM_VTOUIZD	= 2280,
    ARM_VTOUIZS	= 2281,
    ARM_VTOULD	= 2282,
    ARM_VTOULS	= 2283,
    ARM_VTRNd16	= 2284,
    ARM_VTRNd32	= 2285,
    ARM_VTRNd8	= 2286,
    ARM_VTRNq16	= 2287,
    ARM_VTRNq32	= 2288,
    ARM_VTRNq8	= 2289,
    ARM_VTSTv16i8	= 2290,
    ARM_VTSTv2i32	= 2291,
    ARM_VTSTv4i16	= 2292,
    ARM_VTSTv4i32	= 2293,
    ARM_VTSTv8i16	= 2294,
    ARM_VTSTv8i8	= 2295,
    ARM_VUHTOD	= 2296,
    ARM_VUHTOS	= 2297,
    ARM_VUITOD	= 2298,
    ARM_VUITOS	= 2299,
    ARM_VULTOD	= 2300,
    ARM_VULTOS	= 2301,
    ARM_VUZPd16	= 2302,
    ARM_VUZPd8	= 2303,
    ARM_VUZPq16	= 2304,
    ARM_VUZPq32	= 2305,
    ARM_VUZPq8	= 2306,
    ARM_VZIPd16	= 2307,
    ARM_VZIPd8	= 2308,
    ARM_VZIPq16	= 2309,
    ARM_VZIPq32	= 2310,
    ARM_VZIPq8	= 2311,
    ARM_sysLDMDA	= 2312,
    ARM_sysLDMDA_UPD	= 2313,
    ARM_sysLDMDB	= 2314,
    ARM_sysLDMDB_UPD	= 2315,
    ARM_sysLDMIA	= 2316,
    ARM_sysLDMIA_UPD	= 2317,
    ARM_sysLDMIB	= 2318,
    ARM_sysLDMIB_UPD	= 2319,
    ARM_sysSTMDA	= 2320,
    ARM_sysSTMDA_UPD	= 2321,
    ARM_sysSTMDB	= 2322,
    ARM_sysSTMDB_UPD	= 2323,
    ARM_sysSTMIA	= 2324,
    ARM_sysSTMIA_UPD	= 2325,
    ARM_sysSTMIB	= 2326,
    ARM_sysSTMIB_UPD	= 2327,
    ARM_t2ABS	= 2328,
    ARM_t2ADCri	= 2329,
    ARM_t2ADCrr	= 2330,
    ARM_t2ADCrs	= 2331,
    ARM_t2ADDSri	= 2332,
    ARM_t2ADDSrr	= 2333,
    ARM_t2ADDSrs	= 2334,
    ARM_t2ADDri	= 2335,
    ARM_t2ADDri12	= 2336,
    ARM_t2ADDrr	= 2337,
    ARM_t2ADDrs	= 2338,
    ARM_t2ADR	= 2339,
    ARM_t2ANDri	= 2340,
    ARM_t2ANDrr	= 2341,
    ARM_t2ANDrs	= 2342,
    ARM_t2ASRri	= 2343,
    ARM_t2ASRrr	= 2344,
    ARM_t2B	= 2345,
    ARM_t2BFC	= 2346,
    ARM_t2BFI	= 2347,
    ARM_t2BICri	= 2348,
    ARM_t2BICrr	= 2349,
    ARM_t2BICrs	= 2350,
    ARM_t2BR_JT	= 2351,
    ARM_t2BXJ	= 2352,
    ARM_t2Bcc	= 2353,
    ARM_t2CDP	= 2354,
    ARM_t2CDP2	= 2355,
    ARM_t2CLREX	= 2356,
    ARM_t2CLZ	= 2357,
    ARM_t2CMNri	= 2358,
    ARM_t2CMNzrr	= 2359,
    ARM_t2CMNzrs	= 2360,
    ARM_t2CMPri	= 2361,
    ARM_t2CMPrr	= 2362,
    ARM_t2CMPrs	= 2363,
    ARM_t2CPS1p	= 2364,
    ARM_t2CPS2p	= 2365,
    ARM_t2CPS3p	= 2366,
    ARM_t2CRC32B	= 2367,
    ARM_t2CRC32CB	= 2368,
    ARM_t2CRC32CH	= 2369,
    ARM_t2CRC32CW	= 2370,
    ARM_t2CRC32H	= 2371,
    ARM_t2CRC32W	= 2372,
    ARM_t2DBG	= 2373,
    ARM_t2DCPS1	= 2374,
    ARM_t2DCPS2	= 2375,
    ARM_t2DCPS3	= 2376,
    ARM_t2DMB	= 2377,
    ARM_t2DSB	= 2378,
    ARM_t2EORri	= 2379,
    ARM_t2EORrr	= 2380,
    ARM_t2EORrs	= 2381,
    ARM_t2HINT	= 2382,
    ARM_t2ISB	= 2383,
    ARM_t2IT	= 2384,
    ARM_t2Int_eh_sjlj_setjmp	= 2385,
    ARM_t2Int_eh_sjlj_setjmp_nofp	= 2386,
    ARM_t2LDA	= 2387,
    ARM_t2LDAB	= 2388,
    ARM_t2LDAEX	= 2389,
    ARM_t2LDAEXB	= 2390,
    ARM_t2LDAEXD	= 2391,
    ARM_t2LDAEXH	= 2392,
    ARM_t2LDAH	= 2393,
    ARM_t2LDC2L_OFFSET	= 2394,
    ARM_t2LDC2L_OPTION	= 2395,
    ARM_t2LDC2L_POST	= 2396,
    ARM_t2LDC2L_PRE	= 2397,
    ARM_t2LDC2_OFFSET	= 2398,
    ARM_t2LDC2_OPTION	= 2399,
    ARM_t2LDC2_POST	= 2400,
    ARM_t2LDC2_PRE	= 2401,
    ARM_t2LDCL_OFFSET	= 2402,
    ARM_t2LDCL_OPTION	= 2403,
    ARM_t2LDCL_POST	= 2404,
    ARM_t2LDCL_PRE	= 2405,
    ARM_t2LDC_OFFSET	= 2406,
    ARM_t2LDC_OPTION	= 2407,
    ARM_t2LDC_POST	= 2408,
    ARM_t2LDC_PRE	= 2409,
    ARM_t2LDMDB	= 2410,
    ARM_t2LDMDB_UPD	= 2411,
    ARM_t2LDMIA	= 2412,
    ARM_t2LDMIA_RET	= 2413,
    ARM_t2LDMIA_UPD	= 2414,
    ARM_t2LDRBT	= 2415,
    ARM_t2LDRB_POST	= 2416,
    ARM_t2LDRB_PRE	= 2417,
    ARM_t2LDRBi12	= 2418,
    ARM_t2LDRBi8	= 2419,
    ARM_t2LDRBpci	= 2420,
    ARM_t2LDRBpcrel	= 2421,
    ARM_t2LDRBs	= 2422,
    ARM_t2LDRD_POST	= 2423,
    ARM_t2LDRD_PRE	= 2424,
    ARM_t2LDRDi8	= 2425,
    ARM_t2LDREX	= 2426,
    ARM_t2LDREXB	= 2427,
    ARM_t2LDREXD	= 2428,
    ARM_t2LDREXH	= 2429,
    ARM_t2LDRHT	= 2430,
    ARM_t2LDRH_POST	= 2431,
    ARM_t2LDRH_PRE	= 2432,
    ARM_t2LDRHi12	= 2433,
    ARM_t2LDRHi8	= 2434,
    ARM_t2LDRHpci	= 2435,
    ARM_t2LDRHpcrel	= 2436,
    ARM_t2LDRHs	= 2437,
    ARM_t2LDRSBT	= 2438,
    ARM_t2LDRSB_POST	= 2439,
    ARM_t2LDRSB_PRE	= 2440,
    ARM_t2LDRSBi12	= 2441,
    ARM_t2LDRSBi8	= 2442,
    ARM_t2LDRSBpci	= 2443,
    ARM_t2LDRSBpcrel	= 2444,
    ARM_t2LDRSBs	= 2445,
    ARM_t2LDRSHT	= 2446,
    ARM_t2LDRSH_POST	= 2447,
    ARM_t2LDRSH_PRE	= 2448,
    ARM_t2LDRSHi12	= 2449,
    ARM_t2LDRSHi8	= 2450,
    ARM_t2LDRSHpci	= 2451,
    ARM_t2LDRSHpcrel	= 2452,
    ARM_t2LDRSHs	= 2453,
    ARM_t2LDRT	= 2454,
    ARM_t2LDR_POST	= 2455,
    ARM_t2LDR_PRE	= 2456,
    ARM_t2LDRi12	= 2457,
    ARM_t2LDRi8	= 2458,
    ARM_t2LDRpci	= 2459,
    ARM_t2LDRpci_pic	= 2460,
    ARM_t2LDRpcrel	= 2461,
    ARM_t2LDRs	= 2462,
    ARM_t2LEApcrel	= 2463,
    ARM_t2LEApcrelJT	= 2464,
    ARM_t2LSLri	= 2465,
    ARM_t2LSLrr	= 2466,
    ARM_t2LSRri	= 2467,
    ARM_t2LSRrr	= 2468,
    ARM_t2MCR	= 2469,
    ARM_t2MCR2	= 2470,
    ARM_t2MCRR	= 2471,
    ARM_t2MCRR2	= 2472,
    ARM_t2MLA	= 2473,
    ARM_t2MLS	= 2474,
    ARM_t2MOVCCasr	= 2475,
    ARM_t2MOVCCi	= 2476,
    ARM_t2MOVCCi16	= 2477,
    ARM_t2MOVCCi32imm	= 2478,
    ARM_t2MOVCClsl	= 2479,
    ARM_t2MOVCClsr	= 2480,
    ARM_t2MOVCCr	= 2481,
    ARM_t2MOVCCror	= 2482,
    ARM_t2MOVSsi	= 2483,
    ARM_t2MOVSsr	= 2484,
    ARM_t2MOVTi16	= 2485,
    ARM_t2MOVTi16_ga_pcrel	= 2486,
    ARM_t2MOV_ga_pcrel	= 2487,
    ARM_t2MOVi	= 2488,
    ARM_t2MOVi16	= 2489,
    ARM_t2MOVi16_ga_pcrel	= 2490,
    ARM_t2MOVi32imm	= 2491,
    ARM_t2MOVr	= 2492,
    ARM_t2MOVsi	= 2493,
    ARM_t2MOVsr	= 2494,
    ARM_t2MOVsra_flag	= 2495,
    ARM_t2MOVsrl_flag	= 2496,
    ARM_t2MRC	= 2497,
    ARM_t2MRC2	= 2498,
    ARM_t2MRRC	= 2499,
    ARM_t2MRRC2	= 2500,
    ARM_t2MRS_AR	= 2501,
    ARM_t2MRS_M	= 2502,
    ARM_t2MRSsys_AR	= 2503,
    ARM_t2MSR_AR	= 2504,
    ARM_t2MSR_M	= 2505,
    ARM_t2MUL	= 2506,
    ARM_t2MVNCCi	= 2507,
    ARM_t2MVNi	= 2508,
    ARM_t2MVNr	= 2509,
    ARM_t2MVNs	= 2510,
    ARM_t2ORNri	= 2511,
    ARM_t2ORNrr	= 2512,
    ARM_t2ORNrs	= 2513,
    ARM_t2ORRri	= 2514,
    ARM_t2ORRrr	= 2515,
    ARM_t2ORRrs	= 2516,
    ARM_t2PKHBT	= 2517,
    ARM_t2PKHTB	= 2518,
    ARM_t2PLDWi12	= 2519,
    ARM_t2PLDWi8	= 2520,
    ARM_t2PLDWs	= 2521,
    ARM_t2PLDi12	= 2522,
    ARM_t2PLDi8	= 2523,
    ARM_t2PLDpci	= 2524,
    ARM_t2PLDs	= 2525,
    ARM_t2PLIi12	= 2526,
    ARM_t2PLIi8	= 2527,
    ARM_t2PLIpci	= 2528,
    ARM_t2PLIs	= 2529,
    ARM_t2QADD	= 2530,
    ARM_t2QADD16	= 2531,
    ARM_t2QADD8	= 2532,
    ARM_t2QASX	= 2533,
    ARM_t2QDADD	= 2534,
    ARM_t2QDSUB	= 2535,
    ARM_t2QSAX	= 2536,
    ARM_t2QSUB	= 2537,
    ARM_t2QSUB16	= 2538,
    ARM_t2QSUB8	= 2539,
    ARM_t2RBIT	= 2540,
    ARM_t2REV	= 2541,
    ARM_t2REV16	= 2542,
    ARM_t2REVSH	= 2543,
    ARM_t2RFEDB	= 2544,
    ARM_t2RFEDBW	= 2545,
    ARM_t2RFEIA	= 2546,
    ARM_t2RFEIAW	= 2547,
    ARM_t2RORri	= 2548,
    ARM_t2RORrr	= 2549,
    ARM_t2RRX	= 2550,
    ARM_t2RSBSri	= 2551,
    ARM_t2RSBSrs	= 2552,
    ARM_t2RSBri	= 2553,
    ARM_t2RSBrr	= 2554,
    ARM_t2RSBrs	= 2555,
    ARM_t2SADD16	= 2556,
    ARM_t2SADD8	= 2557,
    ARM_t2SASX	= 2558,
    ARM_t2SBCri	= 2559,
    ARM_t2SBCrr	= 2560,
    ARM_t2SBCrs	= 2561,
    ARM_t2SBFX	= 2562,
    ARM_t2SDIV	= 2563,
    ARM_t2SEL	= 2564,
    ARM_t2SHADD16	= 2565,
    ARM_t2SHADD8	= 2566,
    ARM_t2SHASX	= 2567,
    ARM_t2SHSAX	= 2568,
    ARM_t2SHSUB16	= 2569,
    ARM_t2SHSUB8	= 2570,
    ARM_t2SMC	= 2571,
    ARM_t2SMLABB	= 2572,
    ARM_t2SMLABT	= 2573,
    ARM_t2SMLAD	= 2574,
    ARM_t2SMLADX	= 2575,
    ARM_t2SMLAL	= 2576,
    ARM_t2SMLALBB	= 2577,
    ARM_t2SMLALBT	= 2578,
    ARM_t2SMLALD	= 2579,
    ARM_t2SMLALDX	= 2580,
    ARM_t2SMLALTB	= 2581,
    ARM_t2SMLALTT	= 2582,
    ARM_t2SMLATB	= 2583,
    ARM_t2SMLATT	= 2584,
    ARM_t2SMLAWB	= 2585,
    ARM_t2SMLAWT	= 2586,
    ARM_t2SMLSD	= 2587,
    ARM_t2SMLSDX	= 2588,
    ARM_t2SMLSLD	= 2589,
    ARM_t2SMLSLDX	= 2590,
    ARM_t2SMMLA	= 2591,
    ARM_t2SMMLAR	= 2592,
    ARM_t2SMMLS	= 2593,
    ARM_t2SMMLSR	= 2594,
    ARM_t2SMMUL	= 2595,
    ARM_t2SMMULR	= 2596,
    ARM_t2SMUAD	= 2597,
    ARM_t2SMUADX	= 2598,
    ARM_t2SMULBB	= 2599,
    ARM_t2SMULBT	= 2600,
    ARM_t2SMULL	= 2601,
    ARM_t2SMULTB	= 2602,
    ARM_t2SMULTT	= 2603,
    ARM_t2SMULWB	= 2604,
    ARM_t2SMULWT	= 2605,
    ARM_t2SMUSD	= 2606,
    ARM_t2SMUSDX	= 2607,
    ARM_t2SRSDB	= 2608,
    ARM_t2SRSDB_UPD	= 2609,
    ARM_t2SRSIA	= 2610,
    ARM_t2SRSIA_UPD	= 2611,
    ARM_t2SSAT	= 2612,
    ARM_t2SSAT16	= 2613,
    ARM_t2SSAX	= 2614,
    ARM_t2SSUB16	= 2615,
    ARM_t2SSUB8	= 2616,
    ARM_t2STC2L_OFFSET	= 2617,
    ARM_t2STC2L_OPTION	= 2618,
    ARM_t2STC2L_POST	= 2619,
    ARM_t2STC2L_PRE	= 2620,
    ARM_t2STC2_OFFSET	= 2621,
    ARM_t2STC2_OPTION	= 2622,
    ARM_t2STC2_POST	= 2623,
    ARM_t2STC2_PRE	= 2624,
    ARM_t2STCL_OFFSET	= 2625,
    ARM_t2STCL_OPTION	= 2626,
    ARM_t2STCL_POST	= 2627,
    ARM_t2STCL_PRE	= 2628,
    ARM_t2STC_OFFSET	= 2629,
    ARM_t2STC_OPTION	= 2630,
    ARM_t2STC_POST	= 2631,
    ARM_t2STC_PRE	= 2632,
    ARM_t2STL	= 2633,
    ARM_t2STLB	= 2634,
    ARM_t2STLEX	= 2635,
    ARM_t2STLEXB	= 2636,
    ARM_t2STLEXD	= 2637,
    ARM_t2STLEXH	= 2638,
    ARM_t2STLH	= 2639,
    ARM_t2STMDB	= 2640,
    ARM_t2STMDB_UPD	= 2641,
    ARM_t2STMIA	= 2642,
    ARM_t2STMIA_UPD	= 2643,
    ARM_t2STRBT	= 2644,
    ARM_t2STRB_POST	= 2645,
    ARM_t2STRB_PRE	= 2646,
    ARM_t2STRB_preidx	= 2647,
    ARM_t2STRBi12	= 2648,
    ARM_t2STRBi8	= 2649,
    ARM_t2STRBs	= 2650,
    ARM_t2STRD_POST	= 2651,
    ARM_t2STRD_PRE	= 2652,
    ARM_t2STRDi8	= 2653,
    ARM_t2STREX	= 2654,
    ARM_t2STREXB	= 2655,
    ARM_t2STREXD	= 2656,
    ARM_t2STREXH	= 2657,
    ARM_t2STRHT	= 2658,
    ARM_t2STRH_POST	= 2659,
    ARM_t2STRH_PRE	= 2660,
    ARM_t2STRH_preidx	= 2661,
    ARM_t2STRHi12	= 2662,
    ARM_t2STRHi8	= 2663,
    ARM_t2STRHs	= 2664,
    ARM_t2STRT	= 2665,
    ARM_t2STR_POST	= 2666,
    ARM_t2STR_PRE	= 2667,
    ARM_t2STR_preidx	= 2668,
    ARM_t2STRi12	= 2669,
    ARM_t2STRi8	= 2670,
    ARM_t2STRs	= 2671,
    ARM_t2SUBS_PC_LR	= 2672,
    ARM_t2SUBSri	= 2673,
    ARM_t2SUBSrr	= 2674,
    ARM_t2SUBSrs	= 2675,
    ARM_t2SUBri	= 2676,
    ARM_t2SUBri12	= 2677,
    ARM_t2SUBrr	= 2678,
    ARM_t2SUBrs	= 2679,
    ARM_t2SXTAB	= 2680,
    ARM_t2SXTAB16	= 2681,
    ARM_t2SXTAH	= 2682,
    ARM_t2SXTB	= 2683,
    ARM_t2SXTB16	= 2684,
    ARM_t2SXTH	= 2685,
    ARM_t2TBB	= 2686,
    ARM_t2TBB_JT	= 2687,
    ARM_t2TBH	= 2688,
    ARM_t2TBH_JT	= 2689,
    ARM_t2TEQri	= 2690,
    ARM_t2TEQrr	= 2691,
    ARM_t2TEQrs	= 2692,
    ARM_t2TSTri	= 2693,
    ARM_t2TSTrr	= 2694,
    ARM_t2TSTrs	= 2695,
    ARM_t2UADD16	= 2696,
    ARM_t2UADD8	= 2697,
    ARM_t2UASX	= 2698,
    ARM_t2UBFX	= 2699,
    ARM_t2UDIV	= 2700,
    ARM_t2UHADD16	= 2701,
    ARM_t2UHADD8	= 2702,
    ARM_t2UHASX	= 2703,
    ARM_t2UHSAX	= 2704,
    ARM_t2UHSUB16	= 2705,
    ARM_t2UHSUB8	= 2706,
    ARM_t2UMAAL	= 2707,
    ARM_t2UMLAL	= 2708,
    ARM_t2UMULL	= 2709,
    ARM_t2UQADD16	= 2710,
    ARM_t2UQADD8	= 2711,
    ARM_t2UQASX	= 2712,
    ARM_t2UQSAX	= 2713,
    ARM_t2UQSUB16	= 2714,
    ARM_t2UQSUB8	= 2715,
    ARM_t2USAD8	= 2716,
    ARM_t2USADA8	= 2717,
    ARM_t2USAT	= 2718,
    ARM_t2USAT16	= 2719,
    ARM_t2USAX	= 2720,
    ARM_t2USUB16	= 2721,
    ARM_t2USUB8	= 2722,
    ARM_t2UXTAB	= 2723,
    ARM_t2UXTAB16	= 2724,
    ARM_t2UXTAH	= 2725,
    ARM_t2UXTB	= 2726,
    ARM_t2UXTB16	= 2727,
    ARM_t2UXTH	= 2728,
    ARM_tADC	= 2729,
    ARM_tADDhirr	= 2730,
    ARM_tADDi3	= 2731,
    ARM_tADDi8	= 2732,
    ARM_tADDrSP	= 2733,
    ARM_tADDrSPi	= 2734,
    ARM_tADDrr	= 2735,
    ARM_tADDspi	= 2736,
    ARM_tADDspr	= 2737,
    ARM_tADJCALLSTACKDOWN	= 2738,
    ARM_tADJCALLSTACKUP	= 2739,
    ARM_tADR	= 2740,
    ARM_tAND	= 2741,
    ARM_tASRri	= 2742,
    ARM_tASRrr	= 2743,
    ARM_tB	= 2744,
    ARM_tBIC	= 2745,
    ARM_tBKPT	= 2746,
    ARM_tBL	= 2747,
    ARM_tBLXi	= 2748,
    ARM_tBLXr	= 2749,
    ARM_tBRIND	= 2750,
    ARM_tBR_JTr	= 2751,
    ARM_tBX	= 2752,
    ARM_tBX_CALL	= 2753,
    ARM_tBX_RET	= 2754,
    ARM_tBX_RET_vararg	= 2755,
    ARM_tBcc	= 2756,
    ARM_tBfar	= 2757,
    ARM_tCBNZ	= 2758,
    ARM_tCBZ	= 2759,
    ARM_tCMNz	= 2760,
    ARM_tCMPhir	= 2761,
    ARM_tCMPi8	= 2762,
    ARM_tCMPr	= 2763,
    ARM_tCPS	= 2764,
    ARM_tEOR	= 2765,
    ARM_tHINT	= 2766,
    ARM_tHLT	= 2767,
    ARM_tInt_eh_sjlj_longjmp	= 2768,
    ARM_tInt_eh_sjlj_setjmp	= 2769,
    ARM_tLDMIA	= 2770,
    ARM_tLDMIA_UPD	= 2771,
    ARM_tLDRBi	= 2772,
    ARM_tLDRBr	= 2773,
    ARM_tLDRHi	= 2774,
    ARM_tLDRHr	= 2775,
    ARM_tLDRLIT_ga_abs	= 2776,
    ARM_tLDRLIT_ga_pcrel	= 2777,
    ARM_tLDRSB	= 2778,
    ARM_tLDRSH	= 2779,
    ARM_tLDRi	= 2780,
    ARM_tLDRpci	= 2781,
    ARM_tLDRpci_pic	= 2782,
    ARM_tLDRr	= 2783,
    ARM_tLDRspi	= 2784,
    ARM_tLEApcrel	= 2785,
    ARM_tLEApcrelJT	= 2786,
    ARM_tLSLri	= 2787,
    ARM_tLSLrr	= 2788,
    ARM_tLSRri	= 2789,
    ARM_tLSRrr	= 2790,
    ARM_tMOVCCr_pseudo	= 2791,
    ARM_tMOVSr	= 2792,
    ARM_tMOVi8	= 2793,
    ARM_tMOVr	= 2794,
    ARM_tMUL	= 2795,
    ARM_tMVN	= 2796,
    ARM_tORR	= 2797,
    ARM_tPICADD	= 2798,
    ARM_tPOP	= 2799,
    ARM_tPOP_RET	= 2800,
    ARM_tPUSH	= 2801,
    ARM_tREV	= 2802,
    ARM_tREV16	= 2803,
    ARM_tREVSH	= 2804,
    ARM_tROR	= 2805,
    ARM_tRSB	= 2806,
    ARM_tSBC	= 2807,
    ARM_tSETEND	= 2808,
    ARM_tSTMIA_UPD	= 2809,
    ARM_tSTRBi	= 2810,
    ARM_tSTRBr	= 2811,
    ARM_tSTRHi	= 2812,
    ARM_tSTRHr	= 2813,
    ARM_tSTRi	= 2814,
    ARM_tSTRr	= 2815,
    ARM_tSTRspi	= 2816,
    ARM_tSUBi3	= 2817,
    ARM_tSUBi8	= 2818,
    ARM_tSUBrr	= 2819,
    ARM_tSUBspi	= 2820,
    ARM_tSVC	= 2821,
    ARM_tSXTB	= 2822,
    ARM_tSXTH	= 2823,
    ARM_tTAILJMPd	= 2824,
    ARM_tTAILJMPdND	= 2825,
    ARM_tTAILJMPr	= 2826,
    ARM_tTPsoft	= 2827,
    ARM_tTRAP	= 2828,
    ARM_tTST	= 2829,
    ARM_tUXTB	= 2830,
    ARM_tUXTH	= 2831,
    ARM_INSTRUCTION_LIST_END = 2832
};

#endif // GET_INSTRINFO_ENUM


#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC

static uint16_t ImplicitList1[] = { ARM_CPSR, 0 };
static uint16_t ImplicitList2[] = { ARM_SP, 0 };
static uint16_t ImplicitList3[] = { ARM_LR, 0 };
static uint16_t ImplicitList4[] = { ARM_FPSCR_NZCV, 0 };
static uint16_t ImplicitList5[] = { ARM_R7, ARM_LR, ARM_SP, 0 };
static uint16_t ImplicitList6[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 0 };
static uint16_t ImplicitList7[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, 0 };
static uint16_t ImplicitList8[] = { ARM_R0, ARM_R12, ARM_LR, ARM_CPSR, 0 };
static uint16_t ImplicitList9[] = { ARM_FPSCR, 0 };
static uint16_t ImplicitList10[] = { ARM_ITSTATE, 0 };
static uint16_t ImplicitList11[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 0 };
static uint16_t ImplicitList12[] = { ARM_PC, 0 };
static uint16_t ImplicitList13[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R12, ARM_CPSR, 0 };

static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo10[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo11[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo14[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo15[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo16[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo22[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo23[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo24[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo25[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo26[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo27[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo28[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo29[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo34[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo36[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo38[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo39[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo40[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo41[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo42[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo47[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo49[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo50[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo51[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo52[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo55[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo56[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo57[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo58[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo61[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo62[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo64[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo66[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo67[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo71[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo72[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo73[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo74[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo75[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo76[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo80[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo81[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo82[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo84[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo85[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo86[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo87[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo88[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo89[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo90[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo91[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo92[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo93[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo94[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo95[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo96[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo97[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo98[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo99[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo100[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo101[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo102[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo103[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo104[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo105[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo106[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo107[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo108[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo109[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo110[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo111[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo112[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo118[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo119[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo121[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo122[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo123[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo124[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo125[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo126[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo127[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo128[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo129[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo130[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo131[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo132[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo133[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo134[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo135[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo136[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo137[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo138[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo139[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo140[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo141[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo143[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo144[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo145[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo146[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo147[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo148[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo149[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo150[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo151[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo152[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo153[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo154[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo155[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo156[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo157[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo158[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo159[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo160[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo161[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo162[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo163[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo164[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo165[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo166[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo167[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo168[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo169[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo170[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo171[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo172[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo174[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo175[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo176[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo177[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo178[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo179[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo180[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo181[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo182[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo183[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo184[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo185[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo186[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo187[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo188[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo190[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo191[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo192[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo193[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo194[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo195[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo196[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo198[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo199[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo200[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo201[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo202[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo203[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo204[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo205[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo206[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo207[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo208[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo209[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo210[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo211[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo214[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo215[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo216[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo217[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo219[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo220[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo221[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo222[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo223[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo226[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo227[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo228[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo229[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo230[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo231[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo259[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo260[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo261[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo263[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo267[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo274[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo278[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo283[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo286[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo287[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo288[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo291[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo292[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo296[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo298[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo299[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo308[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo309[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo310[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo314[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo316[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo324[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo326[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo327[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo328[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo329[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo330[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo331[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo334[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo335[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo336[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo337[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo338[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo339[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo340[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo341[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo342[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo343[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo357[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo358[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo359[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo360[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo361[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };

static MCInstrDesc ARMInsts[] = {
  { 0,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #0 = PHI
  { 1,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #1 = INLINEASM
  { 2,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #2 = PROLOG_LABEL
  { 3,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #3 = EH_LABEL
  { 4,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #4 = GC_LABEL
  { 5,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #5 = KILL
  { 6,	3,	1,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #6 = EXTRACT_SUBREG
  { 7,	4,	1,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo4,0,0 },  // Inst #7 = INSERT_SUBREG
  { 8,	1,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #8 = IMPLICIT_DEF
  { 9,	4,	1,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo6,0,0 },  // Inst #9 = SUBREG_TO_REG
  { 10,	3,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #10 = COPY_TO_REGCLASS
  { 11,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #11 = DBG_VALUE
  { 12,	1,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #12 = REG_SEQUENCE
  { 13,	2,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #13 = COPY
  { 14,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #14 = BUNDLE
  { 15,	1,	0,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #15 = LIFETIME_START
  { 16,	1,	0,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #16 = LIFETIME_END
  { 17,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo8,0,0 },  // Inst #17 = STACKMAP
  { 18,	6,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo9,0,0 },  // Inst #18 = PATCHPOINT
  { 19,	2,	1,	590,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo10,0,0 },  // Inst #19 = ABS
  { 20,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo11,0,0 },  // Inst #20 = ADCri
  { 21,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,0 },  // Inst #21 = ADCrr
  { 22,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,0 },  // Inst #22 = ADCrsi
  { 23,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,0 },  // Inst #23 = ADCrsr
  { 24,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo15,0,0 },  // Inst #24 = ADDSri
  { 25,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo16,0,0 },  // Inst #25 = ADDSrr
  { 26,	6,	1,	3,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo17,0,0 },  // Inst #26 = ADDSrsi
  { 27,	7,	1,	5,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo18,0,0 },  // Inst #27 = ADDSrsr
  { 28,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #28 = ADDri
  { 29,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #29 = ADDrr
  { 30,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #30 = ADDrsi
  { 31,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #31 = ADDrsr
  { 32,	3,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo20,0,0 },  // Inst #32 = ADJCALLSTACKDOWN
  { 33,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo21,0,0 },  // Inst #33 = ADJCALLSTACKUP
  { 34,	4,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xd01ULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #34 = ADR
  { 35,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #35 = AESD
  { 36,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #36 = AESE
  { 37,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #37 = AESIMC
  { 38,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #38 = AESMC
  { 39,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #39 = ANDri
  { 40,	6,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #40 = ANDrr
  { 41,	7,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #41 = ANDrsi
  { 42,	8,	1,	267,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #42 = ANDrsr
  { 43,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #43 = ASRi
  { 44,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #44 = ASRr
  { 45,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo26,0,0 },  // Inst #45 = ATOMIC_CMP_SWAP_I16
  { 46,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo26,0,0 },  // Inst #46 = ATOMIC_CMP_SWAP_I32
  { 47,	8,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo27,0,0 },  // Inst #47 = ATOMIC_CMP_SWAP_I64
  { 48,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo26,0,0 },  // Inst #48 = ATOMIC_CMP_SWAP_I8
  { 49,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #49 = ATOMIC_LOAD_ADD_I16
  { 50,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #50 = ATOMIC_LOAD_ADD_I32
  { 51,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #51 = ATOMIC_LOAD_ADD_I64
  { 52,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #52 = ATOMIC_LOAD_ADD_I8
  { 53,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #53 = ATOMIC_LOAD_AND_I16
  { 54,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #54 = ATOMIC_LOAD_AND_I32
  { 55,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #55 = ATOMIC_LOAD_AND_I64
  { 56,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #56 = ATOMIC_LOAD_AND_I8
  { 57,	4,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #57 = ATOMIC_LOAD_I64
  { 58,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #58 = ATOMIC_LOAD_MAX_I16
  { 59,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #59 = ATOMIC_LOAD_MAX_I32
  { 60,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #60 = ATOMIC_LOAD_MAX_I64
  { 61,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #61 = ATOMIC_LOAD_MAX_I8
  { 62,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #62 = ATOMIC_LOAD_MIN_I16
  { 63,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #63 = ATOMIC_LOAD_MIN_I32
  { 64,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #64 = ATOMIC_LOAD_MIN_I64
  { 65,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #65 = ATOMIC_LOAD_MIN_I8
  { 66,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #66 = ATOMIC_LOAD_NAND_I16
  { 67,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #67 = ATOMIC_LOAD_NAND_I32
  { 68,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #68 = ATOMIC_LOAD_NAND_I64
  { 69,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #69 = ATOMIC_LOAD_NAND_I8
  { 70,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #70 = ATOMIC_LOAD_OR_I16
  { 71,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #71 = ATOMIC_LOAD_OR_I32
  { 72,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #72 = ATOMIC_LOAD_OR_I64
  { 73,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #73 = ATOMIC_LOAD_OR_I8
  { 74,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #74 = ATOMIC_LOAD_SUB_I16
  { 75,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #75 = ATOMIC_LOAD_SUB_I32
  { 76,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #76 = ATOMIC_LOAD_SUB_I64
  { 77,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #77 = ATOMIC_LOAD_SUB_I8
  { 78,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #78 = ATOMIC_LOAD_UMAX_I16
  { 79,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #79 = ATOMIC_LOAD_UMAX_I32
  { 80,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #80 = ATOMIC_LOAD_UMAX_I64
  { 81,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #81 = ATOMIC_LOAD_UMAX_I8
  { 82,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #82 = ATOMIC_LOAD_UMIN_I16
  { 83,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #83 = ATOMIC_LOAD_UMIN_I32
  { 84,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #84 = ATOMIC_LOAD_UMIN_I64
  { 85,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #85 = ATOMIC_LOAD_UMIN_I8
  { 86,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #86 = ATOMIC_LOAD_XOR_I16
  { 87,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #87 = ATOMIC_LOAD_XOR_I32
  { 88,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #88 = ATOMIC_LOAD_XOR_I64
  { 89,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #89 = ATOMIC_LOAD_XOR_I8
  { 90,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #90 = ATOMIC_STORE_I64
  { 91,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #91 = ATOMIC_SWAP_I16
  { 92,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #92 = ATOMIC_SWAP_I32
  { 93,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #93 = ATOMIC_SWAP_I64
  { 94,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #94 = ATOMIC_SWAP_I8
  { 95,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo30,0,0 },  // Inst #95 = B
  { 96,	4,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo31,0,0 },  // Inst #96 = BCCZi64
  { 97,	6,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo32,0,0 },  // Inst #97 = BCCi64
  { 98,	5,	1,	278,	4,	0|(1<<MCID_Predicable), 0x201ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #98 = BFC
  { 99,	6,	1,	278,	4,	0|(1<<MCID_Predicable), 0x201ULL, NULL, NULL, OperandInfo34,0,0 },  // Inst #99 = BFI
  { 100,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #100 = BICri
  { 101,	6,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #101 = BICrr
  { 102,	7,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #102 = BICrsi
  { 103,	8,	1,	267,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #103 = BICrsr
  { 104,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #104 = BKPT
  { 105,	1,	0,	12,	4,	0|(1<<MCID_Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo30,0,0 },  // Inst #105 = BL
  { 106,	1,	0,	12,	4,	0|(1<<MCID_Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,0 },  // Inst #106 = BLX
  { 107,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,0 },  // Inst #107 = BLX_pred
  { 108,	1,	0,	13,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x180ULL, NULL, NULL, OperandInfo30,0,0 },  // Inst #108 = BLXi
  { 109,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo37,0,0 },  // Inst #109 = BL_pred
  { 110,	1,	0,	10,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo30,0,0 },  // Inst #110 = BMOVPCB_CALL
  { 111,	1,	0,	10,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo38,0,0 },  // Inst #111 = BMOVPCRX_CALL
  { 112,	4,	0,	14,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo39,0,0 },  // Inst #112 = BR_JTadd
  { 113,	5,	0,	14,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo40,0,0 },  // Inst #113 = BR_JTm
  { 114,	3,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo41,0,0 },  // Inst #114 = BR_JTr
  { 115,	1,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x180ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #115 = BX
  { 116,	3,	0,	15,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #116 = BXJ
  { 117,	1,	0,	10,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo38,0,0 },  // Inst #117 = BX_CALL
  { 118,	2,	0,	10,	4,	0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #118 = BX_RET
  { 119,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x180ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #119 = BX_pred
  { 120,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #120 = Bcc
  { 121,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo43,0,0 },  // Inst #121 = CDP
  { 122,	6,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo44,0,0 },  // Inst #122 = CDP2
  { 123,	0,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, 0,0,0 },  // Inst #123 = CLREX
  { 124,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #124 = CLZ
  { 125,	4,	0,	17,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #125 = CMNri
  { 126,	4,	0,	18,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #126 = CMNzrr
  { 127,	5,	0,	19,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #127 = CMNzrsi
  { 128,	6,	0,	20,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #128 = CMNzrsr
  { 129,	4,	0,	17,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #129 = CMPri
  { 130,	4,	0,	18,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #130 = CMPrr
  { 131,	5,	0,	19,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #131 = CMPrsi
  { 132,	6,	0,	20,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #132 = CMPrsr
  { 133,	3,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #133 = CONSTPOOL_ENTRY
  { 134,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo39,0,0 },  // Inst #134 = COPY_STRUCT_BYVAL_I32
  { 135,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #135 = CPS1p
  { 136,	2,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #136 = CPS2p
  { 137,	3,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo48,0,0 },  // Inst #137 = CPS3p
  { 138,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #138 = CRC32B
  { 139,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #139 = CRC32CB
  { 140,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #140 = CRC32CH
  { 141,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #141 = CRC32CW
  { 142,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #142 = CRC32H
  { 143,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #143 = CRC32W
  { 144,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #144 = DBG
  { 145,	1,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #145 = DMB
  { 146,	1,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #146 = DSB
  { 147,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #147 = EORri
  { 148,	6,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #148 = EORrr
  { 149,	7,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #149 = EORrsi
  { 150,	8,	1,	267,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #150 = EORrsr
  { 151,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #151 = FCONSTD
  { 152,	4,	1,	488,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, NULL, NULL, OperandInfo52,0,0 },  // Inst #152 = FCONSTS
  { 153,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #153 = FLDMXDB_UPD
  { 154,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #154 = FLDMXIA
  { 155,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #155 = FLDMXIA_UPD
  { 156,	2,	0,	507,	4,	0|(1<<MCID_Predicable), 0x8c00ULL, ImplicitList4, ImplicitList1, OperandInfo42,0,0 },  // Inst #156 = FMSTAT
  { 157,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #157 = FSTMXDB_UPD
  { 158,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #158 = FSTMXIA
  { 159,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #159 = FSTMXIA_UPD
  { 160,	3,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #160 = HINT
  { 161,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #161 = HLT
  { 162,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #162 = ISB
  { 163,	2,	0,	377,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #163 = ITasm
  { 164,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #164 = Int_eh_sjlj_dispatchsetup
  { 165,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList5, OperandInfo10,0,0 },  // Inst #165 = Int_eh_sjlj_longjmp
  { 166,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList6, OperandInfo10,0,0 },  // Inst #166 = Int_eh_sjlj_setjmp
  { 167,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList7, OperandInfo10,0,0 },  // Inst #167 = Int_eh_sjlj_setjmp_nofp
  { 168,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #168 = LDA
  { 169,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #169 = LDAB
  { 170,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #170 = LDAEX
  { 171,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #171 = LDAEXB
  { 172,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo56,0,0 },  // Inst #172 = LDAEXD
  { 173,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #173 = LDAEXH
  { 174,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #174 = LDAH
  { 175,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #175 = LDC2L_OFFSET
  { 176,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #176 = LDC2L_OPTION
  { 177,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #177 = LDC2L_POST
  { 178,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #178 = LDC2L_PRE
  { 179,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #179 = LDC2_OFFSET
  { 180,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #180 = LDC2_OPTION
  { 181,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #181 = LDC2_POST
  { 182,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #182 = LDC2_PRE
  { 183,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #183 = LDCL_OFFSET
  { 184,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #184 = LDCL_OPTION
  { 185,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #185 = LDCL_POST
  { 186,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #186 = LDCL_PRE
  { 187,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #187 = LDC_OFFSET
  { 188,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #188 = LDC_OPTION
  { 189,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #189 = LDC_POST
  { 190,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #190 = LDC_PRE
  { 191,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #191 = LDMDA
  { 192,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #192 = LDMDA_UPD
  { 193,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #193 = LDMDB
  { 194,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #194 = LDMDB_UPD
  { 195,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #195 = LDMIA
  { 196,	5,	1,	355,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #196 = LDMIA_RET
  { 197,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #197 = LDMIA_UPD
  { 198,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #198 = LDMIB
  { 199,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #199 = LDMIB_UPD
  { 200,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #200 = LDRBT_POST
  { 201,	7,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #201 = LDRBT_POST_IMM
  { 202,	7,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #202 = LDRBT_POST_REG
  { 203,	7,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #203 = LDRB_POST_IMM
  { 204,	7,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #204 = LDRB_POST_REG
  { 205,	6,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #205 = LDRB_PRE_IMM
  { 206,	7,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #206 = LDRB_PRE_REG
  { 207,	5,	1,	325,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, NULL, NULL, OperandInfo61,0,0 },  // Inst #207 = LDRBi12
  { 208,	6,	1,	326,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, NULL, NULL, OperandInfo62,0,0 },  // Inst #208 = LDRBrs
  { 209,	7,	2,	350,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x403ULL, NULL, NULL, OperandInfo63,0,0 },  // Inst #209 = LDRD
  { 210,	6,	1,	31,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x403ULL, NULL, NULL, OperandInfo64,0,0 },  // Inst #210 = LDRD_PAIR
  { 211,	8,	3,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x443ULL, NULL, NULL, OperandInfo65,0,0 },  // Inst #211 = LDRD_POST
  { 212,	8,	3,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x423ULL, NULL, NULL, OperandInfo65,0,0 },  // Inst #212 = LDRD_PRE
  { 213,	4,	1,	327,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #213 = LDREX
  { 214,	4,	1,	327,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #214 = LDREXB
  { 215,	4,	1,	327,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo56,0,0 },  // Inst #215 = LDREXD
  { 216,	4,	1,	327,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #216 = LDREXH
  { 217,	6,	1,	335,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, NULL, NULL, OperandInfo66,0,0 },  // Inst #217 = LDRH
  { 218,	6,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #218 = LDRHTi
  { 219,	7,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #219 = LDRHTr
  { 220,	7,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #220 = LDRH_POST
  { 221,	7,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #221 = LDRH_PRE
  { 222,	2,	1,	33,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo69,0,0 },  // Inst #222 = LDRLIT_ga_abs
  { 223,	2,	1,	34,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo69,0,0 },  // Inst #223 = LDRLIT_ga_pcrel
  { 224,	2,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo69,0,0 },  // Inst #224 = LDRLIT_ga_pcrel_ldr
  { 225,	6,	1,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, NULL, NULL, OperandInfo66,0,0 },  // Inst #225 = LDRSB
  { 226,	6,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #226 = LDRSBTi
  { 227,	7,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #227 = LDRSBTr
  { 228,	7,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #228 = LDRSB_POST
  { 229,	7,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #229 = LDRSB_PRE
  { 230,	6,	1,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, NULL, NULL, OperandInfo66,0,0 },  // Inst #230 = LDRSH
  { 231,	6,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #231 = LDRSHTi
  { 232,	7,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #232 = LDRSHTr
  { 233,	7,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #233 = LDRSH_POST
  { 234,	7,	2,	289,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #234 = LDRSH_PRE
  { 235,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #235 = LDRT_POST
  { 236,	7,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #236 = LDRT_POST_IMM
  { 237,	7,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #237 = LDRT_POST_REG
  { 238,	7,	2,	345,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #238 = LDR_POST_IMM
  { 239,	7,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #239 = LDR_POST_REG
  { 240,	6,	2,	345,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #240 = LDR_PRE_IMM
  { 241,	7,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #241 = LDR_PRE_REG
  { 242,	5,	1,	336,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #242 = LDRcp
  { 243,	5,	1,	328,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #243 = LDRi12
  { 244,	6,	1,	287,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, NULL, NULL, OperandInfo70,0,0 },  // Inst #244 = LDRrs
  { 245,	4,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo71,0,0 },  // Inst #245 = LEApcrel
  { 246,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo72,0,0 },  // Inst #246 = LEApcrelJT
  { 247,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #247 = LSLi
  { 248,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #248 = LSLr
  { 249,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #249 = LSRi
  { 250,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #250 = LSRr
  { 251,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo73,0,0 },  // Inst #251 = MCR
  { 252,	6,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo74,0,0 },  // Inst #252 = MCR2
  { 253,	7,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo75,0,0 },  // Inst #253 = MCRR
  { 254,	5,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo76,0,0 },  // Inst #254 = MCRR2
  { 255,	7,	1,	279,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #255 = MLA
  { 256,	7,	1,	279,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo78,0,0 },  // Inst #256 = MLAv5
  { 257,	6,	1,	279,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #257 = MLS
  { 258,	5,	1,	40,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #258 = MOVCCi
  { 259,	5,	1,	41,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #259 = MOVCCi16
  { 260,	5,	1,	273,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo80,0,0 },  // Inst #260 = MOVCCi32imm
  { 261,	5,	1,	43,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, NULL, NULL, OperandInfo81,0,0 },  // Inst #261 = MOVCCr
  { 262,	6,	1,	268,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo82,0,0 },  // Inst #262 = MOVCCsi
  { 263,	7,	1,	268,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo83,0,0 },  // Inst #263 = MOVCCsr
  { 264,	2,	0,	10,	4,	0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #264 = MOVPCLR
  { 265,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #265 = MOVPCRX
  { 266,	5,	1,	41,	4,	0|(1<<MCID_Predicable), 0x2201ULL, NULL, NULL, OperandInfo84,0,0 },  // Inst #266 = MOVTi16
  { 267,	4,	1,	41,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo85,0,0 },  // Inst #267 = MOVTi16_ga_pcrel
  { 268,	2,	1,	275,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo69,0,0 },  // Inst #268 = MOV_ga_pcrel
  { 269,	2,	1,	276,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo69,0,0 },  // Inst #269 = MOV_ga_pcrel_ldr
  { 270,	5,	1,	41,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, NULL, NULL, OperandInfo86,0,0 },  // Inst #270 = MOVi
  { 271,	4,	1,	41,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x2201ULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #271 = MOVi16
  { 272,	3,	1,	41,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo87,0,0 },  // Inst #272 = MOVi16_ga_pcrel
  { 273,	2,	1,	274,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo69,0,0 },  // Inst #273 = MOVi32imm
  { 274,	5,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, NULL, NULL, OperandInfo88,0,0 },  // Inst #274 = MOVr
  { 275,	5,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, NULL, NULL, OperandInfo89,0,0 },  // Inst #275 = MOVr_TC
  { 276,	6,	1,	269,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, NULL, NULL, OperandInfo90,0,0 },  // Inst #276 = MOVsi
  { 277,	7,	1,	269,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, NULL, NULL, OperandInfo91,0,0 },  // Inst #277 = MOVsr
  { 278,	2,	1,	270,	0,	0|(1<<MCID_Pseudo), 0x2000ULL, NULL, ImplicitList1, OperandInfo10,0,0 },  // Inst #278 = MOVsra_flag
  { 279,	2,	1,	270,	0,	0|(1<<MCID_Pseudo), 0x2000ULL, NULL, ImplicitList1, OperandInfo10,0,0 },  // Inst #279 = MOVsrl_flag
  { 280,	8,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo92,0,0 },  // Inst #280 = MRC
  { 281,	6,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo93,0,0 },  // Inst #281 = MRC2
  { 282,	7,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo75,0,0 },  // Inst #282 = MRRC
  { 283,	5,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo76,0,0 },  // Inst #283 = MRRC2
  { 284,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo94,0,0 },  // Inst #284 = MRS
  { 285,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo94,0,0 },  // Inst #285 = MRSsys
  { 286,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo95,0,0 },  // Inst #286 = MSR
  { 287,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo96,0,0 },  // Inst #287 = MSRi
  { 288,	6,	1,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #288 = MUL
  { 289,	6,	1,	280,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo97,0,0 },  // Inst #289 = MULv5
  { 290,	5,	1,	40,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #290 = MVNCCi
  { 291,	5,	1,	52,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, NULL, NULL, OperandInfo86,0,0 },  // Inst #291 = MVNi
  { 292,	5,	1,	272,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, NULL, NULL, OperandInfo88,0,0 },  // Inst #292 = MVNr
  { 293,	6,	1,	54,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, NULL, NULL, OperandInfo90,0,0 },  // Inst #293 = MVNsi
  { 294,	7,	1,	271,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, NULL, NULL, OperandInfo98,0,0 },  // Inst #294 = MVNsr
  { 295,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #295 = ORRri
  { 296,	6,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #296 = ORRrr
  { 297,	7,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #297 = ORRrsi
  { 298,	8,	1,	267,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #298 = ORRrsr
  { 299,	5,	1,	55,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo15,0,0 },  // Inst #299 = PICADD
  { 300,	5,	1,	286,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #300 = PICLDR
  { 301,	5,	1,	335,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #301 = PICLDRB
  { 302,	5,	1,	335,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #302 = PICLDRH
  { 303,	5,	1,	288,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #303 = PICLDRSB
  { 304,	5,	1,	288,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #304 = PICLDRSH
  { 305,	5,	0,	358,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #305 = PICSTR
  { 306,	5,	0,	359,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #306 = PICSTRB
  { 307,	5,	0,	359,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #307 = PICSTRH
  { 308,	6,	1,	58,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo99,0,0 },  // Inst #308 = PKHBT
  { 309,	6,	1,	59,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo99,0,0 },  // Inst #309 = PKHTB
  { 310,	2,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo100,0,0 },  // Inst #310 = PLDWi12
  { 311,	3,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #311 = PLDWrs
  { 312,	2,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo100,0,0 },  // Inst #312 = PLDi12
  { 313,	3,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #313 = PLDrs
  { 314,	2,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo100,0,0 },  // Inst #314 = PLIi12
  { 315,	3,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #315 = PLIrs
  { 316,	5,	1,	299,	4,	0|(1<<MCID_Predicable), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #316 = QADD
  { 317,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #317 = QADD16
  { 318,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #318 = QADD8
  { 319,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #319 = QASX
  { 320,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #320 = QDADD
  { 321,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #321 = QDSUB
  { 322,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #322 = QSAX
  { 323,	5,	1,	299,	4,	0|(1<<MCID_Predicable), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #323 = QSUB
  { 324,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #324 = QSUB16
  { 325,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #325 = QSUB8
  { 326,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #326 = RBIT
  { 327,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #327 = REV
  { 328,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #328 = REV16
  { 329,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #329 = REVSH
  { 330,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #330 = RFEDA
  { 331,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #331 = RFEDA_UPD
  { 332,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #332 = RFEDB
  { 333,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #333 = RFEDB_UPD
  { 334,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #334 = RFEIA
  { 335,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #335 = RFEIA_UPD
  { 336,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #336 = RFEIB
  { 337,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #337 = RFEIB_UPD
  { 338,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #338 = RORi
  { 339,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #339 = RORr
  { 340,	2,	1,	50,	0,	0|(1<<MCID_Pseudo), 0x2000ULL, ImplicitList1, NULL, OperandInfo10,0,0 },  // Inst #340 = RRX
  { 341,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo88,0,0 },  // Inst #341 = RRXi
  { 342,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo15,0,0 },  // Inst #342 = RSBSri
  { 343,	6,	1,	3,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo17,0,0 },  // Inst #343 = RSBSrsi
  { 344,	7,	1,	5,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo18,0,0 },  // Inst #344 = RSBSrsr
  { 345,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #345 = RSBri
  { 346,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #346 = RSBrr
  { 347,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #347 = RSBrsi
  { 348,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #348 = RSBrsr
  { 349,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo11,0,0 },  // Inst #349 = RSCri
  { 350,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,0 },  // Inst #350 = RSCrr
  { 351,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,0 },  // Inst #351 = RSCrsi
  { 352,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo19,0,0 },  // Inst #352 = RSCrsr
  { 353,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #353 = SADD16
  { 354,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #354 = SADD8
  { 355,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #355 = SASX
  { 356,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo11,0,0 },  // Inst #356 = SBCri
  { 357,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,0 },  // Inst #357 = SBCrr
  { 358,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,0 },  // Inst #358 = SBCrsi
  { 359,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,0 },  // Inst #359 = SBCrsr
  { 360,	6,	1,	278,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #360 = SBFX
  { 361,	5,	1,	324,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #361 = SDIV
  { 362,	5,	1,	277,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #362 = SEL
  { 363,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,ARM_HasV8Ops,0 },  // Inst #363 = SETEND
  { 364,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #364 = SHA1C
  { 365,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #365 = SHA1H
  { 366,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #366 = SHA1M
  { 367,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #367 = SHA1P
  { 368,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #368 = SHA1SU0
  { 369,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #369 = SHA1SU1
  { 370,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #370 = SHA256H
  { 371,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #371 = SHA256H2
  { 372,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #372 = SHA256SU0
  { 373,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #373 = SHA256SU1
  { 374,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #374 = SHADD16
  { 375,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #375 = SHADD8
  { 376,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #376 = SHASX
  { 377,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #377 = SHSAX
  { 378,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #378 = SHSUB16
  { 379,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #379 = SHSUB8
  { 380,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #380 = SMC
  { 381,	6,	1,	285,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #381 = SMLABB
  { 382,	6,	1,	285,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #382 = SMLABT
  { 383,	6,	1,	319,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #383 = SMLAD
  { 384,	6,	1,	319,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #384 = SMLADX
  { 385,	9,	2,	281,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #385 = SMLAL
  { 386,	6,	2,	281,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #386 = SMLALBB
  { 387,	6,	2,	281,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #387 = SMLALBT
  { 388,	6,	2,	283,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #388 = SMLALD
  { 389,	6,	2,	283,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #389 = SMLALDX
  { 390,	6,	2,	281,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #390 = SMLALTB
  { 391,	6,	2,	281,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #391 = SMLALTT
  { 392,	9,	2,	281,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo108,0,0 },  // Inst #392 = SMLALv5
  { 393,	6,	1,	285,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #393 = SMLATB
  { 394,	6,	1,	285,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #394 = SMLATT
  { 395,	6,	1,	285,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #395 = SMLAWB
  { 396,	6,	1,	285,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #396 = SMLAWT
  { 397,	6,	1,	316,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #397 = SMLSD
  { 398,	6,	1,	316,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #398 = SMLSDX
  { 399,	6,	2,	283,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #399 = SMLSLD
  { 400,	6,	2,	283,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #400 = SMLSLDX
  { 401,	6,	1,	279,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #401 = SMMLA
  { 402,	6,	1,	279,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #402 = SMMLAR
  { 403,	6,	1,	279,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #403 = SMMLS
  { 404,	6,	1,	279,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #404 = SMMLSR
  { 405,	5,	1,	280,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #405 = SMMUL
  { 406,	5,	1,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #406 = SMMULR
  { 407,	5,	1,	314,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #407 = SMUAD
  { 408,	5,	1,	314,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #408 = SMUADX
  { 409,	5,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #409 = SMULBB
  { 410,	5,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #410 = SMULBT
  { 411,	7,	2,	321,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #411 = SMULL
  { 412,	7,	2,	282,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo109,0,0 },  // Inst #412 = SMULLv5
  { 413,	5,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #413 = SMULTB
  { 414,	5,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #414 = SMULTT
  { 415,	5,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #415 = SMULWB
  { 416,	5,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #416 = SMULWT
  { 417,	5,	1,	309,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #417 = SMUSD
  { 418,	5,	1,	309,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #418 = SMUSDX
  { 419,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #419 = SRSDA
  { 420,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #420 = SRSDA_UPD
  { 421,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #421 = SRSDB
  { 422,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #422 = SRSDB_UPD
  { 423,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #423 = SRSIA
  { 424,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #424 = SRSIA_UPD
  { 425,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #425 = SRSIB
  { 426,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #426 = SRSIB_UPD
  { 427,	6,	1,	300,	4,	0|(1<<MCID_Predicable), 0x680ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #427 = SSAT
  { 428,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, NULL, NULL, OperandInfo111,0,0 },  // Inst #428 = SSAT16
  { 429,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #429 = SSAX
  { 430,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #430 = SSUB16
  { 431,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #431 = SSUB8
  { 432,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #432 = STC2L_OFFSET
  { 433,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #433 = STC2L_OPTION
  { 434,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #434 = STC2L_POST
  { 435,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #435 = STC2L_PRE
  { 436,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #436 = STC2_OFFSET
  { 437,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #437 = STC2_OPTION
  { 438,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #438 = STC2_POST
  { 439,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #439 = STC2_PRE
  { 440,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #440 = STCL_OFFSET
  { 441,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #441 = STCL_OPTION
  { 442,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #442 = STCL_POST
  { 443,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #443 = STCL_PRE
  { 444,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #444 = STC_OFFSET
  { 445,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #445 = STC_OPTION
  { 446,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #446 = STC_POST
  { 447,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #447 = STC_PRE
  { 448,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #448 = STL
  { 449,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #449 = STLB
  { 450,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #450 = STLEX
  { 451,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #451 = STLEXB
  { 452,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo113,0,0 },  // Inst #452 = STLEXD
  { 453,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #453 = STLEXH
  { 454,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #454 = STLH
  { 455,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #455 = STMDA
  { 456,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #456 = STMDA_UPD
  { 457,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #457 = STMDB
  { 458,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #458 = STMDB_UPD
  { 459,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #459 = STMIA
  { 460,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #460 = STMIA_UPD
  { 461,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #461 = STMIB
  { 462,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #462 = STMIB_UPD
  { 463,	4,	0,	365,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #463 = STRBT_POST
  { 464,	7,	1,	366,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #464 = STRBT_POST_IMM
  { 465,	7,	1,	366,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #465 = STRBT_POST_REG
  { 466,	7,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #466 = STRB_POST_IMM
  { 467,	7,	1,	366,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #467 = STRB_POST_REG
  { 468,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo115,0,0 },  // Inst #468 = STRB_PRE_IMM
  { 469,	7,	1,	366,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #469 = STRB_PRE_REG
  { 470,	5,	0,	359,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, NULL, NULL, OperandInfo61,0,0 },  // Inst #470 = STRBi12
  { 471,	7,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo116,0,0 },  // Inst #471 = STRBi_preidx
  { 472,	7,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo116,0,0 },  // Inst #472 = STRBr_preidx
  { 473,	6,	0,	360,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, NULL, NULL, OperandInfo62,0,0 },  // Inst #473 = STRBrs
  { 474,	7,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x483ULL, NULL, NULL, OperandInfo63,0,0 },  // Inst #474 = STRD
  { 475,	6,	0,	72,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x483ULL, NULL, NULL, OperandInfo64,0,0 },  // Inst #475 = STRD_PAIR
  { 476,	8,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4c3ULL, NULL, NULL, OperandInfo117,0,0 },  // Inst #476 = STRD_POST
  { 477,	8,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4a3ULL, NULL, NULL, OperandInfo117,0,0 },  // Inst #477 = STRD_PRE
  { 478,	5,	1,	361,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #478 = STREX
  { 479,	5,	1,	361,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #479 = STREXB
  { 480,	5,	1,	361,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo113,0,0 },  // Inst #480 = STREXD
  { 481,	5,	1,	361,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #481 = STREXH
  { 482,	6,	0,	359,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x483ULL, NULL, NULL, OperandInfo66,0,0 },  // Inst #482 = STRH
  { 483,	6,	1,	366,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, NULL, NULL, OperandInfo115,0,0 },  // Inst #483 = STRHTi
  { 484,	7,	1,	366,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #484 = STRHTr
  { 485,	7,	1,	366,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x4c3ULL, NULL, NULL, OperandInfo118,0,0 },  // Inst #485 = STRH_POST
  { 486,	7,	1,	366,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4a3ULL, NULL, NULL, OperandInfo118,0,0 },  // Inst #486 = STRH_PRE
  { 487,	7,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo119,0,0 },  // Inst #487 = STRH_preidx
  { 488,	4,	0,	365,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #488 = STRT_POST
  { 489,	7,	1,	368,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #489 = STRT_POST_IMM
  { 490,	7,	1,	368,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #490 = STRT_POST_REG
  { 491,	7,	1,	369,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #491 = STR_POST_IMM
  { 492,	7,	1,	368,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #492 = STR_POST_REG
  { 493,	6,	1,	369,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo115,0,0 },  // Inst #493 = STR_PRE_IMM
  { 494,	7,	1,	368,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #494 = STR_PRE_REG
  { 495,	5,	0,	358,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #495 = STRi12
  { 496,	7,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo116,0,0 },  // Inst #496 = STRi_preidx
  { 497,	7,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo116,0,0 },  // Inst #497 = STRr_preidx
  { 498,	6,	0,	362,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, NULL, NULL, OperandInfo70,0,0 },  // Inst #498 = STRrs
  { 499,	3,	0,	76,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo20,0,0 },  // Inst #499 = SUBS_PC_LR
  { 500,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo15,0,0 },  // Inst #500 = SUBSri
  { 501,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo16,0,0 },  // Inst #501 = SUBSrr
  { 502,	6,	1,	3,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo17,0,0 },  // Inst #502 = SUBSrsi
  { 503,	7,	1,	5,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo18,0,0 },  // Inst #503 = SUBSrsr
  { 504,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #504 = SUBri
  { 505,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #505 = SUBrr
  { 506,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #506 = SUBrsi
  { 507,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #507 = SUBrsr
  { 508,	3,	0,	10,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, ImplicitList2, NULL, OperandInfo50,0,0 },  // Inst #508 = SVC
  { 509,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #509 = SWP
  { 510,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #510 = SWPB
  { 511,	6,	1,	304,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo121,0,0 },  // Inst #511 = SXTAB
  { 512,	6,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, NULL, NULL, OperandInfo121,0,0 },  // Inst #512 = SXTAB16
  { 513,	6,	1,	304,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo121,0,0 },  // Inst #513 = SXTAH
  { 514,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo122,0,0 },  // Inst #514 = SXTB
  { 515,	5,	1,	290,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, NULL, NULL, OperandInfo122,0,0 },  // Inst #515 = SXTB16
  { 516,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo122,0,0 },  // Inst #516 = SXTH
  { 517,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo30,0,0 },  // Inst #517 = TAILJMPd
  { 518,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo123,0,0 },  // Inst #518 = TAILJMPr
  { 519,	1,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, NULL, OperandInfo2,0,0 },  // Inst #519 = TCRETURNdi
  { 520,	1,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, NULL, OperandInfo123,0,0 },  // Inst #520 = TCRETURNri
  { 521,	4,	0,	79,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #521 = TEQri
  { 522,	4,	0,	80,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #522 = TEQrr
  { 523,	5,	0,	81,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #523 = TEQrsi
  { 524,	6,	0,	82,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #524 = TEQrsr
  { 525,	0,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, 0,0,0 },  // Inst #525 = TPsoft
  { 526,	0,	0,	0,	4,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, 0,0,0 },  // Inst #526 = TRAP
  { 527,	0,	0,	0,	4,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, 0,0,0 },  // Inst #527 = TRAPNaCl
  { 528,	4,	0,	79,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #528 = TSTri
  { 529,	4,	0,	80,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #529 = TSTrr
  { 530,	5,	0,	81,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #530 = TSTrsi
  { 531,	6,	0,	82,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #531 = TSTrsr
  { 532,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #532 = UADD16
  { 533,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #533 = UADD8
  { 534,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #534 = UASX
  { 535,	6,	1,	278,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #535 = UBFX
  { 536,	5,	1,	324,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #536 = UDIV
  { 537,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #537 = UHADD16
  { 538,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #538 = UHADD8
  { 539,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #539 = UHASX
  { 540,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #540 = UHSAX
  { 541,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #541 = UHSUB16
  { 542,	5,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #542 = UHSUB8
  { 543,	6,	2,	281,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #543 = UMAAL
  { 544,	9,	2,	281,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #544 = UMLAL
  { 545,	9,	2,	281,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo108,0,0 },  // Inst #545 = UMLALv5
  { 546,	7,	2,	321,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #546 = UMULL
  { 547,	7,	2,	282,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo109,0,0 },  // Inst #547 = UMULLv5
  { 548,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #548 = UQADD16
  { 549,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #549 = UQADD8
  { 550,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #550 = UQASX
  { 551,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #551 = UQSAX
  { 552,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #552 = UQSUB16
  { 553,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #553 = UQSUB8
  { 554,	5,	1,	307,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #554 = USAD8
  { 555,	6,	1,	308,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #555 = USADA8
  { 556,	6,	1,	300,	4,	0|(1<<MCID_Predicable), 0x680ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #556 = USAT
  { 557,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, NULL, NULL, OperandInfo111,0,0 },  // Inst #557 = USAT16
  { 558,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #558 = USAX
  { 559,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #559 = USUB16
  { 560,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #560 = USUB8
  { 561,	6,	1,	304,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo121,0,0 },  // Inst #561 = UXTAB
  { 562,	6,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, NULL, NULL, OperandInfo121,0,0 },  // Inst #562 = UXTAB16
  { 563,	6,	1,	304,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo121,0,0 },  // Inst #563 = UXTAH
  { 564,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo122,0,0 },  // Inst #564 = UXTB
  { 565,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo122,0,0 },  // Inst #565 = UXTB16
  { 566,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo122,0,0 },  // Inst #566 = UXTH
  { 567,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #567 = VABALsv2i64
  { 568,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #568 = VABALsv4i32
  { 569,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #569 = VABALsv8i16
  { 570,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #570 = VABALuv2i64
  { 571,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #571 = VABALuv4i32
  { 572,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #572 = VABALuv8i16
  { 573,	6,	1,	401,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #573 = VABAsv16i8
  { 574,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #574 = VABAsv2i32
  { 575,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #575 = VABAsv4i16
  { 576,	6,	1,	401,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #576 = VABAsv4i32
  { 577,	6,	1,	401,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #577 = VABAsv8i16
  { 578,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #578 = VABAsv8i8
  { 579,	6,	1,	401,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #579 = VABAuv16i8
  { 580,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #580 = VABAuv2i32
  { 581,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #581 = VABAuv4i16
  { 582,	6,	1,	401,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #582 = VABAuv4i32
  { 583,	6,	1,	401,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #583 = VABAuv8i16
  { 584,	6,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #584 = VABAuv8i8
  { 585,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #585 = VABDLsv2i64
  { 586,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #586 = VABDLsv4i32
  { 587,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #587 = VABDLsv8i16
  { 588,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #588 = VABDLuv2i64
  { 589,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #589 = VABDLuv4i32
  { 590,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #590 = VABDLuv8i16
  { 591,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #591 = VABDfd
  { 592,	5,	1,	443,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #592 = VABDfq
  { 593,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #593 = VABDsv16i8
  { 594,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #594 = VABDsv2i32
  { 595,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #595 = VABDsv4i16
  { 596,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #596 = VABDsv4i32
  { 597,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #597 = VABDsv8i16
  { 598,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #598 = VABDsv8i8
  { 599,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #599 = VABDuv16i8
  { 600,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #600 = VABDuv2i32
  { 601,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #601 = VABDuv4i16
  { 602,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #602 = VABDuv4i32
  { 603,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #603 = VABDuv8i16
  { 604,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #604 = VABDuv8i8
  { 605,	4,	1,	437,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #605 = VABSD
  { 606,	4,	1,	438,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #606 = VABSS
  { 607,	4,	1,	402,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #607 = VABSfd
  { 608,	4,	1,	403,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #608 = VABSfq
  { 609,	4,	1,	404,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #609 = VABSv16i8
  { 610,	4,	1,	405,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #610 = VABSv2i32
  { 611,	4,	1,	405,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #611 = VABSv4i16
  { 612,	4,	1,	404,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #612 = VABSv4i32
  { 613,	4,	1,	404,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #613 = VABSv8i16
  { 614,	4,	1,	405,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #614 = VABSv8i8
  { 615,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #615 = VACGEd
  { 616,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #616 = VACGEq
  { 617,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #617 = VACGTd
  { 618,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #618 = VACGTq
  { 619,	5,	1,	448,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #619 = VADDD
  { 620,	5,	1,	421,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #620 = VADDHNv2i32
  { 621,	5,	1,	421,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #621 = VADDHNv4i16
  { 622,	5,	1,	421,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #622 = VADDHNv8i8
  { 623,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #623 = VADDLsv2i64
  { 624,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #624 = VADDLsv4i32
  { 625,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #625 = VADDLsv8i16
  { 626,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #626 = VADDLuv2i64
  { 627,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #627 = VADDLuv4i32
  { 628,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #628 = VADDLuv8i16
  { 629,	5,	1,	445,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #629 = VADDS
  { 630,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #630 = VADDWsv2i64
  { 631,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #631 = VADDWsv4i32
  { 632,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #632 = VADDWsv8i16
  { 633,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #633 = VADDWuv2i64
  { 634,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #634 = VADDWuv4i32
  { 635,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #635 = VADDWuv8i16
  { 636,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #636 = VADDfd
  { 637,	5,	1,	443,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #637 = VADDfq
  { 638,	5,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #638 = VADDv16i8
  { 639,	5,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #639 = VADDv1i64
  { 640,	5,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #640 = VADDv2i32
  { 641,	5,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #641 = VADDv2i64
  { 642,	5,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #642 = VADDv4i16
  { 643,	5,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #643 = VADDv4i32
  { 644,	5,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #644 = VADDv8i16
  { 645,	5,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #645 = VADDv8i8
  { 646,	5,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #646 = VANDd
  { 647,	5,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #647 = VANDq
  { 648,	5,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #648 = VBICd
  { 649,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #649 = VBICiv2i32
  { 650,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #650 = VBICiv4i16
  { 651,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo138,0,0 },  // Inst #651 = VBICiv4i32
  { 652,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo138,0,0 },  // Inst #652 = VBICiv8i16
  { 653,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #653 = VBICq
  { 654,	6,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #654 = VBIFd
  { 655,	6,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #655 = VBIFq
  { 656,	6,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #656 = VBITd
  { 657,	6,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #657 = VBITq
  { 658,	6,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #658 = VBSLd
  { 659,	6,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #659 = VBSLq
  { 660,	5,	1,	406,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #660 = VCEQfd
  { 661,	5,	1,	407,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #661 = VCEQfq
  { 662,	5,	1,	408,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #662 = VCEQv16i8
  { 663,	5,	1,	409,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #663 = VCEQv2i32
  { 664,	5,	1,	409,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #664 = VCEQv4i16
  { 665,	5,	1,	408,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #665 = VCEQv4i32
  { 666,	5,	1,	408,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #666 = VCEQv8i16
  { 667,	5,	1,	409,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #667 = VCEQv8i8
  { 668,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #668 = VCEQzv16i8
  { 669,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #669 = VCEQzv2f32
  { 670,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #670 = VCEQzv2i32
  { 671,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #671 = VCEQzv4f32
  { 672,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #672 = VCEQzv4i16
  { 673,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #673 = VCEQzv4i32
  { 674,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #674 = VCEQzv8i16
  { 675,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #675 = VCEQzv8i8
  { 676,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #676 = VCGEfd
  { 677,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #677 = VCGEfq
  { 678,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #678 = VCGEsv16i8
  { 679,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #679 = VCGEsv2i32
  { 680,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #680 = VCGEsv4i16
  { 681,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #681 = VCGEsv4i32
  { 682,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #682 = VCGEsv8i16
  { 683,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #683 = VCGEsv8i8
  { 684,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #684 = VCGEuv16i8
  { 685,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #685 = VCGEuv2i32
  { 686,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #686 = VCGEuv4i16
  { 687,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #687 = VCGEuv4i32
  { 688,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #688 = VCGEuv8i16
  { 689,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #689 = VCGEuv8i8
  { 690,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #690 = VCGEzv16i8
  { 691,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #691 = VCGEzv2f32
  { 692,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #692 = VCGEzv2i32
  { 693,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #693 = VCGEzv4f32
  { 694,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #694 = VCGEzv4i16
  { 695,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #695 = VCGEzv4i32
  { 696,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #696 = VCGEzv8i16
  { 697,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #697 = VCGEzv8i8
  { 698,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #698 = VCGTfd
  { 699,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #699 = VCGTfq
  { 700,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #700 = VCGTsv16i8
  { 701,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #701 = VCGTsv2i32
  { 702,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #702 = VCGTsv4i16
  { 703,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #703 = VCGTsv4i32
  { 704,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #704 = VCGTsv8i16
  { 705,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #705 = VCGTsv8i8
  { 706,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #706 = VCGTuv16i8
  { 707,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #707 = VCGTuv2i32
  { 708,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #708 = VCGTuv4i16
  { 709,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #709 = VCGTuv4i32
  { 710,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #710 = VCGTuv8i16
  { 711,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #711 = VCGTuv8i8
  { 712,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #712 = VCGTzv16i8
  { 713,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #713 = VCGTzv2f32
  { 714,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #714 = VCGTzv2i32
  { 715,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #715 = VCGTzv4f32
  { 716,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #716 = VCGTzv4i16
  { 717,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #717 = VCGTzv4i32
  { 718,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #718 = VCGTzv8i16
  { 719,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #719 = VCGTzv8i8
  { 720,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #720 = VCLEzv16i8
  { 721,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #721 = VCLEzv2f32
  { 722,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #722 = VCLEzv2i32
  { 723,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #723 = VCLEzv4f32
  { 724,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #724 = VCLEzv4i16
  { 725,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #725 = VCLEzv4i32
  { 726,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #726 = VCLEzv8i16
  { 727,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #727 = VCLEzv8i8
  { 728,	4,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #728 = VCLSv16i8
  { 729,	4,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #729 = VCLSv2i32
  { 730,	4,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #730 = VCLSv4i16
  { 731,	4,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #731 = VCLSv4i32
  { 732,	4,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #732 = VCLSv8i16
  { 733,	4,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #733 = VCLSv8i8
  { 734,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #734 = VCLTzv16i8
  { 735,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #735 = VCLTzv2f32
  { 736,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #736 = VCLTzv2i32
  { 737,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #737 = VCLTzv4f32
  { 738,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #738 = VCLTzv4i16
  { 739,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #739 = VCLTzv4i32
  { 740,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #740 = VCLTzv8i16
  { 741,	4,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #741 = VCLTzv8i8
  { 742,	4,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #742 = VCLZv16i8
  { 743,	4,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #743 = VCLZv2i32
  { 744,	4,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #744 = VCLZv4i16
  { 745,	4,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #745 = VCLZv4i32
  { 746,	4,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #746 = VCLZv8i16
  { 747,	4,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #747 = VCLZv8i8
  { 748,	4,	0,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, ImplicitList4, OperandInfo131,0,0 },  // Inst #748 = VCMPD
  { 749,	4,	0,	439,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, ImplicitList4, OperandInfo131,0,0 },  // Inst #749 = VCMPED
  { 750,	4,	0,	440,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, ImplicitList4, OperandInfo132,0,0 },  // Inst #750 = VCMPES
  { 751,	3,	0,	439,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, ImplicitList4, OperandInfo139,0,0 },  // Inst #751 = VCMPEZD
  { 752,	3,	0,	440,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, ImplicitList4, OperandInfo140,0,0 },  // Inst #752 = VCMPEZS
  { 753,	4,	0,	440,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, NULL, ImplicitList4, OperandInfo132,0,0 },  // Inst #753 = VCMPS
  { 754,	3,	0,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, ImplicitList4, OperandInfo139,0,0 },  // Inst #754 = VCMPZD
  { 755,	3,	0,	440,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, NULL, ImplicitList4, OperandInfo140,0,0 },  // Inst #755 = VCMPZS
  { 756,	4,	1,	384,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #756 = VCNTd
  { 757,	4,	1,	385,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #757 = VCNTq
  { 758,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #758 = VCVTANSD
  { 759,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #759 = VCVTANSQ
  { 760,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #760 = VCVTANUD
  { 761,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #761 = VCVTANUQ
  { 762,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #762 = VCVTASD
  { 763,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #763 = VCVTASS
  { 764,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #764 = VCVTAUD
  { 765,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #765 = VCVTAUS
  { 766,	4,	1,	474,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #766 = VCVTBDH
  { 767,	4,	1,	474,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #767 = VCVTBHD
  { 768,	4,	1,	475,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #768 = VCVTBHS
  { 769,	4,	1,	476,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #769 = VCVTBSH
  { 770,	4,	1,	477,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #770 = VCVTDS
  { 771,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #771 = VCVTMNSD
  { 772,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #772 = VCVTMNSQ
  { 773,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #773 = VCVTMNUD
  { 774,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #774 = VCVTMNUQ
  { 775,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #775 = VCVTMSD
  { 776,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #776 = VCVTMSS
  { 777,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #777 = VCVTMUD
  { 778,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #778 = VCVTMUS
  { 779,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #779 = VCVTNNSD
  { 780,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #780 = VCVTNNSQ
  { 781,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #781 = VCVTNNUD
  { 782,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #782 = VCVTNNUQ
  { 783,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #783 = VCVTNSD
  { 784,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #784 = VCVTNSS
  { 785,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #785 = VCVTNUD
  { 786,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #786 = VCVTNUS
  { 787,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #787 = VCVTPNSD
  { 788,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #788 = VCVTPNSQ
  { 789,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #789 = VCVTPNUD
  { 790,	2,	1,	474,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #790 = VCVTPNUQ
  { 791,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #791 = VCVTPSD
  { 792,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #792 = VCVTPSS
  { 793,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #793 = VCVTPUD
  { 794,	2,	1,	474,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #794 = VCVTPUS
  { 795,	4,	1,	478,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #795 = VCVTSD
  { 796,	4,	1,	474,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #796 = VCVTTDH
  { 797,	4,	1,	474,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #797 = VCVTTHD
  { 798,	4,	1,	475,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #798 = VCVTTHS
  { 799,	4,	1,	476,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #799 = VCVTTSH
  { 800,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #800 = VCVTf2h
  { 801,	4,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #801 = VCVTf2sd
  { 802,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #802 = VCVTf2sq
  { 803,	4,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #803 = VCVTf2ud
  { 804,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #804 = VCVTf2uq
  { 805,	5,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #805 = VCVTf2xsd
  { 806,	5,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #806 = VCVTf2xsq
  { 807,	5,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #807 = VCVTf2xud
  { 808,	5,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #808 = VCVTf2xuq
  { 809,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #809 = VCVTh2f
  { 810,	4,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #810 = VCVTs2fd
  { 811,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #811 = VCVTs2fq
  { 812,	4,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #812 = VCVTu2fd
  { 813,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #813 = VCVTu2fq
  { 814,	5,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #814 = VCVTxs2fd
  { 815,	5,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #815 = VCVTxs2fq
  { 816,	5,	1,	480,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #816 = VCVTxu2fd
  { 817,	5,	1,	479,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #817 = VCVTxu2fq
  { 818,	5,	1,	588,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #818 = VDIVD
  { 819,	5,	1,	586,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #819 = VDIVS
  { 820,	4,	1,	496,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo150,0,0 },  // Inst #820 = VDUP16d
  { 821,	4,	1,	496,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #821 = VDUP16q
  { 822,	4,	1,	496,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo150,0,0 },  // Inst #822 = VDUP32d
  { 823,	4,	1,	496,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #823 = VDUP32q
  { 824,	4,	1,	496,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo150,0,0 },  // Inst #824 = VDUP8d
  { 825,	4,	1,	496,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #825 = VDUP8q
  { 826,	5,	1,	494,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #826 = VDUPLN16d
  { 827,	5,	1,	495,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #827 = VDUPLN16q
  { 828,	5,	1,	494,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #828 = VDUPLN32d
  { 829,	5,	1,	495,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #829 = VDUPLN32q
  { 830,	5,	1,	494,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #830 = VDUPLN8d
  { 831,	5,	1,	495,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #831 = VDUPLN8q
  { 832,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #832 = VDUPfdf
  { 833,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10000ULL, NULL, NULL, OperandInfo153,0,0 },  // Inst #833 = VDUPfqf
  { 834,	5,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #834 = VEORd
  { 835,	5,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #835 = VEORq
  { 836,	6,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo154,0,0 },  // Inst #836 = VEXTd16
  { 837,	6,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo154,0,0 },  // Inst #837 = VEXTd32
  { 838,	6,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo154,0,0 },  // Inst #838 = VEXTd8
  { 839,	6,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #839 = VEXTq16
  { 840,	6,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #840 = VEXTq32
  { 841,	6,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #841 = VEXTq64
  { 842,	6,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #842 = VEXTq8
  { 843,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #843 = VFMAD
  { 844,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #844 = VFMAS
  { 845,	6,	1,	472,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #845 = VFMAfd
  { 846,	6,	1,	473,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #846 = VFMAfq
  { 847,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #847 = VFMSD
  { 848,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #848 = VFMSS
  { 849,	6,	1,	472,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #849 = VFMSfd
  { 850,	6,	1,	473,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #850 = VFMSfq
  { 851,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #851 = VFNMAD
  { 852,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #852 = VFNMAS
  { 853,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #853 = VFNMSD
  { 854,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #854 = VFNMSS
  { 855,	5,	1,	503,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #855 = VGETLNi32
  { 856,	5,	1,	504,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #856 = VGETLNs16
  { 857,	5,	1,	504,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #857 = VGETLNs8
  { 858,	5,	1,	503,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #858 = VGETLNu16
  { 859,	5,	1,	503,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #859 = VGETLNu8
  { 860,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #860 = VHADDsv16i8
  { 861,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #861 = VHADDsv2i32
  { 862,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #862 = VHADDsv4i16
  { 863,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #863 = VHADDsv4i32
  { 864,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #864 = VHADDsv8i16
  { 865,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #865 = VHADDsv8i8
  { 866,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #866 = VHADDuv16i8
  { 867,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #867 = VHADDuv2i32
  { 868,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #868 = VHADDuv4i16
  { 869,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #869 = VHADDuv4i32
  { 870,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #870 = VHADDuv8i16
  { 871,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #871 = VHADDuv8i8
  { 872,	5,	1,	388,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #872 = VHSUBsv16i8
  { 873,	5,	1,	389,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #873 = VHSUBsv2i32
  { 874,	5,	1,	389,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #874 = VHSUBsv4i16
  { 875,	5,	1,	388,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #875 = VHSUBsv4i32
  { 876,	5,	1,	388,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #876 = VHSUBsv8i16
  { 877,	5,	1,	389,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #877 = VHSUBsv8i8
  { 878,	5,	1,	388,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #878 = VHSUBuv16i8
  { 879,	5,	1,	389,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #879 = VHSUBuv2i32
  { 880,	5,	1,	389,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #880 = VHSUBuv4i16
  { 881,	5,	1,	388,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #881 = VHSUBuv4i32
  { 882,	5,	1,	388,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #882 = VHSUBuv8i16
  { 883,	5,	1,	389,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #883 = VHSUBuv8i8
  { 884,	5,	1,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #884 = VLD1DUPd16
  { 885,	6,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #885 = VLD1DUPd16wb_fixed
  { 886,	7,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #886 = VLD1DUPd16wb_register
  { 887,	5,	1,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #887 = VLD1DUPd32
  { 888,	6,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #888 = VLD1DUPd32wb_fixed
  { 889,	7,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #889 = VLD1DUPd32wb_register
  { 890,	5,	1,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #890 = VLD1DUPd8
  { 891,	6,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #891 = VLD1DUPd8wb_fixed
  { 892,	7,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #892 = VLD1DUPd8wb_register
  { 893,	5,	1,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #893 = VLD1DUPq16
  { 894,	6,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #894 = VLD1DUPq16wb_fixed
  { 895,	7,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #895 = VLD1DUPq16wb_register
  { 896,	5,	1,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #896 = VLD1DUPq32
  { 897,	6,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #897 = VLD1DUPq32wb_fixed
  { 898,	7,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #898 = VLD1DUPq32wb_register
  { 899,	5,	1,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #899 = VLD1DUPq8
  { 900,	6,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #900 = VLD1DUPq8wb_fixed
  { 901,	7,	2,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #901 = VLD1DUPq8wb_register
  { 902,	7,	1,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo164,0,0 },  // Inst #902 = VLD1LNd16
  { 903,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #903 = VLD1LNd16_UPD
  { 904,	7,	1,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo164,0,0 },  // Inst #904 = VLD1LNd32
  { 905,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #905 = VLD1LNd32_UPD
  { 906,	7,	1,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo164,0,0 },  // Inst #906 = VLD1LNd8
  { 907,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #907 = VLD1LNd8_UPD
  { 908,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #908 = VLD1LNdAsm_16
  { 909,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #909 = VLD1LNdAsm_32
  { 910,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #910 = VLD1LNdAsm_8
  { 911,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #911 = VLD1LNdWB_fixed_Asm_16
  { 912,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #912 = VLD1LNdWB_fixed_Asm_32
  { 913,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #913 = VLD1LNdWB_fixed_Asm_8
  { 914,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #914 = VLD1LNdWB_register_Asm_16
  { 915,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #915 = VLD1LNdWB_register_Asm_32
  { 916,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #916 = VLD1LNdWB_register_Asm_8
  { 917,	7,	1,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #917 = VLD1LNq16Pseudo
  { 918,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #918 = VLD1LNq16Pseudo_UPD
  { 919,	7,	1,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #919 = VLD1LNq32Pseudo
  { 920,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #920 = VLD1LNq32Pseudo_UPD
  { 921,	7,	1,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #921 = VLD1LNq8Pseudo
  { 922,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #922 = VLD1LNq8Pseudo_UPD
  { 923,	5,	1,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #923 = VLD1d16
  { 924,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #924 = VLD1d16Q
  { 925,	6,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #925 = VLD1d16Qwb_fixed
  { 926,	7,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #926 = VLD1d16Qwb_register
  { 927,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #927 = VLD1d16T
  { 928,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #928 = VLD1d16Twb_fixed
  { 929,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #929 = VLD1d16Twb_register
  { 930,	6,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #930 = VLD1d16wb_fixed
  { 931,	7,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #931 = VLD1d16wb_register
  { 932,	5,	1,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #932 = VLD1d32
  { 933,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #933 = VLD1d32Q
  { 934,	6,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #934 = VLD1d32Qwb_fixed
  { 935,	7,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #935 = VLD1d32Qwb_register
  { 936,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #936 = VLD1d32T
  { 937,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #937 = VLD1d32Twb_fixed
  { 938,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #938 = VLD1d32Twb_register
  { 939,	6,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #939 = VLD1d32wb_fixed
  { 940,	7,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #940 = VLD1d32wb_register
  { 941,	5,	1,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #941 = VLD1d64
  { 942,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #942 = VLD1d64Q
  { 943,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #943 = VLD1d64QPseudo
  { 944,	6,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #944 = VLD1d64Qwb_fixed
  { 945,	7,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #945 = VLD1d64Qwb_register
  { 946,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #946 = VLD1d64T
  { 947,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #947 = VLD1d64TPseudo
  { 948,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #948 = VLD1d64Twb_fixed
  { 949,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #949 = VLD1d64Twb_register
  { 950,	6,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #950 = VLD1d64wb_fixed
  { 951,	7,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #951 = VLD1d64wb_register
  { 952,	5,	1,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #952 = VLD1d8
  { 953,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #953 = VLD1d8Q
  { 954,	6,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #954 = VLD1d8Qwb_fixed
  { 955,	7,	2,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #955 = VLD1d8Qwb_register
  { 956,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #956 = VLD1d8T
  { 957,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #957 = VLD1d8Twb_fixed
  { 958,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #958 = VLD1d8Twb_register
  { 959,	6,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #959 = VLD1d8wb_fixed
  { 960,	7,	2,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #960 = VLD1d8wb_register
  { 961,	5,	1,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #961 = VLD1q16
  { 962,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #962 = VLD1q16wb_fixed
  { 963,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #963 = VLD1q16wb_register
  { 964,	5,	1,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #964 = VLD1q32
  { 965,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #965 = VLD1q32wb_fixed
  { 966,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #966 = VLD1q32wb_register
  { 967,	5,	1,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #967 = VLD1q64
  { 968,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #968 = VLD1q64wb_fixed
  { 969,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #969 = VLD1q64wb_register
  { 970,	5,	1,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #970 = VLD1q8
  { 971,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #971 = VLD1q8wb_fixed
  { 972,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #972 = VLD1q8wb_register
  { 973,	5,	1,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #973 = VLD2DUPd16
  { 974,	6,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #974 = VLD2DUPd16wb_fixed
  { 975,	7,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #975 = VLD2DUPd16wb_register
  { 976,	5,	1,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #976 = VLD2DUPd16x2
  { 977,	6,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #977 = VLD2DUPd16x2wb_fixed
  { 978,	7,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #978 = VLD2DUPd16x2wb_register
  { 979,	5,	1,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #979 = VLD2DUPd32
  { 980,	6,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #980 = VLD2DUPd32wb_fixed
  { 981,	7,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #981 = VLD2DUPd32wb_register
  { 982,	5,	1,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #982 = VLD2DUPd32x2
  { 983,	6,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #983 = VLD2DUPd32x2wb_fixed
  { 984,	7,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #984 = VLD2DUPd32x2wb_register
  { 985,	5,	1,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #985 = VLD2DUPd8
  { 986,	6,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #986 = VLD2DUPd8wb_fixed
  { 987,	7,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #987 = VLD2DUPd8wb_register
  { 988,	5,	1,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #988 = VLD2DUPd8x2
  { 989,	6,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #989 = VLD2DUPd8x2wb_fixed
  { 990,	7,	2,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #990 = VLD2DUPd8x2wb_register
  { 991,	9,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #991 = VLD2LNd16
  { 992,	7,	1,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #992 = VLD2LNd16Pseudo
  { 993,	9,	2,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #993 = VLD2LNd16Pseudo_UPD
  { 994,	11,	3,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #994 = VLD2LNd16_UPD
  { 995,	9,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #995 = VLD2LNd32
  { 996,	7,	1,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #996 = VLD2LNd32Pseudo
  { 997,	9,	2,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #997 = VLD2LNd32Pseudo_UPD
  { 998,	11,	3,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #998 = VLD2LNd32_UPD
  { 999,	9,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #999 = VLD2LNd8
  { 1000,	7,	1,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #1000 = VLD2LNd8Pseudo
  { 1001,	9,	2,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1001 = VLD2LNd8Pseudo_UPD
  { 1002,	11,	3,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1002 = VLD2LNd8_UPD
  { 1003,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1003 = VLD2LNdAsm_16
  { 1004,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1004 = VLD2LNdAsm_32
  { 1005,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1005 = VLD2LNdAsm_8
  { 1006,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1006 = VLD2LNdWB_fixed_Asm_16
  { 1007,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1007 = VLD2LNdWB_fixed_Asm_32
  { 1008,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1008 = VLD2LNdWB_fixed_Asm_8
  { 1009,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1009 = VLD2LNdWB_register_Asm_16
  { 1010,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1010 = VLD2LNdWB_register_Asm_32
  { 1011,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1011 = VLD2LNdWB_register_Asm_8
  { 1012,	9,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #1012 = VLD2LNq16
  { 1013,	7,	1,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1013 = VLD2LNq16Pseudo
  { 1014,	9,	2,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1014 = VLD2LNq16Pseudo_UPD
  { 1015,	11,	3,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1015 = VLD2LNq16_UPD
  { 1016,	9,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #1016 = VLD2LNq32
  { 1017,	7,	1,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1017 = VLD2LNq32Pseudo
  { 1018,	9,	2,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1018 = VLD2LNq32Pseudo_UPD
  { 1019,	11,	3,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1019 = VLD2LNq32_UPD
  { 1020,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1020 = VLD2LNqAsm_16
  { 1021,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1021 = VLD2LNqAsm_32
  { 1022,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1022 = VLD2LNqWB_fixed_Asm_16
  { 1023,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1023 = VLD2LNqWB_fixed_Asm_32
  { 1024,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1024 = VLD2LNqWB_register_Asm_16
  { 1025,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1025 = VLD2LNqWB_register_Asm_32
  { 1026,	5,	1,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1026 = VLD2b16
  { 1027,	6,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1027 = VLD2b16wb_fixed
  { 1028,	7,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #1028 = VLD2b16wb_register
  { 1029,	5,	1,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1029 = VLD2b32
  { 1030,	6,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1030 = VLD2b32wb_fixed
  { 1031,	7,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #1031 = VLD2b32wb_register
  { 1032,	5,	1,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1032 = VLD2b8
  { 1033,	6,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1033 = VLD2b8wb_fixed
  { 1034,	7,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #1034 = VLD2b8wb_register
  { 1035,	5,	1,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1035 = VLD2d16
  { 1036,	6,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1036 = VLD2d16wb_fixed
  { 1037,	7,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #1037 = VLD2d16wb_register
  { 1038,	5,	1,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1038 = VLD2d32
  { 1039,	6,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1039 = VLD2d32wb_fixed
  { 1040,	7,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #1040 = VLD2d32wb_register
  { 1041,	5,	1,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1041 = VLD2d8
  { 1042,	6,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1042 = VLD2d8wb_fixed
  { 1043,	7,	2,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #1043 = VLD2d8wb_register
  { 1044,	5,	1,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1044 = VLD2q16
  { 1045,	5,	1,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1045 = VLD2q16Pseudo
  { 1046,	6,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo175,0,0 },  // Inst #1046 = VLD2q16PseudoWB_fixed
  { 1047,	7,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1047 = VLD2q16PseudoWB_register
  { 1048,	6,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #1048 = VLD2q16wb_fixed
  { 1049,	7,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1049 = VLD2q16wb_register
  { 1050,	5,	1,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1050 = VLD2q32
  { 1051,	5,	1,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1051 = VLD2q32Pseudo
  { 1052,	6,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo175,0,0 },  // Inst #1052 = VLD2q32PseudoWB_fixed
  { 1053,	7,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1053 = VLD2q32PseudoWB_register
  { 1054,	6,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #1054 = VLD2q32wb_fixed
  { 1055,	7,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1055 = VLD2q32wb_register
  { 1056,	5,	1,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1056 = VLD2q8
  { 1057,	5,	1,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1057 = VLD2q8Pseudo
  { 1058,	6,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo175,0,0 },  // Inst #1058 = VLD2q8PseudoWB_fixed
  { 1059,	7,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1059 = VLD2q8PseudoWB_register
  { 1060,	6,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #1060 = VLD2q8wb_fixed
  { 1061,	7,	2,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1061 = VLD2q8wb_register
  { 1062,	7,	3,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1062 = VLD3DUPd16
  { 1063,	5,	1,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1063 = VLD3DUPd16Pseudo
  { 1064,	7,	2,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1064 = VLD3DUPd16Pseudo_UPD
  { 1065,	9,	4,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1065 = VLD3DUPd16_UPD
  { 1066,	7,	3,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1066 = VLD3DUPd32
  { 1067,	5,	1,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1067 = VLD3DUPd32Pseudo
  { 1068,	7,	2,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1068 = VLD3DUPd32Pseudo_UPD
  { 1069,	9,	4,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1069 = VLD3DUPd32_UPD
  { 1070,	7,	3,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1070 = VLD3DUPd8
  { 1071,	5,	1,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1071 = VLD3DUPd8Pseudo
  { 1072,	7,	2,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1072 = VLD3DUPd8Pseudo_UPD
  { 1073,	9,	4,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1073 = VLD3DUPd8_UPD
  { 1074,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1074 = VLD3DUPdAsm_16
  { 1075,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1075 = VLD3DUPdAsm_32
  { 1076,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1076 = VLD3DUPdAsm_8
  { 1077,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1077 = VLD3DUPdWB_fixed_Asm_16
  { 1078,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1078 = VLD3DUPdWB_fixed_Asm_32
  { 1079,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1079 = VLD3DUPdWB_fixed_Asm_8
  { 1080,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1080 = VLD3DUPdWB_register_Asm_16
  { 1081,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1081 = VLD3DUPdWB_register_Asm_32
  { 1082,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1082 = VLD3DUPdWB_register_Asm_8
  { 1083,	7,	3,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1083 = VLD3DUPq16
  { 1084,	9,	4,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1084 = VLD3DUPq16_UPD
  { 1085,	7,	3,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1085 = VLD3DUPq32
  { 1086,	9,	4,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1086 = VLD3DUPq32_UPD
  { 1087,	7,	3,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1087 = VLD3DUPq8
  { 1088,	9,	4,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1088 = VLD3DUPq8_UPD
  { 1089,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1089 = VLD3DUPqAsm_16
  { 1090,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1090 = VLD3DUPqAsm_32
  { 1091,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1091 = VLD3DUPqAsm_8
  { 1092,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1092 = VLD3DUPqWB_fixed_Asm_16
  { 1093,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1093 = VLD3DUPqWB_fixed_Asm_32
  { 1094,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1094 = VLD3DUPqWB_fixed_Asm_8
  { 1095,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1095 = VLD3DUPqWB_register_Asm_16
  { 1096,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1096 = VLD3DUPqWB_register_Asm_32
  { 1097,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1097 = VLD3DUPqWB_register_Asm_8
  { 1098,	11,	3,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1098 = VLD3LNd16
  { 1099,	7,	1,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1099 = VLD3LNd16Pseudo
  { 1100,	9,	2,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1100 = VLD3LNd16Pseudo_UPD
  { 1101,	13,	4,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1101 = VLD3LNd16_UPD
  { 1102,	11,	3,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1102 = VLD3LNd32
  { 1103,	7,	1,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1103 = VLD3LNd32Pseudo
  { 1104,	9,	2,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1104 = VLD3LNd32Pseudo_UPD
  { 1105,	13,	4,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1105 = VLD3LNd32_UPD
  { 1106,	11,	3,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1106 = VLD3LNd8
  { 1107,	7,	1,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1107 = VLD3LNd8Pseudo
  { 1108,	9,	2,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1108 = VLD3LNd8Pseudo_UPD
  { 1109,	13,	4,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1109 = VLD3LNd8_UPD
  { 1110,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1110 = VLD3LNdAsm_16
  { 1111,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1111 = VLD3LNdAsm_32
  { 1112,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1112 = VLD3LNdAsm_8
  { 1113,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1113 = VLD3LNdWB_fixed_Asm_16
  { 1114,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1114 = VLD3LNdWB_fixed_Asm_32
  { 1115,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1115 = VLD3LNdWB_fixed_Asm_8
  { 1116,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1116 = VLD3LNdWB_register_Asm_16
  { 1117,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1117 = VLD3LNdWB_register_Asm_32
  { 1118,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1118 = VLD3LNdWB_register_Asm_8
  { 1119,	11,	3,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1119 = VLD3LNq16
  { 1120,	7,	1,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1120 = VLD3LNq16Pseudo
  { 1121,	9,	2,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1121 = VLD3LNq16Pseudo_UPD
  { 1122,	13,	4,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1122 = VLD3LNq16_UPD
  { 1123,	11,	3,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1123 = VLD3LNq32
  { 1124,	7,	1,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1124 = VLD3LNq32Pseudo
  { 1125,	9,	2,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1125 = VLD3LNq32Pseudo_UPD
  { 1126,	13,	4,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1126 = VLD3LNq32_UPD
  { 1127,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1127 = VLD3LNqAsm_16
  { 1128,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1128 = VLD3LNqAsm_32
  { 1129,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1129 = VLD3LNqWB_fixed_Asm_16
  { 1130,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1130 = VLD3LNqWB_fixed_Asm_32
  { 1131,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1131 = VLD3LNqWB_register_Asm_16
  { 1132,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1132 = VLD3LNqWB_register_Asm_32
  { 1133,	7,	3,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1133 = VLD3d16
  { 1134,	5,	1,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1134 = VLD3d16Pseudo
  { 1135,	7,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1135 = VLD3d16Pseudo_UPD
  { 1136,	9,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1136 = VLD3d16_UPD
  { 1137,	7,	3,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1137 = VLD3d32
  { 1138,	5,	1,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1138 = VLD3d32Pseudo
  { 1139,	7,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1139 = VLD3d32Pseudo_UPD
  { 1140,	9,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1140 = VLD3d32_UPD
  { 1141,	7,	3,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1141 = VLD3d8
  { 1142,	5,	1,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1142 = VLD3d8Pseudo
  { 1143,	7,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1143 = VLD3d8Pseudo_UPD
  { 1144,	9,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1144 = VLD3d8_UPD
  { 1145,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1145 = VLD3dAsm_16
  { 1146,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1146 = VLD3dAsm_32
  { 1147,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1147 = VLD3dAsm_8
  { 1148,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1148 = VLD3dWB_fixed_Asm_16
  { 1149,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1149 = VLD3dWB_fixed_Asm_32
  { 1150,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1150 = VLD3dWB_fixed_Asm_8
  { 1151,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1151 = VLD3dWB_register_Asm_16
  { 1152,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1152 = VLD3dWB_register_Asm_32
  { 1153,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1153 = VLD3dWB_register_Asm_8
  { 1154,	7,	3,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1154 = VLD3q16
  { 1155,	8,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1155 = VLD3q16Pseudo_UPD
  { 1156,	9,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1156 = VLD3q16_UPD
  { 1157,	6,	1,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1157 = VLD3q16oddPseudo
  { 1158,	8,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1158 = VLD3q16oddPseudo_UPD
  { 1159,	7,	3,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1159 = VLD3q32
  { 1160,	8,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1160 = VLD3q32Pseudo_UPD
  { 1161,	9,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1161 = VLD3q32_UPD
  { 1162,	6,	1,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1162 = VLD3q32oddPseudo
  { 1163,	8,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1163 = VLD3q32oddPseudo_UPD
  { 1164,	7,	3,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1164 = VLD3q8
  { 1165,	8,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1165 = VLD3q8Pseudo_UPD
  { 1166,	9,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1166 = VLD3q8_UPD
  { 1167,	6,	1,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1167 = VLD3q8oddPseudo
  { 1168,	8,	2,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1168 = VLD3q8oddPseudo_UPD
  { 1169,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1169 = VLD3qAsm_16
  { 1170,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1170 = VLD3qAsm_32
  { 1171,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1171 = VLD3qAsm_8
  { 1172,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1172 = VLD3qWB_fixed_Asm_16
  { 1173,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1173 = VLD3qWB_fixed_Asm_32
  { 1174,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1174 = VLD3qWB_fixed_Asm_8
  { 1175,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1175 = VLD3qWB_register_Asm_16
  { 1176,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1176 = VLD3qWB_register_Asm_32
  { 1177,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1177 = VLD3qWB_register_Asm_8
  { 1178,	8,	4,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1178 = VLD4DUPd16
  { 1179,	5,	1,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1179 = VLD4DUPd16Pseudo
  { 1180,	7,	2,	557,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1180 = VLD4DUPd16Pseudo_UPD
  { 1181,	10,	5,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1181 = VLD4DUPd16_UPD
  { 1182,	8,	4,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1182 = VLD4DUPd32
  { 1183,	5,	1,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1183 = VLD4DUPd32Pseudo
  { 1184,	7,	2,	557,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1184 = VLD4DUPd32Pseudo_UPD
  { 1185,	10,	5,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1185 = VLD4DUPd32_UPD
  { 1186,	8,	4,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1186 = VLD4DUPd8
  { 1187,	5,	1,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1187 = VLD4DUPd8Pseudo
  { 1188,	7,	2,	557,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1188 = VLD4DUPd8Pseudo_UPD
  { 1189,	10,	5,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1189 = VLD4DUPd8_UPD
  { 1190,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1190 = VLD4DUPdAsm_16
  { 1191,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1191 = VLD4DUPdAsm_32
  { 1192,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1192 = VLD4DUPdAsm_8
  { 1193,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1193 = VLD4DUPdWB_fixed_Asm_16
  { 1194,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1194 = VLD4DUPdWB_fixed_Asm_32
  { 1195,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1195 = VLD4DUPdWB_fixed_Asm_8
  { 1196,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1196 = VLD4DUPdWB_register_Asm_16
  { 1197,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1197 = VLD4DUPdWB_register_Asm_32
  { 1198,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1198 = VLD4DUPdWB_register_Asm_8
  { 1199,	8,	4,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1199 = VLD4DUPq16
  { 1200,	10,	5,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1200 = VLD4DUPq16_UPD
  { 1201,	8,	4,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1201 = VLD4DUPq32
  { 1202,	10,	5,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1202 = VLD4DUPq32_UPD
  { 1203,	8,	4,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1203 = VLD4DUPq8
  { 1204,	10,	5,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1204 = VLD4DUPq8_UPD
  { 1205,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1205 = VLD4DUPqAsm_16
  { 1206,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1206 = VLD4DUPqAsm_32
  { 1207,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1207 = VLD4DUPqAsm_8
  { 1208,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1208 = VLD4DUPqWB_fixed_Asm_16
  { 1209,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1209 = VLD4DUPqWB_fixed_Asm_32
  { 1210,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1210 = VLD4DUPqWB_fixed_Asm_8
  { 1211,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1211 = VLD4DUPqWB_register_Asm_16
  { 1212,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1212 = VLD4DUPqWB_register_Asm_32
  { 1213,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1213 = VLD4DUPqWB_register_Asm_8
  { 1214,	13,	4,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1214 = VLD4LNd16
  { 1215,	7,	1,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1215 = VLD4LNd16Pseudo
  { 1216,	9,	2,	558,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1216 = VLD4LNd16Pseudo_UPD
  { 1217,	15,	5,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo190,0,0 },  // Inst #1217 = VLD4LNd16_UPD
  { 1218,	13,	4,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1218 = VLD4LNd32
  { 1219,	7,	1,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1219 = VLD4LNd32Pseudo
  { 1220,	9,	2,	558,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1220 = VLD4LNd32Pseudo_UPD
  { 1221,	15,	5,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo190,0,0 },  // Inst #1221 = VLD4LNd32_UPD
  { 1222,	13,	4,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1222 = VLD4LNd8
  { 1223,	7,	1,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1223 = VLD4LNd8Pseudo
  { 1224,	9,	2,	558,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1224 = VLD4LNd8Pseudo_UPD
  { 1225,	15,	5,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo190,0,0 },  // Inst #1225 = VLD4LNd8_UPD
  { 1226,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1226 = VLD4LNdAsm_16
  { 1227,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1227 = VLD4LNdAsm_32
  { 1228,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1228 = VLD4LNdAsm_8
  { 1229,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1229 = VLD4LNdWB_fixed_Asm_16
  { 1230,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1230 = VLD4LNdWB_fixed_Asm_32
  { 1231,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1231 = VLD4LNdWB_fixed_Asm_8
  { 1232,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1232 = VLD4LNdWB_register_Asm_16
  { 1233,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1233 = VLD4LNdWB_register_Asm_32
  { 1234,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1234 = VLD4LNdWB_register_Asm_8
  { 1235,	13,	4,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1235 = VLD4LNq16
  { 1236,	7,	1,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1236 = VLD4LNq16Pseudo
  { 1237,	9,	2,	558,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1237 = VLD4LNq16Pseudo_UPD
  { 1238,	15,	5,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo190,0,0 },  // Inst #1238 = VLD4LNq16_UPD
  { 1239,	13,	4,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1239 = VLD4LNq32
  { 1240,	7,	1,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1240 = VLD4LNq32Pseudo
  { 1241,	9,	2,	558,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1241 = VLD4LNq32Pseudo_UPD
  { 1242,	15,	5,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo190,0,0 },  // Inst #1242 = VLD4LNq32_UPD
  { 1243,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1243 = VLD4LNqAsm_16
  { 1244,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1244 = VLD4LNqAsm_32
  { 1245,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1245 = VLD4LNqWB_fixed_Asm_16
  { 1246,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1246 = VLD4LNqWB_fixed_Asm_32
  { 1247,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1247 = VLD4LNqWB_register_Asm_16
  { 1248,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1248 = VLD4LNqWB_register_Asm_32
  { 1249,	8,	4,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1249 = VLD4d16
  { 1250,	5,	1,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1250 = VLD4d16Pseudo
  { 1251,	7,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1251 = VLD4d16Pseudo_UPD
  { 1252,	10,	5,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1252 = VLD4d16_UPD
  { 1253,	8,	4,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1253 = VLD4d32
  { 1254,	5,	1,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1254 = VLD4d32Pseudo
  { 1255,	7,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1255 = VLD4d32Pseudo_UPD
  { 1256,	10,	5,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1256 = VLD4d32_UPD
  { 1257,	8,	4,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1257 = VLD4d8
  { 1258,	5,	1,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1258 = VLD4d8Pseudo
  { 1259,	7,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1259 = VLD4d8Pseudo_UPD
  { 1260,	10,	5,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1260 = VLD4d8_UPD
  { 1261,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1261 = VLD4dAsm_16
  { 1262,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1262 = VLD4dAsm_32
  { 1263,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1263 = VLD4dAsm_8
  { 1264,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1264 = VLD4dWB_fixed_Asm_16
  { 1265,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1265 = VLD4dWB_fixed_Asm_32
  { 1266,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1266 = VLD4dWB_fixed_Asm_8
  { 1267,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1267 = VLD4dWB_register_Asm_16
  { 1268,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1268 = VLD4dWB_register_Asm_32
  { 1269,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1269 = VLD4dWB_register_Asm_8
  { 1270,	8,	4,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1270 = VLD4q16
  { 1271,	8,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1271 = VLD4q16Pseudo_UPD
  { 1272,	10,	5,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1272 = VLD4q16_UPD
  { 1273,	6,	1,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1273 = VLD4q16oddPseudo
  { 1274,	8,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1274 = VLD4q16oddPseudo_UPD
  { 1275,	8,	4,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1275 = VLD4q32
  { 1276,	8,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1276 = VLD4q32Pseudo_UPD
  { 1277,	10,	5,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1277 = VLD4q32_UPD
  { 1278,	6,	1,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1278 = VLD4q32oddPseudo
  { 1279,	8,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1279 = VLD4q32oddPseudo_UPD
  { 1280,	8,	4,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1280 = VLD4q8
  { 1281,	8,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1281 = VLD4q8Pseudo_UPD
  { 1282,	10,	5,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1282 = VLD4q8_UPD
  { 1283,	6,	1,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1283 = VLD4q8oddPseudo
  { 1284,	8,	2,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1284 = VLD4q8oddPseudo_UPD
  { 1285,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1285 = VLD4qAsm_16
  { 1286,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1286 = VLD4qAsm_32
  { 1287,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1287 = VLD4qAsm_8
  { 1288,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1288 = VLD4qWB_fixed_Asm_16
  { 1289,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1289 = VLD4qWB_fixed_Asm_32
  { 1290,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1290 = VLD4qWB_fixed_Asm_8
  { 1291,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1291 = VLD4qWB_register_Asm_16
  { 1292,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1292 = VLD4qWB_register_Asm_32
  { 1293,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1293 = VLD4qWB_register_Asm_8
  { 1294,	5,	1,	515,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1294 = VLDMDDB_UPD
  { 1295,	4,	0,	514,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #1295 = VLDMDIA
  { 1296,	5,	1,	515,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1296 = VLDMDIA_UPD
  { 1297,	4,	1,	512,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x18004ULL, NULL, NULL, OperandInfo191,0,0 },  // Inst #1297 = VLDMQIA
  { 1298,	5,	1,	515,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1298 = VLDMSDB_UPD
  { 1299,	4,	0,	514,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #1299 = VLDMSIA
  { 1300,	5,	1,	515,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1300 = VLDMSIA_UPD
  { 1301,	5,	1,	508,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, NULL, NULL, OperandInfo192,0,0 },  // Inst #1301 = VLDRD
  { 1302,	5,	1,	509,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, NULL, NULL, OperandInfo193,0,0 },  // Inst #1302 = VLDRS
  { 1303,	3,	1,	446,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo194,0,0 },  // Inst #1303 = VMAXNMD
  { 1304,	3,	1,	446,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo194,0,0 },  // Inst #1304 = VMAXNMND
  { 1305,	3,	1,	446,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo195,0,0 },  // Inst #1305 = VMAXNMNQ
  { 1306,	3,	1,	446,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1306 = VMAXNMS
  { 1307,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1307 = VMAXfd
  { 1308,	5,	1,	443,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1308 = VMAXfq
  { 1309,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1309 = VMAXsv16i8
  { 1310,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1310 = VMAXsv2i32
  { 1311,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1311 = VMAXsv4i16
  { 1312,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1312 = VMAXsv4i32
  { 1313,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1313 = VMAXsv8i16
  { 1314,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1314 = VMAXsv8i8
  { 1315,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1315 = VMAXuv16i8
  { 1316,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1316 = VMAXuv2i32
  { 1317,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1317 = VMAXuv4i16
  { 1318,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1318 = VMAXuv4i32
  { 1319,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1319 = VMAXuv8i16
  { 1320,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1320 = VMAXuv8i8
  { 1321,	3,	1,	446,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo194,0,0 },  // Inst #1321 = VMINNMD
  { 1322,	3,	1,	446,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo194,0,0 },  // Inst #1322 = VMINNMND
  { 1323,	3,	1,	446,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo195,0,0 },  // Inst #1323 = VMINNMNQ
  { 1324,	3,	1,	446,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1324 = VMINNMS
  { 1325,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1325 = VMINfd
  { 1326,	5,	1,	443,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1326 = VMINfq
  { 1327,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1327 = VMINsv16i8
  { 1328,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1328 = VMINsv2i32
  { 1329,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1329 = VMINsv4i16
  { 1330,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1330 = VMINsv4i32
  { 1331,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1331 = VMINsv8i16
  { 1332,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1332 = VMINsv8i8
  { 1333,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1333 = VMINuv16i8
  { 1334,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1334 = VMINuv2i32
  { 1335,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1335 = VMINuv4i16
  { 1336,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1336 = VMINuv4i32
  { 1337,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1337 = VMINuv8i16
  { 1338,	5,	1,	444,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1338 = VMINuv8i8
  { 1339,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1339 = VMLAD
  { 1340,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1340 = VMLALslsv2i32
  { 1341,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1341 = VMLALslsv4i16
  { 1342,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1342 = VMLALsluv2i32
  { 1343,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1343 = VMLALsluv4i16
  { 1344,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1344 = VMLALsv2i64
  { 1345,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1345 = VMLALsv4i32
  { 1346,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1346 = VMLALsv8i16
  { 1347,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1347 = VMLALuv2i64
  { 1348,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1348 = VMLALuv4i32
  { 1349,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1349 = VMLALuv8i16
  { 1350,	6,	1,	467,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #1350 = VMLAS
  { 1351,	6,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1351 = VMLAfd
  { 1352,	6,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1352 = VMLAfq
  { 1353,	7,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1353 = VMLAslfd
  { 1354,	7,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo200,0,0 },  // Inst #1354 = VMLAslfq
  { 1355,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1355 = VMLAslv2i32
  { 1356,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo201,0,0 },  // Inst #1356 = VMLAslv4i16
  { 1357,	7,	1,	470,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo200,0,0 },  // Inst #1357 = VMLAslv4i32
  { 1358,	7,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo202,0,0 },  // Inst #1358 = VMLAslv8i16
  { 1359,	6,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1359 = VMLAv16i8
  { 1360,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1360 = VMLAv2i32
  { 1361,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1361 = VMLAv4i16
  { 1362,	6,	1,	470,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1362 = VMLAv4i32
  { 1363,	6,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1363 = VMLAv8i16
  { 1364,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1364 = VMLAv8i8
  { 1365,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1365 = VMLSD
  { 1366,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1366 = VMLSLslsv2i32
  { 1367,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1367 = VMLSLslsv4i16
  { 1368,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1368 = VMLSLsluv2i32
  { 1369,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1369 = VMLSLsluv4i16
  { 1370,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1370 = VMLSLsv2i64
  { 1371,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1371 = VMLSLsv4i32
  { 1372,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1372 = VMLSLsv8i16
  { 1373,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1373 = VMLSLuv2i64
  { 1374,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1374 = VMLSLuv4i32
  { 1375,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1375 = VMLSLuv8i16
  { 1376,	6,	1,	467,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #1376 = VMLSS
  { 1377,	6,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1377 = VMLSfd
  { 1378,	6,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1378 = VMLSfq
  { 1379,	7,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1379 = VMLSslfd
  { 1380,	7,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo200,0,0 },  // Inst #1380 = VMLSslfq
  { 1381,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1381 = VMLSslv2i32
  { 1382,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo201,0,0 },  // Inst #1382 = VMLSslv4i16
  { 1383,	7,	1,	470,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo200,0,0 },  // Inst #1383 = VMLSslv4i32
  { 1384,	7,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo202,0,0 },  // Inst #1384 = VMLSslv8i16
  { 1385,	6,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1385 = VMLSv16i8
  { 1386,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1386 = VMLSv2i32
  { 1387,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1387 = VMLSv4i16
  { 1388,	6,	1,	470,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1388 = VMLSv4i32
  { 1389,	6,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1389 = VMLSv8i16
  { 1390,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1390 = VMLSv8i8
  { 1391,	4,	1,	487,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1391 = VMOVD
  { 1392,	5,	1,	501,	4,	0|(1<<MCID_Predicable), 0x18a80ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1392 = VMOVDRR
  { 1393,	5,	1,	487,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1393 = VMOVDcc
  { 1394,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #1394 = VMOVLsv2i64
  { 1395,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #1395 = VMOVLsv4i32
  { 1396,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #1396 = VMOVLsv8i16
  { 1397,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #1397 = VMOVLuv2i64
  { 1398,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #1398 = VMOVLuv4i32
  { 1399,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #1399 = VMOVLuv8i16
  { 1400,	4,	1,	492,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1400 = VMOVNv2i32
  { 1401,	4,	1,	492,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1401 = VMOVNv4i16
  { 1402,	4,	1,	492,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1402 = VMOVNv8i8
  { 1403,	5,	2,	500,	4,	0|(1<<MCID_Predicable), 0x18980ULL, NULL, NULL, OperandInfo205,0,0 },  // Inst #1403 = VMOVRRD
  { 1404,	6,	2,	500,	4,	0|(1<<MCID_Predicable), 0x18980ULL, NULL, NULL, OperandInfo206,0,0 },  // Inst #1404 = VMOVRRS
  { 1405,	4,	1,	497,	4,	0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18900ULL, NULL, NULL, OperandInfo207,0,0 },  // Inst #1405 = VMOVRS
  { 1406,	4,	1,	488,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1406 = VMOVS
  { 1407,	4,	1,	498,	4,	0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18a00ULL, NULL, NULL, OperandInfo208,0,0 },  // Inst #1407 = VMOVSR
  { 1408,	6,	2,	502,	4,	0|(1<<MCID_Predicable), 0x18a80ULL, NULL, NULL, OperandInfo209,0,0 },  // Inst #1408 = VMOVSRR
  { 1409,	5,	1,	488,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1409 = VMOVScc
  { 1410,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1410 = VMOVv16i8
  { 1411,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1411 = VMOVv1i64
  { 1412,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1412 = VMOVv2f32
  { 1413,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1413 = VMOVv2i32
  { 1414,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1414 = VMOVv2i64
  { 1415,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1415 = VMOVv4f32
  { 1416,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1416 = VMOVv4i16
  { 1417,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1417 = VMOVv4i32
  { 1418,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1418 = VMOVv8i16
  { 1419,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1419 = VMOVv8i8
  { 1420,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1420 = VMRS
  { 1421,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1421 = VMRS_FPEXC
  { 1422,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1422 = VMRS_FPINST
  { 1423,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1423 = VMRS_FPINST2
  { 1424,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1424 = VMRS_FPSID
  { 1425,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1425 = VMRS_MVFR0
  { 1426,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1426 = VMRS_MVFR1
  { 1427,	3,	1,	505,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1427 = VMRS_MVFR2
  { 1428,	3,	0,	506,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1428 = VMSR
  { 1429,	3,	0,	506,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1429 = VMSR_FPEXC
  { 1430,	3,	0,	506,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1430 = VMSR_FPINST
  { 1431,	3,	0,	506,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1431 = VMSR_FPINST2
  { 1432,	3,	0,	506,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1432 = VMSR_FPSID
  { 1433,	5,	1,	461,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1433 = VMULD
  { 1434,	3,	1,	451,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo212,0,0 },  // Inst #1434 = VMULLp64
  { 1435,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1435 = VMULLp8
  { 1436,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo213,0,0 },  // Inst #1436 = VMULLslsv2i32
  { 1437,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo214,0,0 },  // Inst #1437 = VMULLslsv4i16
  { 1438,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo213,0,0 },  // Inst #1438 = VMULLsluv2i32
  { 1439,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo214,0,0 },  // Inst #1439 = VMULLsluv4i16
  { 1440,	5,	1,	453,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1440 = VMULLsv2i64
  { 1441,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1441 = VMULLsv4i32
  { 1442,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1442 = VMULLsv8i16
  { 1443,	5,	1,	453,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1443 = VMULLuv2i64
  { 1444,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1444 = VMULLuv4i32
  { 1445,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1445 = VMULLuv8i16
  { 1446,	5,	1,	454,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #1446 = VMULS
  { 1447,	5,	1,	455,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1447 = VMULfd
  { 1448,	5,	1,	456,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1448 = VMULfq
  { 1449,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1449 = VMULpd
  { 1450,	5,	1,	457,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1450 = VMULpq
  { 1451,	6,	1,	458,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1451 = VMULslfd
  { 1452,	6,	1,	459,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo216,0,0 },  // Inst #1452 = VMULslfq
  { 1453,	6,	1,	453,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1453 = VMULslv2i32
  { 1454,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo217,0,0 },  // Inst #1454 = VMULslv4i16
  { 1455,	6,	1,	460,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo216,0,0 },  // Inst #1455 = VMULslv4i32
  { 1456,	6,	1,	457,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1456 = VMULslv8i16
  { 1457,	5,	1,	457,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1457 = VMULv16i8
  { 1458,	5,	1,	453,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1458 = VMULv2i32
  { 1459,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1459 = VMULv4i16
  { 1460,	5,	1,	460,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1460 = VMULv4i32
  { 1461,	5,	1,	457,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1461 = VMULv8i16
  { 1462,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1462 = VMULv8i8
  { 1463,	4,	1,	490,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1463 = VMVNd
  { 1464,	4,	1,	490,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1464 = VMVNq
  { 1465,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1465 = VMVNv2i32
  { 1466,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1466 = VMVNv4i16
  { 1467,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1467 = VMVNv4i32
  { 1468,	4,	1,	489,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1468 = VMVNv8i16
  { 1469,	4,	1,	437,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1469 = VNEGD
  { 1470,	4,	1,	438,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1470 = VNEGS
  { 1471,	4,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1471 = VNEGf32q
  { 1472,	4,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1472 = VNEGfd
  { 1473,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1473 = VNEGs16d
  { 1474,	4,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1474 = VNEGs16q
  { 1475,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1475 = VNEGs32d
  { 1476,	4,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1476 = VNEGs32q
  { 1477,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1477 = VNEGs8d
  { 1478,	4,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1478 = VNEGs8q
  { 1479,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1479 = VNMLAD
  { 1480,	6,	1,	467,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #1480 = VNMLAS
  { 1481,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1481 = VNMLSD
  { 1482,	6,	1,	467,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #1482 = VNMLSS
  { 1483,	5,	1,	461,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1483 = VNMULD
  { 1484,	5,	1,	454,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #1484 = VNMULS
  { 1485,	5,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1485 = VORNd
  { 1486,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1486 = VORNq
  { 1487,	5,	1,	382,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1487 = VORRd
  { 1488,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #1488 = VORRiv2i32
  { 1489,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #1489 = VORRiv4i16
  { 1490,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo138,0,0 },  // Inst #1490 = VORRiv4i32
  { 1491,	5,	1,	383,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo138,0,0 },  // Inst #1491 = VORRiv8i16
  { 1492,	5,	1,	381,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1492 = VORRq
  { 1493,	5,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1493 = VPADALsv16i8
  { 1494,	5,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1494 = VPADALsv2i32
  { 1495,	5,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1495 = VPADALsv4i16
  { 1496,	5,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1496 = VPADALsv4i32
  { 1497,	5,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1497 = VPADALsv8i16
  { 1498,	5,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1498 = VPADALsv8i8
  { 1499,	5,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1499 = VPADALuv16i8
  { 1500,	5,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1500 = VPADALuv2i32
  { 1501,	5,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1501 = VPADALuv4i16
  { 1502,	5,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1502 = VPADALuv4i32
  { 1503,	5,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1503 = VPADALuv8i16
  { 1504,	5,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1504 = VPADALuv8i8
  { 1505,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1505 = VPADDLsv16i8
  { 1506,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1506 = VPADDLsv2i32
  { 1507,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1507 = VPADDLsv4i16
  { 1508,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1508 = VPADDLsv4i32
  { 1509,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1509 = VPADDLsv8i16
  { 1510,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1510 = VPADDLsv8i8
  { 1511,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1511 = VPADDLuv16i8
  { 1512,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1512 = VPADDLuv2i32
  { 1513,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1513 = VPADDLuv4i16
  { 1514,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1514 = VPADDLuv4i32
  { 1515,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1515 = VPADDLuv8i16
  { 1516,	4,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1516 = VPADDLuv8i8
  { 1517,	5,	1,	447,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1517 = VPADDf
  { 1518,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1518 = VPADDi16
  { 1519,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1519 = VPADDi32
  { 1520,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1520 = VPADDi8
  { 1521,	5,	1,	447,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1521 = VPMAXf
  { 1522,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1522 = VPMAXs16
  { 1523,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1523 = VPMAXs32
  { 1524,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1524 = VPMAXs8
  { 1525,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1525 = VPMAXu16
  { 1526,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1526 = VPMAXu32
  { 1527,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1527 = VPMAXu8
  { 1528,	5,	1,	447,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1528 = VPMINf
  { 1529,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1529 = VPMINs16
  { 1530,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1530 = VPMINs32
  { 1531,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1531 = VPMINs8
  { 1532,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1532 = VPMINu16
  { 1533,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1533 = VPMINu32
  { 1534,	5,	1,	444,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1534 = VPMINu8
  { 1535,	4,	1,	413,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1535 = VQABSv16i8
  { 1536,	4,	1,	414,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1536 = VQABSv2i32
  { 1537,	4,	1,	414,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1537 = VQABSv4i16
  { 1538,	4,	1,	413,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1538 = VQABSv4i32
  { 1539,	4,	1,	413,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1539 = VQABSv8i16
  { 1540,	4,	1,	414,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1540 = VQABSv8i8
  { 1541,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1541 = VQADDsv16i8
  { 1542,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1542 = VQADDsv1i64
  { 1543,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1543 = VQADDsv2i32
  { 1544,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1544 = VQADDsv2i64
  { 1545,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1545 = VQADDsv4i16
  { 1546,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1546 = VQADDsv4i32
  { 1547,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1547 = VQADDsv8i16
  { 1548,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1548 = VQADDsv8i8
  { 1549,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1549 = VQADDuv16i8
  { 1550,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1550 = VQADDuv1i64
  { 1551,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1551 = VQADDuv2i32
  { 1552,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1552 = VQADDuv2i64
  { 1553,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1553 = VQADDuv4i16
  { 1554,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1554 = VQADDuv4i32
  { 1555,	5,	1,	415,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1555 = VQADDuv8i16
  { 1556,	5,	1,	416,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1556 = VQADDuv8i8
  { 1557,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1557 = VQDMLALslv2i32
  { 1558,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1558 = VQDMLALslv4i16
  { 1559,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1559 = VQDMLALv2i64
  { 1560,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1560 = VQDMLALv4i32
  { 1561,	7,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1561 = VQDMLSLslv2i32
  { 1562,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1562 = VQDMLSLslv4i16
  { 1563,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1563 = VQDMLSLv2i64
  { 1564,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1564 = VQDMLSLv4i32
  { 1565,	6,	1,	453,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1565 = VQDMULHslv2i32
  { 1566,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo217,0,0 },  // Inst #1566 = VQDMULHslv4i16
  { 1567,	6,	1,	460,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo216,0,0 },  // Inst #1567 = VQDMULHslv4i32
  { 1568,	6,	1,	457,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1568 = VQDMULHslv8i16
  { 1569,	5,	1,	453,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1569 = VQDMULHv2i32
  { 1570,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1570 = VQDMULHv4i16
  { 1571,	5,	1,	460,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1571 = VQDMULHv4i32
  { 1572,	5,	1,	457,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1572 = VQDMULHv8i16
  { 1573,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo213,0,0 },  // Inst #1573 = VQDMULLslv2i32
  { 1574,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo214,0,0 },  // Inst #1574 = VQDMULLslv4i16
  { 1575,	5,	1,	453,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1575 = VQDMULLv2i64
  { 1576,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1576 = VQDMULLv4i32
  { 1577,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1577 = VQMOVNsuv2i32
  { 1578,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1578 = VQMOVNsuv4i16
  { 1579,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1579 = VQMOVNsuv8i8
  { 1580,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1580 = VQMOVNsv2i32
  { 1581,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1581 = VQMOVNsv4i16
  { 1582,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1582 = VQMOVNsv8i8
  { 1583,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1583 = VQMOVNuv2i32
  { 1584,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1584 = VQMOVNuv4i16
  { 1585,	4,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1585 = VQMOVNuv8i8
  { 1586,	4,	1,	413,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1586 = VQNEGv16i8
  { 1587,	4,	1,	414,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1587 = VQNEGv2i32
  { 1588,	4,	1,	414,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1588 = VQNEGv4i16
  { 1589,	4,	1,	413,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1589 = VQNEGv4i32
  { 1590,	4,	1,	413,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1590 = VQNEGv8i16
  { 1591,	4,	1,	414,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1591 = VQNEGv8i8
  { 1592,	6,	1,	453,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1592 = VQRDMULHslv2i32
  { 1593,	6,	1,	452,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo217,0,0 },  // Inst #1593 = VQRDMULHslv4i16
  { 1594,	6,	1,	460,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo216,0,0 },  // Inst #1594 = VQRDMULHslv4i32
  { 1595,	6,	1,	457,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1595 = VQRDMULHslv8i16
  { 1596,	5,	1,	453,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1596 = VQRDMULHv2i32
  { 1597,	5,	1,	452,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1597 = VQRDMULHv4i16
  { 1598,	5,	1,	460,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1598 = VQRDMULHv4i32
  { 1599,	5,	1,	457,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1599 = VQRDMULHv8i16
  { 1600,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1600 = VQRSHLsv16i8
  { 1601,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1601 = VQRSHLsv1i64
  { 1602,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1602 = VQRSHLsv2i32
  { 1603,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1603 = VQRSHLsv2i64
  { 1604,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1604 = VQRSHLsv4i16
  { 1605,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1605 = VQRSHLsv4i32
  { 1606,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1606 = VQRSHLsv8i16
  { 1607,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1607 = VQRSHLsv8i8
  { 1608,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1608 = VQRSHLuv16i8
  { 1609,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1609 = VQRSHLuv1i64
  { 1610,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1610 = VQRSHLuv2i32
  { 1611,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1611 = VQRSHLuv2i64
  { 1612,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1612 = VQRSHLuv4i16
  { 1613,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1613 = VQRSHLuv4i32
  { 1614,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1614 = VQRSHLuv8i16
  { 1615,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1615 = VQRSHLuv8i8
  { 1616,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1616 = VQRSHRNsv2i32
  { 1617,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1617 = VQRSHRNsv4i16
  { 1618,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1618 = VQRSHRNsv8i8
  { 1619,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1619 = VQRSHRNuv2i32
  { 1620,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1620 = VQRSHRNuv4i16
  { 1621,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1621 = VQRSHRNuv8i8
  { 1622,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1622 = VQRSHRUNv2i32
  { 1623,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1623 = VQRSHRUNv4i16
  { 1624,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1624 = VQRSHRUNv8i8
  { 1625,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1625 = VQSHLsiv16i8
  { 1626,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1626 = VQSHLsiv1i64
  { 1627,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1627 = VQSHLsiv2i32
  { 1628,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1628 = VQSHLsiv2i64
  { 1629,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1629 = VQSHLsiv4i16
  { 1630,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1630 = VQSHLsiv4i32
  { 1631,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1631 = VQSHLsiv8i16
  { 1632,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1632 = VQSHLsiv8i8
  { 1633,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1633 = VQSHLsuv16i8
  { 1634,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1634 = VQSHLsuv1i64
  { 1635,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1635 = VQSHLsuv2i32
  { 1636,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1636 = VQSHLsuv2i64
  { 1637,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1637 = VQSHLsuv4i16
  { 1638,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1638 = VQSHLsuv4i32
  { 1639,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1639 = VQSHLsuv8i16
  { 1640,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1640 = VQSHLsuv8i8
  { 1641,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1641 = VQSHLsv16i8
  { 1642,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1642 = VQSHLsv1i64
  { 1643,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1643 = VQSHLsv2i32
  { 1644,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1644 = VQSHLsv2i64
  { 1645,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1645 = VQSHLsv4i16
  { 1646,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1646 = VQSHLsv4i32
  { 1647,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1647 = VQSHLsv8i16
  { 1648,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1648 = VQSHLsv8i8
  { 1649,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1649 = VQSHLuiv16i8
  { 1650,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1650 = VQSHLuiv1i64
  { 1651,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1651 = VQSHLuiv2i32
  { 1652,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1652 = VQSHLuiv2i64
  { 1653,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1653 = VQSHLuiv4i16
  { 1654,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1654 = VQSHLuiv4i32
  { 1655,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1655 = VQSHLuiv8i16
  { 1656,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1656 = VQSHLuiv8i8
  { 1657,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1657 = VQSHLuv16i8
  { 1658,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1658 = VQSHLuv1i64
  { 1659,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1659 = VQSHLuv2i32
  { 1660,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1660 = VQSHLuv2i64
  { 1661,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1661 = VQSHLuv4i16
  { 1662,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1662 = VQSHLuv4i32
  { 1663,	5,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1663 = VQSHLuv8i16
  { 1664,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1664 = VQSHLuv8i8
  { 1665,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1665 = VQSHRNsv2i32
  { 1666,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1666 = VQSHRNsv4i16
  { 1667,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1667 = VQSHRNsv8i8
  { 1668,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1668 = VQSHRNuv2i32
  { 1669,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1669 = VQSHRNuv4i16
  { 1670,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1670 = VQSHRNuv8i8
  { 1671,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1671 = VQSHRUNv2i32
  { 1672,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1672 = VQSHRUNv4i16
  { 1673,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1673 = VQSHRUNv8i8
  { 1674,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1674 = VQSUBsv16i8
  { 1675,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1675 = VQSUBsv1i64
  { 1676,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1676 = VQSUBsv2i32
  { 1677,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1677 = VQSUBsv2i64
  { 1678,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1678 = VQSUBsv4i16
  { 1679,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1679 = VQSUBsv4i32
  { 1680,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1680 = VQSUBsv8i16
  { 1681,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1681 = VQSUBsv8i8
  { 1682,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1682 = VQSUBuv16i8
  { 1683,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1683 = VQSUBuv1i64
  { 1684,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1684 = VQSUBuv2i32
  { 1685,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1685 = VQSUBuv2i64
  { 1686,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1686 = VQSUBuv4i16
  { 1687,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1687 = VQSUBuv4i32
  { 1688,	5,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1688 = VQSUBuv8i16
  { 1689,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1689 = VQSUBuv8i8
  { 1690,	5,	1,	424,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1690 = VRADDHNv2i32
  { 1691,	5,	1,	424,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1691 = VRADDHNv4i16
  { 1692,	5,	1,	424,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1692 = VRADDHNv8i8
  { 1693,	4,	1,	419,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1693 = VRECPEd
  { 1694,	4,	1,	419,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1694 = VRECPEfd
  { 1695,	4,	1,	420,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1695 = VRECPEfq
  { 1696,	4,	1,	420,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1696 = VRECPEq
  { 1697,	5,	1,	449,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1697 = VRECPSfd
  { 1698,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1698 = VRECPSfq
  { 1699,	4,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1699 = VREV16d8
  { 1700,	4,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1700 = VREV16q8
  { 1701,	4,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1701 = VREV32d16
  { 1702,	4,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1702 = VREV32d8
  { 1703,	4,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1703 = VREV32q16
  { 1704,	4,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1704 = VREV32q8
  { 1705,	4,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1705 = VREV64d16
  { 1706,	4,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1706 = VREV64d32
  { 1707,	4,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1707 = VREV64d8
  { 1708,	4,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1708 = VREV64q16
  { 1709,	4,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1709 = VREV64q32
  { 1710,	4,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1710 = VREV64q8
  { 1711,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1711 = VRHADDsv16i8
  { 1712,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1712 = VRHADDsv2i32
  { 1713,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1713 = VRHADDsv4i16
  { 1714,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1714 = VRHADDsv4i32
  { 1715,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1715 = VRHADDsv8i16
  { 1716,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1716 = VRHADDsv8i8
  { 1717,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1717 = VRHADDuv16i8
  { 1718,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1718 = VRHADDuv2i32
  { 1719,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1719 = VRHADDuv4i16
  { 1720,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1720 = VRHADDuv4i32
  { 1721,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1721 = VRHADDuv8i16
  { 1722,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1722 = VRHADDuv8i8
  { 1723,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1723 = VRINTAD
  { 1724,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1724 = VRINTAND
  { 1725,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1725 = VRINTANQ
  { 1726,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #1726 = VRINTAS
  { 1727,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1727 = VRINTMD
  { 1728,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1728 = VRINTMND
  { 1729,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1729 = VRINTMNQ
  { 1730,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #1730 = VRINTMS
  { 1731,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1731 = VRINTND
  { 1732,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1732 = VRINTNND
  { 1733,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1733 = VRINTNNQ
  { 1734,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #1734 = VRINTNS
  { 1735,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1735 = VRINTPD
  { 1736,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1736 = VRINTPND
  { 1737,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1737 = VRINTPNQ
  { 1738,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #1738 = VRINTPS
  { 1739,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1739 = VRINTRD
  { 1740,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1740 = VRINTRS
  { 1741,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1741 = VRINTXD
  { 1742,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1742 = VRINTXND
  { 1743,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1743 = VRINTXNQ
  { 1744,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1744 = VRINTXS
  { 1745,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1745 = VRINTZD
  { 1746,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #1746 = VRINTZND
  { 1747,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1747 = VRINTZNQ
  { 1748,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1748 = VRINTZS
  { 1749,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1749 = VRSHLsv16i8
  { 1750,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1750 = VRSHLsv1i64
  { 1751,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1751 = VRSHLsv2i32
  { 1752,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1752 = VRSHLsv2i64
  { 1753,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1753 = VRSHLsv4i16
  { 1754,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1754 = VRSHLsv4i32
  { 1755,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1755 = VRSHLsv8i16
  { 1756,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1756 = VRSHLsv8i8
  { 1757,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1757 = VRSHLuv16i8
  { 1758,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1758 = VRSHLuv1i64
  { 1759,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1759 = VRSHLuv2i32
  { 1760,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1760 = VRSHLuv2i64
  { 1761,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1761 = VRSHLuv4i16
  { 1762,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1762 = VRSHLuv4i32
  { 1763,	5,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1763 = VRSHLuv8i16
  { 1764,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1764 = VRSHLuv8i8
  { 1765,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1765 = VRSHRNv2i32
  { 1766,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1766 = VRSHRNv4i16
  { 1767,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1767 = VRSHRNv8i8
  { 1768,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1768 = VRSHRsv16i8
  { 1769,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1769 = VRSHRsv1i64
  { 1770,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1770 = VRSHRsv2i32
  { 1771,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1771 = VRSHRsv2i64
  { 1772,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1772 = VRSHRsv4i16
  { 1773,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1773 = VRSHRsv4i32
  { 1774,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1774 = VRSHRsv8i16
  { 1775,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1775 = VRSHRsv8i8
  { 1776,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1776 = VRSHRuv16i8
  { 1777,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1777 = VRSHRuv1i64
  { 1778,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1778 = VRSHRuv2i32
  { 1779,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1779 = VRSHRuv2i64
  { 1780,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1780 = VRSHRuv4i16
  { 1781,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1781 = VRSHRuv4i32
  { 1782,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1782 = VRSHRuv8i16
  { 1783,	5,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1783 = VRSHRuv8i8
  { 1784,	4,	1,	419,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1784 = VRSQRTEd
  { 1785,	4,	1,	419,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1785 = VRSQRTEfd
  { 1786,	4,	1,	420,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1786 = VRSQRTEfq
  { 1787,	4,	1,	420,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1787 = VRSQRTEq
  { 1788,	5,	1,	449,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1788 = VRSQRTSfd
  { 1789,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1789 = VRSQRTSfq
  { 1790,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1790 = VRSRAsv16i8
  { 1791,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1791 = VRSRAsv1i64
  { 1792,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1792 = VRSRAsv2i32
  { 1793,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1793 = VRSRAsv2i64
  { 1794,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1794 = VRSRAsv4i16
  { 1795,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1795 = VRSRAsv4i32
  { 1796,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1796 = VRSRAsv8i16
  { 1797,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1797 = VRSRAsv8i8
  { 1798,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1798 = VRSRAuv16i8
  { 1799,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1799 = VRSRAuv1i64
  { 1800,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1800 = VRSRAuv2i32
  { 1801,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1801 = VRSRAuv2i64
  { 1802,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1802 = VRSRAuv4i16
  { 1803,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1803 = VRSRAuv4i32
  { 1804,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1804 = VRSRAuv8i16
  { 1805,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1805 = VRSRAuv8i8
  { 1806,	5,	1,	424,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1806 = VRSUBHNv2i32
  { 1807,	5,	1,	424,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1807 = VRSUBHNv4i16
  { 1808,	5,	1,	424,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1808 = VRSUBHNv8i8
  { 1809,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo194,0,0 },  // Inst #1809 = VSELEQD
  { 1810,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo196,0,0 },  // Inst #1810 = VSELEQS
  { 1811,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo194,0,0 },  // Inst #1811 = VSELGED
  { 1812,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo196,0,0 },  // Inst #1812 = VSELGES
  { 1813,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo194,0,0 },  // Inst #1813 = VSELGTD
  { 1814,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo196,0,0 },  // Inst #1814 = VSELGTS
  { 1815,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo194,0,0 },  // Inst #1815 = VSELVSD
  { 1816,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo196,0,0 },  // Inst #1816 = VSELVSS
  { 1817,	6,	1,	499,	4,	0|(1<<MCID_Predicable), 0x10e00ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #1817 = VSETLNi16
  { 1818,	6,	1,	499,	4,	0|(1<<MCID_Predicable), 0x10e00ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #1818 = VSETLNi32
  { 1819,	6,	1,	499,	4,	0|(1<<MCID_Predicable), 0x10e00ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #1819 = VSETLNi8
  { 1820,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1820 = VSHLLi16
  { 1821,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1821 = VSHLLi32
  { 1822,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1822 = VSHLLi8
  { 1823,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1823 = VSHLLsv2i64
  { 1824,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1824 = VSHLLsv4i32
  { 1825,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1825 = VSHLLsv8i16
  { 1826,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1826 = VSHLLuv2i64
  { 1827,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1827 = VSHLLuv4i32
  { 1828,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #1828 = VSHLLuv8i16
  { 1829,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1829 = VSHLiv16i8
  { 1830,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1830 = VSHLiv1i64
  { 1831,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1831 = VSHLiv2i32
  { 1832,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1832 = VSHLiv2i64
  { 1833,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1833 = VSHLiv4i16
  { 1834,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1834 = VSHLiv4i32
  { 1835,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1835 = VSHLiv8i16
  { 1836,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1836 = VSHLiv8i8
  { 1837,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1837 = VSHLsv16i8
  { 1838,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1838 = VSHLsv1i64
  { 1839,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1839 = VSHLsv2i32
  { 1840,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1840 = VSHLsv2i64
  { 1841,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1841 = VSHLsv4i16
  { 1842,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1842 = VSHLsv4i32
  { 1843,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1843 = VSHLsv8i16
  { 1844,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1844 = VSHLsv8i8
  { 1845,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1845 = VSHLuv16i8
  { 1846,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1846 = VSHLuv1i64
  { 1847,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1847 = VSHLuv2i32
  { 1848,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1848 = VSHLuv2i64
  { 1849,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1849 = VSHLuv4i16
  { 1850,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1850 = VSHLuv4i32
  { 1851,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1851 = VSHLuv8i16
  { 1852,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1852 = VSHLuv8i8
  { 1853,	5,	1,	422,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1853 = VSHRNv2i32
  { 1854,	5,	1,	422,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1854 = VSHRNv4i16
  { 1855,	5,	1,	422,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1855 = VSHRNv8i8
  { 1856,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1856 = VSHRsv16i8
  { 1857,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1857 = VSHRsv1i64
  { 1858,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1858 = VSHRsv2i32
  { 1859,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1859 = VSHRsv2i64
  { 1860,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1860 = VSHRsv4i16
  { 1861,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1861 = VSHRsv4i32
  { 1862,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1862 = VSHRsv8i16
  { 1863,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1863 = VSHRsv8i8
  { 1864,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1864 = VSHRuv16i8
  { 1865,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1865 = VSHRuv1i64
  { 1866,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1866 = VSHRuv2i32
  { 1867,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1867 = VSHRuv2i64
  { 1868,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1868 = VSHRuv4i16
  { 1869,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1869 = VSHRuv4i32
  { 1870,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1870 = VSHRuv8i16
  { 1871,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1871 = VSHRuv8i8
  { 1872,	5,	1,	189,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #1872 = VSHTOD
  { 1873,	5,	1,	190,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #1873 = VSHTOS
  { 1874,	4,	1,	481,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1874 = VSITOD
  { 1875,	4,	1,	482,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1875 = VSITOS
  { 1876,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1876 = VSLIv16i8
  { 1877,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo229,0,0 },  // Inst #1877 = VSLIv1i64
  { 1878,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo229,0,0 },  // Inst #1878 = VSLIv2i32
  { 1879,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1879 = VSLIv2i64
  { 1880,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo229,0,0 },  // Inst #1880 = VSLIv4i16
  { 1881,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1881 = VSLIv4i32
  { 1882,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1882 = VSLIv8i16
  { 1883,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo229,0,0 },  // Inst #1883 = VSLIv8i8
  { 1884,	5,	1,	189,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #1884 = VSLTOD
  { 1885,	5,	1,	190,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #1885 = VSLTOS
  { 1886,	4,	1,	589,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1886 = VSQRTD
  { 1887,	4,	1,	587,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1887 = VSQRTS
  { 1888,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1888 = VSRAsv16i8
  { 1889,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1889 = VSRAsv1i64
  { 1890,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1890 = VSRAsv2i32
  { 1891,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1891 = VSRAsv2i64
  { 1892,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1892 = VSRAsv4i16
  { 1893,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1893 = VSRAsv4i32
  { 1894,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1894 = VSRAsv8i16
  { 1895,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1895 = VSRAsv8i8
  { 1896,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1896 = VSRAuv16i8
  { 1897,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1897 = VSRAuv1i64
  { 1898,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1898 = VSRAuv2i32
  { 1899,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1899 = VSRAuv2i64
  { 1900,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1900 = VSRAuv4i16
  { 1901,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1901 = VSRAuv4i32
  { 1902,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1902 = VSRAuv8i16
  { 1903,	6,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1903 = VSRAuv8i8
  { 1904,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1904 = VSRIv16i8
  { 1905,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1905 = VSRIv1i64
  { 1906,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1906 = VSRIv2i32
  { 1907,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1907 = VSRIv2i64
  { 1908,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1908 = VSRIv4i16
  { 1909,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1909 = VSRIv4i32
  { 1910,	6,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1910 = VSRIv8i16
  { 1911,	6,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1911 = VSRIv8i8
  { 1912,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo230,0,0 },  // Inst #1912 = VST1LNd16
  { 1913,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1913 = VST1LNd16_UPD
  { 1914,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo230,0,0 },  // Inst #1914 = VST1LNd32
  { 1915,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1915 = VST1LNd32_UPD
  { 1916,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo230,0,0 },  // Inst #1916 = VST1LNd8
  { 1917,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1917 = VST1LNd8_UPD
  { 1918,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1918 = VST1LNdAsm_16
  { 1919,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1919 = VST1LNdAsm_32
  { 1920,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1920 = VST1LNdAsm_8
  { 1921,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1921 = VST1LNdWB_fixed_Asm_16
  { 1922,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1922 = VST1LNdWB_fixed_Asm_32
  { 1923,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1923 = VST1LNdWB_fixed_Asm_8
  { 1924,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1924 = VST1LNdWB_register_Asm_16
  { 1925,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1925 = VST1LNdWB_register_Asm_32
  { 1926,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #1926 = VST1LNdWB_register_Asm_8
  { 1927,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1927 = VST1LNq16Pseudo
  { 1928,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1928 = VST1LNq16Pseudo_UPD
  { 1929,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1929 = VST1LNq32Pseudo
  { 1930,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1930 = VST1LNq32Pseudo_UPD
  { 1931,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1931 = VST1LNq8Pseudo
  { 1932,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1932 = VST1LNq8Pseudo_UPD
  { 1933,	5,	0,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1933 = VST1d16
  { 1934,	5,	0,	566,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1934 = VST1d16Q
  { 1935,	6,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1935 = VST1d16Qwb_fixed
  { 1936,	7,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1936 = VST1d16Qwb_register
  { 1937,	5,	0,	563,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1937 = VST1d16T
  { 1938,	6,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1938 = VST1d16Twb_fixed
  { 1939,	7,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1939 = VST1d16Twb_register
  { 1940,	6,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1940 = VST1d16wb_fixed
  { 1941,	7,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1941 = VST1d16wb_register
  { 1942,	5,	0,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1942 = VST1d32
  { 1943,	5,	0,	566,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1943 = VST1d32Q
  { 1944,	6,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1944 = VST1d32Qwb_fixed
  { 1945,	7,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1945 = VST1d32Qwb_register
  { 1946,	5,	0,	563,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1946 = VST1d32T
  { 1947,	6,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1947 = VST1d32Twb_fixed
  { 1948,	7,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1948 = VST1d32Twb_register
  { 1949,	6,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1949 = VST1d32wb_fixed
  { 1950,	7,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1950 = VST1d32wb_register
  { 1951,	5,	0,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1951 = VST1d64
  { 1952,	5,	0,	566,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1952 = VST1d64Q
  { 1953,	5,	0,	566,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #1953 = VST1d64QPseudo
  { 1954,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1954 = VST1d64QPseudoWB_fixed
  { 1955,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1955 = VST1d64QPseudoWB_register
  { 1956,	6,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1956 = VST1d64Qwb_fixed
  { 1957,	7,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1957 = VST1d64Qwb_register
  { 1958,	5,	0,	563,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1958 = VST1d64T
  { 1959,	5,	0,	563,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #1959 = VST1d64TPseudo
  { 1960,	7,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1960 = VST1d64TPseudoWB_fixed
  { 1961,	7,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1961 = VST1d64TPseudoWB_register
  { 1962,	6,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1962 = VST1d64Twb_fixed
  { 1963,	7,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1963 = VST1d64Twb_register
  { 1964,	6,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1964 = VST1d64wb_fixed
  { 1965,	7,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1965 = VST1d64wb_register
  { 1966,	5,	0,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1966 = VST1d8
  { 1967,	5,	0,	566,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1967 = VST1d8Q
  { 1968,	6,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1968 = VST1d8Qwb_fixed
  { 1969,	7,	1,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1969 = VST1d8Qwb_register
  { 1970,	5,	0,	563,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1970 = VST1d8T
  { 1971,	6,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1971 = VST1d8Twb_fixed
  { 1972,	7,	1,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1972 = VST1d8Twb_register
  { 1973,	6,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1973 = VST1d8wb_fixed
  { 1974,	7,	1,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1974 = VST1d8wb_register
  { 1975,	5,	0,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1975 = VST1q16
  { 1976,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1976 = VST1q16wb_fixed
  { 1977,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #1977 = VST1q16wb_register
  { 1978,	5,	0,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1978 = VST1q32
  { 1979,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1979 = VST1q32wb_fixed
  { 1980,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #1980 = VST1q32wb_register
  { 1981,	5,	0,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1981 = VST1q64
  { 1982,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1982 = VST1q64wb_fixed
  { 1983,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #1983 = VST1q64wb_register
  { 1984,	5,	0,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1984 = VST1q8
  { 1985,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1985 = VST1q8wb_fixed
  { 1986,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #1986 = VST1q8wb_register
  { 1987,	7,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #1987 = VST2LNd16
  { 1988,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1988 = VST2LNd16Pseudo
  { 1989,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1989 = VST2LNd16Pseudo_UPD
  { 1990,	9,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #1990 = VST2LNd16_UPD
  { 1991,	7,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #1991 = VST2LNd32
  { 1992,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1992 = VST2LNd32Pseudo
  { 1993,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1993 = VST2LNd32Pseudo_UPD
  { 1994,	9,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #1994 = VST2LNd32_UPD
  { 1995,	7,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #1995 = VST2LNd8
  { 1996,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1996 = VST2LNd8Pseudo
  { 1997,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1997 = VST2LNd8Pseudo_UPD
  { 1998,	9,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #1998 = VST2LNd8_UPD
  { 1999,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1999 = VST2LNdAsm_16
  { 2000,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2000 = VST2LNdAsm_32
  { 2001,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2001 = VST2LNdAsm_8
  { 2002,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2002 = VST2LNdWB_fixed_Asm_16
  { 2003,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2003 = VST2LNdWB_fixed_Asm_32
  { 2004,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2004 = VST2LNdWB_fixed_Asm_8
  { 2005,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2005 = VST2LNdWB_register_Asm_16
  { 2006,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2006 = VST2LNdWB_register_Asm_32
  { 2007,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2007 = VST2LNdWB_register_Asm_8
  { 2008,	7,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #2008 = VST2LNq16
  { 2009,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2009 = VST2LNq16Pseudo
  { 2010,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2010 = VST2LNq16Pseudo_UPD
  { 2011,	9,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2011 = VST2LNq16_UPD
  { 2012,	7,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #2012 = VST2LNq32
  { 2013,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2013 = VST2LNq32Pseudo
  { 2014,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2014 = VST2LNq32Pseudo_UPD
  { 2015,	9,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2015 = VST2LNq32_UPD
  { 2016,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2016 = VST2LNqAsm_16
  { 2017,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2017 = VST2LNqAsm_32
  { 2018,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2018 = VST2LNqWB_fixed_Asm_16
  { 2019,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2019 = VST2LNqWB_fixed_Asm_32
  { 2020,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2020 = VST2LNqWB_register_Asm_16
  { 2021,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2021 = VST2LNqWB_register_Asm_32
  { 2022,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2022 = VST2b16
  { 2023,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2023 = VST2b16wb_fixed
  { 2024,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2024 = VST2b16wb_register
  { 2025,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2025 = VST2b32
  { 2026,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2026 = VST2b32wb_fixed
  { 2027,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2027 = VST2b32wb_register
  { 2028,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2028 = VST2b8
  { 2029,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2029 = VST2b8wb_fixed
  { 2030,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2030 = VST2b8wb_register
  { 2031,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2031 = VST2d16
  { 2032,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2032 = VST2d16wb_fixed
  { 2033,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2033 = VST2d16wb_register
  { 2034,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2034 = VST2d32
  { 2035,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2035 = VST2d32wb_fixed
  { 2036,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2036 = VST2d32wb_register
  { 2037,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2037 = VST2d8
  { 2038,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2038 = VST2d8wb_fixed
  { 2039,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2039 = VST2d8wb_register
  { 2040,	5,	0,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #2040 = VST2q16
  { 2041,	5,	0,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2041 = VST2q16Pseudo
  { 2042,	6,	1,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo246,0,0 },  // Inst #2042 = VST2q16PseudoWB_fixed
  { 2043,	7,	1,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2043 = VST2q16PseudoWB_register
  { 2044,	6,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #2044 = VST2q16wb_fixed
  { 2045,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2045 = VST2q16wb_register
  { 2046,	5,	0,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #2046 = VST2q32
  { 2047,	5,	0,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2047 = VST2q32Pseudo
  { 2048,	6,	1,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo246,0,0 },  // Inst #2048 = VST2q32PseudoWB_fixed
  { 2049,	7,	1,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2049 = VST2q32PseudoWB_register
  { 2050,	6,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #2050 = VST2q32wb_fixed
  { 2051,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2051 = VST2q32wb_register
  { 2052,	5,	0,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #2052 = VST2q8
  { 2053,	5,	0,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2053 = VST2q8Pseudo
  { 2054,	6,	1,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo246,0,0 },  // Inst #2054 = VST2q8PseudoWB_fixed
  { 2055,	7,	1,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2055 = VST2q8PseudoWB_register
  { 2056,	6,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #2056 = VST2q8wb_fixed
  { 2057,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2057 = VST2q8wb_register
  { 2058,	8,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2058 = VST3LNd16
  { 2059,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2059 = VST3LNd16Pseudo
  { 2060,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2060 = VST3LNd16Pseudo_UPD
  { 2061,	10,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2061 = VST3LNd16_UPD
  { 2062,	8,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2062 = VST3LNd32
  { 2063,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2063 = VST3LNd32Pseudo
  { 2064,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2064 = VST3LNd32Pseudo_UPD
  { 2065,	10,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2065 = VST3LNd32_UPD
  { 2066,	8,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2066 = VST3LNd8
  { 2067,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2067 = VST3LNd8Pseudo
  { 2068,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2068 = VST3LNd8Pseudo_UPD
  { 2069,	10,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2069 = VST3LNd8_UPD
  { 2070,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2070 = VST3LNdAsm_16
  { 2071,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2071 = VST3LNdAsm_32
  { 2072,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2072 = VST3LNdAsm_8
  { 2073,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2073 = VST3LNdWB_fixed_Asm_16
  { 2074,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2074 = VST3LNdWB_fixed_Asm_32
  { 2075,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2075 = VST3LNdWB_fixed_Asm_8
  { 2076,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2076 = VST3LNdWB_register_Asm_16
  { 2077,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2077 = VST3LNdWB_register_Asm_32
  { 2078,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2078 = VST3LNdWB_register_Asm_8
  { 2079,	8,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2079 = VST3LNq16
  { 2080,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2080 = VST3LNq16Pseudo
  { 2081,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2081 = VST3LNq16Pseudo_UPD
  { 2082,	10,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2082 = VST3LNq16_UPD
  { 2083,	8,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2083 = VST3LNq32
  { 2084,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2084 = VST3LNq32Pseudo
  { 2085,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2085 = VST3LNq32Pseudo_UPD
  { 2086,	10,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2086 = VST3LNq32_UPD
  { 2087,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2087 = VST3LNqAsm_16
  { 2088,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2088 = VST3LNqAsm_32
  { 2089,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2089 = VST3LNqWB_fixed_Asm_16
  { 2090,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2090 = VST3LNqWB_fixed_Asm_32
  { 2091,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2091 = VST3LNqWB_register_Asm_16
  { 2092,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2092 = VST3LNqWB_register_Asm_32
  { 2093,	7,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2093 = VST3d16
  { 2094,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2094 = VST3d16Pseudo
  { 2095,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2095 = VST3d16Pseudo_UPD
  { 2096,	9,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2096 = VST3d16_UPD
  { 2097,	7,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2097 = VST3d32
  { 2098,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2098 = VST3d32Pseudo
  { 2099,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2099 = VST3d32Pseudo_UPD
  { 2100,	9,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2100 = VST3d32_UPD
  { 2101,	7,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2101 = VST3d8
  { 2102,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2102 = VST3d8Pseudo
  { 2103,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2103 = VST3d8Pseudo_UPD
  { 2104,	9,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2104 = VST3d8_UPD
  { 2105,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2105 = VST3dAsm_16
  { 2106,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2106 = VST3dAsm_32
  { 2107,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2107 = VST3dAsm_8
  { 2108,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2108 = VST3dWB_fixed_Asm_16
  { 2109,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2109 = VST3dWB_fixed_Asm_32
  { 2110,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2110 = VST3dWB_fixed_Asm_8
  { 2111,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2111 = VST3dWB_register_Asm_16
  { 2112,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2112 = VST3dWB_register_Asm_32
  { 2113,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2113 = VST3dWB_register_Asm_8
  { 2114,	7,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2114 = VST3q16
  { 2115,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2115 = VST3q16Pseudo_UPD
  { 2116,	9,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2116 = VST3q16_UPD
  { 2117,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2117 = VST3q16oddPseudo
  { 2118,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2118 = VST3q16oddPseudo_UPD
  { 2119,	7,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2119 = VST3q32
  { 2120,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2120 = VST3q32Pseudo_UPD
  { 2121,	9,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2121 = VST3q32_UPD
  { 2122,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2122 = VST3q32oddPseudo
  { 2123,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2123 = VST3q32oddPseudo_UPD
  { 2124,	7,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2124 = VST3q8
  { 2125,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2125 = VST3q8Pseudo_UPD
  { 2126,	9,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2126 = VST3q8_UPD
  { 2127,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2127 = VST3q8oddPseudo
  { 2128,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2128 = VST3q8oddPseudo_UPD
  { 2129,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2129 = VST3qAsm_16
  { 2130,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2130 = VST3qAsm_32
  { 2131,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2131 = VST3qAsm_8
  { 2132,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2132 = VST3qWB_fixed_Asm_16
  { 2133,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2133 = VST3qWB_fixed_Asm_32
  { 2134,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2134 = VST3qWB_fixed_Asm_8
  { 2135,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2135 = VST3qWB_register_Asm_16
  { 2136,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2136 = VST3qWB_register_Asm_32
  { 2137,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2137 = VST3qWB_register_Asm_8
  { 2138,	9,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2138 = VST4LNd16
  { 2139,	6,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2139 = VST4LNd16Pseudo
  { 2140,	8,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2140 = VST4LNd16Pseudo_UPD
  { 2141,	11,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2141 = VST4LNd16_UPD
  { 2142,	9,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2142 = VST4LNd32
  { 2143,	6,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2143 = VST4LNd32Pseudo
  { 2144,	8,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2144 = VST4LNd32Pseudo_UPD
  { 2145,	11,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2145 = VST4LNd32_UPD
  { 2146,	9,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2146 = VST4LNd8
  { 2147,	6,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2147 = VST4LNd8Pseudo
  { 2148,	8,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2148 = VST4LNd8Pseudo_UPD
  { 2149,	11,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2149 = VST4LNd8_UPD
  { 2150,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2150 = VST4LNdAsm_16
  { 2151,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2151 = VST4LNdAsm_32
  { 2152,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2152 = VST4LNdAsm_8
  { 2153,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2153 = VST4LNdWB_fixed_Asm_16
  { 2154,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2154 = VST4LNdWB_fixed_Asm_32
  { 2155,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2155 = VST4LNdWB_fixed_Asm_8
  { 2156,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2156 = VST4LNdWB_register_Asm_16
  { 2157,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2157 = VST4LNdWB_register_Asm_32
  { 2158,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2158 = VST4LNdWB_register_Asm_8
  { 2159,	9,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2159 = VST4LNq16
  { 2160,	6,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2160 = VST4LNq16Pseudo
  { 2161,	8,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2161 = VST4LNq16Pseudo_UPD
  { 2162,	11,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2162 = VST4LNq16_UPD
  { 2163,	9,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2163 = VST4LNq32
  { 2164,	6,	0,	584,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2164 = VST4LNq32Pseudo
  { 2165,	8,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2165 = VST4LNq32Pseudo_UPD
  { 2166,	11,	1,	585,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2166 = VST4LNq32_UPD
  { 2167,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2167 = VST4LNqAsm_16
  { 2168,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2168 = VST4LNqAsm_32
  { 2169,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2169 = VST4LNqWB_fixed_Asm_16
  { 2170,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2170 = VST4LNqWB_fixed_Asm_32
  { 2171,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2171 = VST4LNqWB_register_Asm_16
  { 2172,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #2172 = VST4LNqWB_register_Asm_32
  { 2173,	8,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2173 = VST4d16
  { 2174,	5,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2174 = VST4d16Pseudo
  { 2175,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2175 = VST4d16Pseudo_UPD
  { 2176,	10,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2176 = VST4d16_UPD
  { 2177,	8,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2177 = VST4d32
  { 2178,	5,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2178 = VST4d32Pseudo
  { 2179,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2179 = VST4d32Pseudo_UPD
  { 2180,	10,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2180 = VST4d32_UPD
  { 2181,	8,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2181 = VST4d8
  { 2182,	5,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2182 = VST4d8Pseudo
  { 2183,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2183 = VST4d8Pseudo_UPD
  { 2184,	10,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2184 = VST4d8_UPD
  { 2185,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2185 = VST4dAsm_16
  { 2186,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2186 = VST4dAsm_32
  { 2187,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2187 = VST4dAsm_8
  { 2188,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2188 = VST4dWB_fixed_Asm_16
  { 2189,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2189 = VST4dWB_fixed_Asm_32
  { 2190,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2190 = VST4dWB_fixed_Asm_8
  { 2191,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2191 = VST4dWB_register_Asm_16
  { 2192,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2192 = VST4dWB_register_Asm_32
  { 2193,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2193 = VST4dWB_register_Asm_8
  { 2194,	8,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2194 = VST4q16
  { 2195,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2195 = VST4q16Pseudo_UPD
  { 2196,	10,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2196 = VST4q16_UPD
  { 2197,	5,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2197 = VST4q16oddPseudo
  { 2198,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2198 = VST4q16oddPseudo_UPD
  { 2199,	8,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2199 = VST4q32
  { 2200,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2200 = VST4q32Pseudo_UPD
  { 2201,	10,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2201 = VST4q32_UPD
  { 2202,	5,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2202 = VST4q32oddPseudo
  { 2203,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2203 = VST4q32oddPseudo_UPD
  { 2204,	8,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2204 = VST4q8
  { 2205,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2205 = VST4q8Pseudo_UPD
  { 2206,	10,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2206 = VST4q8_UPD
  { 2207,	5,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2207 = VST4q8oddPseudo
  { 2208,	7,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2208 = VST4q8oddPseudo_UPD
  { 2209,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2209 = VST4qAsm_16
  { 2210,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2210 = VST4qAsm_32
  { 2211,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2211 = VST4qAsm_8
  { 2212,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2212 = VST4qWB_fixed_Asm_16
  { 2213,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2213 = VST4qWB_fixed_Asm_32
  { 2214,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #2214 = VST4qWB_fixed_Asm_8
  { 2215,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2215 = VST4qWB_register_Asm_16
  { 2216,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2216 = VST4qWB_register_Asm_32
  { 2217,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #2217 = VST4qWB_register_Asm_8
  { 2218,	5,	1,	517,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2218 = VSTMDDB_UPD
  { 2219,	4,	0,	516,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2219 = VSTMDIA
  { 2220,	5,	1,	517,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2220 = VSTMDIA_UPD
  { 2221,	4,	0,	513,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18004ULL, NULL, NULL, OperandInfo191,0,0 },  // Inst #2221 = VSTMQIA
  { 2222,	5,	1,	517,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2222 = VSTMSDB_UPD
  { 2223,	4,	0,	516,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2223 = VSTMSIA
  { 2224,	5,	1,	517,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2224 = VSTMSIA_UPD
  { 2225,	5,	0,	510,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, NULL, NULL, OperandInfo192,0,0 },  // Inst #2225 = VSTRD
  { 2226,	5,	0,	511,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, NULL, NULL, OperandInfo193,0,0 },  // Inst #2226 = VSTRS
  { 2227,	5,	1,	448,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2227 = VSUBD
  { 2228,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #2228 = VSUBHNv2i32
  { 2229,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #2229 = VSUBHNv4i16
  { 2230,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #2230 = VSUBHNv8i8
  { 2231,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2231 = VSUBLsv2i64
  { 2232,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2232 = VSUBLsv4i32
  { 2233,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2233 = VSUBLsv8i16
  { 2234,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2234 = VSUBLuv2i64
  { 2235,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2235 = VSUBLuv4i32
  { 2236,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2236 = VSUBLuv8i16
  { 2237,	5,	1,	445,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #2237 = VSUBS
  { 2238,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #2238 = VSUBWsv2i64
  { 2239,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #2239 = VSUBWsv4i32
  { 2240,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #2240 = VSUBWsv8i16
  { 2241,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #2241 = VSUBWuv2i64
  { 2242,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #2242 = VSUBWuv4i32
  { 2243,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #2243 = VSUBWuv8i16
  { 2244,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2244 = VSUBfd
  { 2245,	5,	1,	443,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2245 = VSUBfq
  { 2246,	5,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2246 = VSUBv16i8
  { 2247,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2247 = VSUBv1i64
  { 2248,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2248 = VSUBv2i32
  { 2249,	5,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2249 = VSUBv2i64
  { 2250,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2250 = VSUBv4i16
  { 2251,	5,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2251 = VSUBv4i32
  { 2252,	5,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2252 = VSUBv8i16
  { 2253,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2253 = VSUBv8i8
  { 2254,	6,	2,	433,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2254 = VSWPd
  { 2255,	6,	2,	433,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2255 = VSWPq
  { 2256,	5,	1,	425,	4,	0|(1<<MCID_Predicable), 0x11480ULL, NULL, NULL, OperandInfo262,0,0 },  // Inst #2256 = VTBL1
  { 2257,	5,	1,	427,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo263,0,0 },  // Inst #2257 = VTBL2
  { 2258,	5,	1,	429,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo262,0,0 },  // Inst #2258 = VTBL3
  { 2259,	5,	1,	429,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo264,0,0 },  // Inst #2259 = VTBL3Pseudo
  { 2260,	5,	1,	431,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo262,0,0 },  // Inst #2260 = VTBL4
  { 2261,	5,	1,	431,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo264,0,0 },  // Inst #2261 = VTBL4Pseudo
  { 2262,	6,	1,	426,	4,	0|(1<<MCID_Predicable), 0x11480ULL, NULL, NULL, OperandInfo265,0,0 },  // Inst #2262 = VTBX1
  { 2263,	6,	1,	428,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo266,0,0 },  // Inst #2263 = VTBX2
  { 2264,	6,	1,	430,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo265,0,0 },  // Inst #2264 = VTBX3
  { 2265,	6,	1,	430,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo267,0,0 },  // Inst #2265 = VTBX3Pseudo
  { 2266,	6,	1,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo265,0,0 },  // Inst #2266 = VTBX4
  { 2267,	6,	1,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo267,0,0 },  // Inst #2267 = VTBX4Pseudo
  { 2268,	5,	1,	483,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2268 = VTOSHD
  { 2269,	5,	1,	484,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #2269 = VTOSHS
  { 2270,	4,	1,	485,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo144,0,0 },  // Inst #2270 = VTOSIRD
  { 2271,	4,	1,	486,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo132,0,0 },  // Inst #2271 = VTOSIRS
  { 2272,	4,	1,	485,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #2272 = VTOSIZD
  { 2273,	4,	1,	486,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #2273 = VTOSIZS
  { 2274,	5,	1,	483,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2274 = VTOSLD
  { 2275,	5,	1,	484,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #2275 = VTOSLS
  { 2276,	5,	1,	483,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2276 = VTOUHD
  { 2277,	5,	1,	484,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #2277 = VTOUHS
  { 2278,	4,	1,	485,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo144,0,0 },  // Inst #2278 = VTOUIRD
  { 2279,	4,	1,	486,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo132,0,0 },  // Inst #2279 = VTOUIRS
  { 2280,	4,	1,	485,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #2280 = VTOUIZD
  { 2281,	4,	1,	486,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #2281 = VTOUIZS
  { 2282,	5,	1,	483,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2282 = VTOULD
  { 2283,	5,	1,	484,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #2283 = VTOULS
  { 2284,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2284 = VTRNd16
  { 2285,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2285 = VTRNd32
  { 2286,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2286 = VTRNd8
  { 2287,	6,	2,	435,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2287 = VTRNq16
  { 2288,	6,	2,	435,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2288 = VTRNq32
  { 2289,	6,	2,	435,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2289 = VTRNq8
  { 2290,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2290 = VTSTv16i8
  { 2291,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2291 = VTSTv2i32
  { 2292,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2292 = VTSTv4i16
  { 2293,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2293 = VTSTv4i32
  { 2294,	5,	1,	386,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #2294 = VTSTv8i16
  { 2295,	5,	1,	387,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2295 = VTSTv8i8
  { 2296,	5,	1,	189,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2296 = VUHTOD
  { 2297,	5,	1,	190,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #2297 = VUHTOS
  { 2298,	4,	1,	481,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #2298 = VUITOD
  { 2299,	4,	1,	482,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #2299 = VUITOS
  { 2300,	5,	1,	189,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2300 = VULTOD
  { 2301,	5,	1,	190,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #2301 = VULTOS
  { 2302,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2302 = VUZPd16
  { 2303,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2303 = VUZPd8
  { 2304,	6,	2,	436,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2304 = VUZPq16
  { 2305,	6,	2,	436,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2305 = VUZPq32
  { 2306,	6,	2,	436,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2306 = VUZPq8
  { 2307,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2307 = VZIPd16
  { 2308,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2308 = VZIPd8
  { 2309,	6,	2,	436,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2309 = VZIPq16
  { 2310,	6,	2,	436,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2310 = VZIPq32
  { 2311,	6,	2,	436,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2311 = VZIPq8
  { 2312,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2312 = sysLDMDA
  { 2313,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2313 = sysLDMDA_UPD
  { 2314,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2314 = sysLDMDB
  { 2315,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2315 = sysLDMDB_UPD
  { 2316,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2316 = sysLDMIA
  { 2317,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2317 = sysLDMIA_UPD
  { 2318,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2318 = sysLDMIB
  { 2319,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2319 = sysLDMIB_UPD
  { 2320,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2320 = sysSTMDA
  { 2321,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2321 = sysSTMDA_UPD
  { 2322,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2322 = sysSTMDB
  { 2323,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2323 = sysSTMDB_UPD
  { 2324,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2324 = sysSTMIA
  { 2325,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2325 = sysSTMIA_UPD
  { 2326,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2326 = sysSTMIB
  { 2327,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2327 = sysSTMIB_UPD
  { 2328,	2,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo268,0,0 },  // Inst #2328 = t2ABS
  { 2329,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,0 },  // Inst #2329 = t2ADCri
  { 2330,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,0 },  // Inst #2330 = t2ADCrr
  { 2331,	7,	1,	58,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo271,0,0 },  // Inst #2331 = t2ADCrs
  { 2332,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo272,0,0 },  // Inst #2332 = t2ADDSri
  { 2333,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo273,0,0 },  // Inst #2333 = t2ADDSrr
  { 2334,	6,	1,	238,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo274,0,0 },  // Inst #2334 = t2ADDSrs
  { 2335,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo275,0,0 },  // Inst #2335 = t2ADDri
  { 2336,	5,	1,	1,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo276,0,0 },  // Inst #2336 = t2ADDri12
  { 2337,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo277,0,0 },  // Inst #2337 = t2ADDrr
  { 2338,	7,	1,	58,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo278,0,0 },  // Inst #2338 = t2ADDrs
  { 2339,	4,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2339 = t2ADR
  { 2340,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2340 = t2ANDri
  { 2341,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2341 = t2ANDrr
  { 2342,	7,	1,	59,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo271,0,0 },  // Inst #2342 = t2ANDrs
  { 2343,	6,	1,	50,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2343 = t2ASRri
  { 2344,	6,	1,	49,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2344 = t2ASRrr
  { 2345,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2345 = t2B
  { 2346,	5,	1,	297,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo280,0,0 },  // Inst #2346 = t2BFC
  { 2347,	6,	1,	298,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo281,0,0 },  // Inst #2347 = t2BFI
  { 2348,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2348 = t2BICri
  { 2349,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2349 = t2BICrr
  { 2350,	7,	1,	59,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo271,0,0 },  // Inst #2350 = t2BICrs
  { 2351,	4,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo39,0,0 },  // Inst #2351 = t2BR_JT
  { 2352,	3,	0,	15,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo282,0,0 },  // Inst #2352 = t2BXJ
  { 2353,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2353 = t2Bcc
  { 2354,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo43,0,0 },  // Inst #2354 = t2CDP
  { 2355,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo43,0,0 },  // Inst #2355 = t2CDP2
  { 2356,	2,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2356 = t2CLREX
  { 2357,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2357 = t2CLZ
  { 2358,	4,	0,	17,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2358 = t2CMNri
  { 2359,	4,	0,	18,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2359 = t2CMNzrr
  { 2360,	5,	0,	240,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo286,0,0 },  // Inst #2360 = t2CMNzrs
  { 2361,	4,	0,	241,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2361 = t2CMPri
  { 2362,	4,	0,	242,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2362 = t2CMPrr
  { 2363,	5,	0,	243,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo286,0,0 },  // Inst #2363 = t2CMPrs
  { 2364,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #2364 = t2CPS1p
  { 2365,	2,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #2365 = t2CPS2p
  { 2366,	3,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #2366 = t2CPS3p
  { 2367,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo287,0,0 },  // Inst #2367 = t2CRC32B
  { 2368,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo287,0,0 },  // Inst #2368 = t2CRC32CB
  { 2369,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo287,0,0 },  // Inst #2369 = t2CRC32CH
  { 2370,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo287,0,0 },  // Inst #2370 = t2CRC32CW
  { 2371,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo287,0,0 },  // Inst #2371 = t2CRC32H
  { 2372,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo287,0,0 },  // Inst #2372 = t2CRC32W
  { 2373,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2373 = t2DBG
  { 2374,	2,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2374 = t2DCPS1
  { 2375,	2,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2375 = t2DCPS2
  { 2376,	2,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2376 = t2DCPS3
  { 2377,	3,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2377 = t2DMB
  { 2378,	3,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2378 = t2DSB
  { 2379,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2379 = t2EORri
  { 2380,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2380 = t2EORrr
  { 2381,	7,	1,	59,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo271,0,0 },  // Inst #2381 = t2EORrs
  { 2382,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2382 = t2HINT
  { 2383,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2383 = t2ISB
  { 2384,	2,	0,	378,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList10, OperandInfo7,0,0 },  // Inst #2384 = t2IT
  { 2385,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList11, OperandInfo288,0,0 },  // Inst #2385 = t2Int_eh_sjlj_setjmp
  { 2386,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList7, OperandInfo288,0,0 },  // Inst #2386 = t2Int_eh_sjlj_setjmp_nofp
  { 2387,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2387 = t2LDA
  { 2388,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2388 = t2LDAB
  { 2389,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2389 = t2LDAEX
  { 2390,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2390 = t2LDAEXB
  { 2391,	5,	2,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2391 = t2LDAEXD
  { 2392,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2392 = t2LDAEXH
  { 2393,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2393 = t2LDAH
  { 2394,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2394 = t2LDC2L_OFFSET
  { 2395,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2395 = t2LDC2L_OPTION
  { 2396,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2396 = t2LDC2L_POST
  { 2397,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2397 = t2LDC2L_PRE
  { 2398,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2398 = t2LDC2_OFFSET
  { 2399,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2399 = t2LDC2_OPTION
  { 2400,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2400 = t2LDC2_POST
  { 2401,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2401 = t2LDC2_PRE
  { 2402,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2402 = t2LDCL_OFFSET
  { 2403,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2403 = t2LDCL_OPTION
  { 2404,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2404 = t2LDCL_POST
  { 2405,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2405 = t2LDCL_PRE
  { 2406,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2406 = t2LDC_OFFSET
  { 2407,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2407 = t2LDC_OPTION
  { 2408,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2408 = t2LDC_POST
  { 2409,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2409 = t2LDC_PRE
  { 2410,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2410 = t2LDMDB
  { 2411,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2411 = t2LDMDB_UPD
  { 2412,	4,	0,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2412 = t2LDMIA
  { 2413,	5,	1,	355,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2413 = t2LDMIA_RET
  { 2414,	5,	1,	354,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2414 = t2LDMIA_UPD
  { 2415,	5,	1,	346,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2415 = t2LDRBT
  { 2416,	6,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2416 = t2LDRB_POST
  { 2417,	6,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2417 = t2LDRB_PRE
  { 2418,	5,	1,	329,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2418 = t2LDRBi12
  { 2419,	5,	1,	329,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2419 = t2LDRBi8
  { 2420,	4,	1,	329,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2420 = t2LDRBpci
  { 2421,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo284,0,0 },  // Inst #2421 = t2LDRBpcrel
  { 2422,	6,	1,	326,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2422 = t2LDRBs
  { 2423,	7,	3,	352,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo293,0,0 },  // Inst #2423 = t2LDRD_POST
  { 2424,	7,	3,	352,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo293,0,0 },  // Inst #2424 = t2LDRD_PRE
  { 2425,	6,	2,	351,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0xc8fULL, NULL, NULL, OperandInfo294,0,0 },  // Inst #2425 = t2LDRDi8
  { 2426,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo295,0,0 },  // Inst #2426 = t2LDREX
  { 2427,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2427 = t2LDREXB
  { 2428,	5,	2,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2428 = t2LDREXD
  { 2429,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2429 = t2LDREXH
  { 2430,	5,	1,	346,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2430 = t2LDRHT
  { 2431,	6,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2431 = t2LDRH_POST
  { 2432,	6,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2432 = t2LDRH_PRE
  { 2433,	5,	1,	329,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2433 = t2LDRHi12
  { 2434,	5,	1,	329,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2434 = t2LDRHi8
  { 2435,	4,	1,	329,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2435 = t2LDRHpci
  { 2436,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo284,0,0 },  // Inst #2436 = t2LDRHpcrel
  { 2437,	6,	1,	326,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2437 = t2LDRHs
  { 2438,	5,	1,	348,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2438 = t2LDRSBT
  { 2439,	6,	2,	349,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2439 = t2LDRSB_POST
  { 2440,	6,	2,	349,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2440 = t2LDRSB_PRE
  { 2441,	5,	1,	337,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2441 = t2LDRSBi12
  { 2442,	5,	1,	337,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2442 = t2LDRSBi8
  { 2443,	4,	1,	337,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2443 = t2LDRSBpci
  { 2444,	4,	0,	338,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo284,0,0 },  // Inst #2444 = t2LDRSBpcrel
  { 2445,	6,	1,	339,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2445 = t2LDRSBs
  { 2446,	5,	1,	348,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2446 = t2LDRSHT
  { 2447,	6,	2,	349,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2447 = t2LDRSH_POST
  { 2448,	6,	2,	349,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2448 = t2LDRSH_PRE
  { 2449,	5,	1,	337,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2449 = t2LDRSHi12
  { 2450,	5,	1,	337,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2450 = t2LDRSHi8
  { 2451,	4,	1,	337,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2451 = t2LDRSHpci
  { 2452,	4,	0,	338,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo284,0,0 },  // Inst #2452 = t2LDRSHpcrel
  { 2453,	6,	1,	339,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2453 = t2LDRSHs
  { 2454,	5,	1,	347,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2454 = t2LDRT
  { 2455,	6,	2,	345,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2455 = t2LDR_POST
  { 2456,	6,	2,	345,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2456 = t2LDR_PRE
  { 2457,	5,	1,	330,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2457 = t2LDRi12
  { 2458,	5,	1,	330,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2458 = t2LDRi8
  { 2459,	4,	1,	330,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2459 = t2LDRpci
  { 2460,	3,	1,	331,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo296,0,0 },  // Inst #2460 = t2LDRpci_pic
  { 2461,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2461 = t2LDRpcrel
  { 2462,	6,	1,	332,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8dULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2462 = t2LDRs
  { 2463,	4,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo297,0,0 },  // Inst #2463 = t2LEApcrel
  { 2464,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo298,0,0 },  // Inst #2464 = t2LEApcrelJT
  { 2465,	6,	1,	50,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2465 = t2LSLri
  { 2466,	6,	1,	49,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2466 = t2LSLrr
  { 2467,	6,	1,	50,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2467 = t2LSRri
  { 2468,	6,	1,	49,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2468 = t2LSRrr
  { 2469,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo73,0,0 },  // Inst #2469 = t2MCR
  { 2470,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo73,0,0 },  // Inst #2470 = t2MCR2
  { 2471,	7,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2471 = t2MCRR
  { 2472,	7,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2472 = t2MCRR2
  { 2473,	6,	1,	313,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2473 = t2MLA
  { 2474,	6,	1,	313,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2474 = t2MLS
  { 2475,	6,	1,	247,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo301,0,0 },  // Inst #2475 = t2MOVCCasr
  { 2476,	5,	1,	40,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo280,0,0 },  // Inst #2476 = t2MOVCCi
  { 2477,	5,	1,	40,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo280,0,0 },  // Inst #2477 = t2MOVCCi16
  { 2478,	5,	1,	292,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo302,0,0 },  // Inst #2478 = t2MOVCCi32imm
  { 2479,	6,	1,	247,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo301,0,0 },  // Inst #2479 = t2MOVCClsl
  { 2480,	6,	1,	247,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo301,0,0 },  // Inst #2480 = t2MOVCClsr
  { 2481,	5,	1,	43,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, NULL, NULL, OperandInfo303,0,0 },  // Inst #2481 = t2MOVCCr
  { 2482,	6,	1,	247,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo301,0,0 },  // Inst #2482 = t2MOVCCror
  { 2483,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo304,0,0 },  // Inst #2483 = t2MOVSsi
  { 2484,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo305,0,0 },  // Inst #2484 = t2MOVSsr
  { 2485,	5,	1,	41,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo280,0,0 },  // Inst #2485 = t2MOVTi16
  { 2486,	4,	1,	41,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo306,0,0 },  // Inst #2486 = t2MOVTi16_ga_pcrel
  { 2487,	2,	1,	294,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo307,0,0 },  // Inst #2487 = t2MOV_ga_pcrel
  { 2488,	5,	1,	41,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, NULL, NULL, OperandInfo308,0,0 },  // Inst #2488 = t2MOVi
  { 2489,	4,	1,	41,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0xc80ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2489 = t2MOVi16
  { 2490,	3,	1,	295,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo296,0,0 },  // Inst #2490 = t2MOVi16_ga_pcrel
  { 2491,	2,	1,	293,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo307,0,0 },  // Inst #2491 = t2MOVi32imm
  { 2492,	5,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo309,0,0 },  // Inst #2492 = t2MOVr
  { 2493,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo304,0,0 },  // Inst #2493 = t2MOVsi
  { 2494,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo305,0,0 },  // Inst #2494 = t2MOVsr
  { 2495,	4,	1,	50,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo283,0,0 },  // Inst #2495 = t2MOVsra_flag
  { 2496,	4,	1,	50,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo283,0,0 },  // Inst #2496 = t2MOVsrl_flag
  { 2497,	8,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo92,0,0 },  // Inst #2497 = t2MRC
  { 2498,	8,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo92,0,0 },  // Inst #2498 = t2MRC2
  { 2499,	7,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2499 = t2MRRC
  { 2500,	7,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2500 = t2MRRC2
  { 2501,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2501 = t2MRS_AR
  { 2502,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2502 = t2MRS_M
  { 2503,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2503 = t2MRSsys_AR
  { 2504,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2504 = t2MSR_AR
  { 2505,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2505 = t2MSR_M
  { 2506,	5,	1,	310,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2506 = t2MUL
  { 2507,	5,	1,	40,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo280,0,0 },  // Inst #2507 = t2MVNCCi
  { 2508,	5,	1,	52,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, NULL, NULL, OperandInfo308,0,0 },  // Inst #2508 = t2MVNi
  { 2509,	5,	1,	53,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo312,0,0 },  // Inst #2509 = t2MVNr
  { 2510,	6,	1,	249,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2510 = t2MVNs
  { 2511,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2511 = t2ORNri
  { 2512,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2512 = t2ORNrr
  { 2513,	7,	1,	59,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo271,0,0 },  // Inst #2513 = t2ORNrs
  { 2514,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2514 = t2ORRri
  { 2515,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2515 = t2ORRrr
  { 2516,	7,	1,	59,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo271,0,0 },  // Inst #2516 = t2ORRrs
  { 2517,	6,	1,	59,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2517 = t2PKHBT
  { 2518,	6,	1,	59,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2518 = t2PKHTB
  { 2519,	4,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2519 = t2PLDWi12
  { 2520,	4,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2520 = t2PLDWi8
  { 2521,	5,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2521 = t2PLDWs
  { 2522,	4,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2522 = t2PLDi12
  { 2523,	4,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2523 = t2PLDi8
  { 2524,	3,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2524 = t2PLDpci
  { 2525,	5,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2525 = t2PLDs
  { 2526,	4,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2526 = t2PLIi12
  { 2527,	4,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2527 = t2PLIi8
  { 2528,	3,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2528 = t2PLIpci
  { 2529,	5,	0,	60,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2529 = t2PLIs
  { 2530,	5,	1,	300,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2530 = t2QADD
  { 2531,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2531 = t2QADD16
  { 2532,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2532 = t2QADD8
  { 2533,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2533 = t2QASX
  { 2534,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2534 = t2QDADD
  { 2535,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2535 = t2QDSUB
  { 2536,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2536 = t2QSAX
  { 2537,	5,	1,	300,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2537 = t2QSUB
  { 2538,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2538 = t2QSUB16
  { 2539,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2539 = t2QSUB8
  { 2540,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2540 = t2RBIT
  { 2541,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2541 = t2REV
  { 2542,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2542 = t2REV16
  { 2543,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2543 = t2REVSH
  { 2544,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2544 = t2RFEDB
  { 2545,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2545 = t2RFEDBW
  { 2546,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2546 = t2RFEIA
  { 2547,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2547 = t2RFEIAW
  { 2548,	6,	1,	50,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2548 = t2RORri
  { 2549,	6,	1,	49,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2549 = t2RORrr
  { 2550,	5,	1,	50,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, ImplicitList1, NULL, OperandInfo312,0,0 },  // Inst #2550 = t2RRX
  { 2551,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo317,0,0 },  // Inst #2551 = t2RSBSri
  { 2552,	6,	1,	58,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo318,0,0 },  // Inst #2552 = t2RSBSrs
  { 2553,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2553 = t2RSBri
  { 2554,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2554 = t2RSBrr
  { 2555,	7,	1,	250,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo271,0,0 },  // Inst #2555 = t2RSBrs
  { 2556,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2556 = t2SADD16
  { 2557,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2557 = t2SADD8
  { 2558,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2558 = t2SASX
  { 2559,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,0 },  // Inst #2559 = t2SBCri
  { 2560,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,0 },  // Inst #2560 = t2SBCrr
  { 2561,	7,	1,	58,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo271,0,0 },  // Inst #2561 = t2SBCrs
  { 2562,	6,	1,	297,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo319,0,0 },  // Inst #2562 = t2SBFX
  { 2563,	5,	1,	324,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2563 = t2SDIV
  { 2564,	5,	1,	296,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #2564 = t2SEL
  { 2565,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2565 = t2SHADD16
  { 2566,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2566 = t2SHADD8
  { 2567,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2567 = t2SHASX
  { 2568,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2568 = t2SHSAX
  { 2569,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2569 = t2SHSUB16
  { 2570,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2570 = t2SHSUB8
  { 2571,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2571 = t2SMC
  { 2572,	6,	1,	317,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2572 = t2SMLABB
  { 2573,	6,	1,	317,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2573 = t2SMLABT
  { 2574,	6,	1,	320,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2574 = t2SMLAD
  { 2575,	6,	1,	320,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2575 = t2SMLADX
  { 2576,	8,	2,	323,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo320,0,0 },  // Inst #2576 = t2SMLAL
  { 2577,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2577 = t2SMLALBB
  { 2578,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2578 = t2SMLALBT
  { 2579,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2579 = t2SMLALD
  { 2580,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2580 = t2SMLALDX
  { 2581,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2581 = t2SMLALTB
  { 2582,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2582 = t2SMLALTT
  { 2583,	6,	1,	317,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2583 = t2SMLATB
  { 2584,	6,	1,	317,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2584 = t2SMLATT
  { 2585,	6,	1,	317,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2585 = t2SMLAWB
  { 2586,	6,	1,	317,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2586 = t2SMLAWT
  { 2587,	6,	1,	318,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2587 = t2SMLSD
  { 2588,	6,	1,	318,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2588 = t2SMLSDX
  { 2589,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2589 = t2SMLSLD
  { 2590,	6,	2,	323,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2590 = t2SMLSLDX
  { 2591,	6,	1,	313,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2591 = t2SMMLA
  { 2592,	6,	1,	313,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2592 = t2SMMLAR
  { 2593,	6,	1,	313,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2593 = t2SMMLS
  { 2594,	6,	1,	313,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2594 = t2SMMLSR
  { 2595,	5,	1,	310,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2595 = t2SMMUL
  { 2596,	5,	1,	310,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2596 = t2SMMULR
  { 2597,	5,	1,	315,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2597 = t2SMUAD
  { 2598,	5,	1,	315,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2598 = t2SMUADX
  { 2599,	5,	1,	311,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2599 = t2SMULBB
  { 2600,	5,	1,	311,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2600 = t2SMULBT
  { 2601,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2601 = t2SMULL
  { 2602,	5,	1,	311,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2602 = t2SMULTB
  { 2603,	5,	1,	311,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2603 = t2SMULTT
  { 2604,	5,	1,	311,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2604 = t2SMULWB
  { 2605,	5,	1,	311,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2605 = t2SMULWT
  { 2606,	5,	1,	312,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2606 = t2SMUSD
  { 2607,	5,	1,	312,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2607 = t2SMUSDX
  { 2608,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2608 = t2SRSDB
  { 2609,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2609 = t2SRSDB_UPD
  { 2610,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2610 = t2SRSIA
  { 2611,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2611 = t2SRSIA_UPD
  { 2612,	6,	1,	300,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo321,0,0 },  // Inst #2612 = t2SSAT
  { 2613,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo322,0,0 },  // Inst #2613 = t2SSAT16
  { 2614,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2614 = t2SSAX
  { 2615,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2615 = t2SSUB16
  { 2616,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2616 = t2SSUB8
  { 2617,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2617 = t2STC2L_OFFSET
  { 2618,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2618 = t2STC2L_OPTION
  { 2619,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2619 = t2STC2L_POST
  { 2620,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2620 = t2STC2L_PRE
  { 2621,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2621 = t2STC2_OFFSET
  { 2622,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2622 = t2STC2_OPTION
  { 2623,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2623 = t2STC2_POST
  { 2624,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2624 = t2STC2_PRE
  { 2625,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2625 = t2STCL_OFFSET
  { 2626,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2626 = t2STCL_OPTION
  { 2627,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2627 = t2STCL_POST
  { 2628,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2628 = t2STCL_PRE
  { 2629,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2629 = t2STC_OFFSET
  { 2630,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2630 = t2STC_OPTION
  { 2631,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2631 = t2STC_POST
  { 2632,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2632 = t2STC_PRE
  { 2633,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2633 = t2STL
  { 2634,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2634 = t2STLB
  { 2635,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo323,0,0 },  // Inst #2635 = t2STLEX
  { 2636,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo323,0,0 },  // Inst #2636 = t2STLEXB
  { 2637,	6,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo324,0,0 },  // Inst #2637 = t2STLEXD
  { 2638,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo323,0,0 },  // Inst #2638 = t2STLEXH
  { 2639,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2639 = t2STLH
  { 2640,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2640 = t2STMDB
  { 2641,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2641 = t2STMDB_UPD
  { 2642,	4,	0,	374,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2642 = t2STMIA
  { 2643,	5,	1,	375,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2643 = t2STMIA_UPD
  { 2644,	5,	1,	370,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2644 = t2STRBT
  { 2645,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo325,0,0 },  // Inst #2645 = t2STRB_POST
  { 2646,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo325,0,0 },  // Inst #2646 = t2STRB_PRE
  { 2647,	6,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo326,0,0 },  // Inst #2647 = t2STRB_preidx
  { 2648,	5,	0,	363,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2648 = t2STRBi12
  { 2649,	5,	0,	363,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2649 = t2STRBi8
  { 2650,	6,	0,	360,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo327,0,0 },  // Inst #2650 = t2STRBs
  { 2651,	7,	1,	373,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo328,0,0 },  // Inst #2651 = t2STRD_POST
  { 2652,	7,	1,	373,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo328,0,0 },  // Inst #2652 = t2STRD_PRE
  { 2653,	6,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0xc8fULL, NULL, NULL, OperandInfo17,0,0 },  // Inst #2653 = t2STRDi8
  { 2654,	6,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo329,0,0 },  // Inst #2654 = t2STREX
  { 2655,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo323,0,0 },  // Inst #2655 = t2STREXB
  { 2656,	6,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo324,0,0 },  // Inst #2656 = t2STREXD
  { 2657,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo323,0,0 },  // Inst #2657 = t2STREXH
  { 2658,	5,	1,	370,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2658 = t2STRHT
  { 2659,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo325,0,0 },  // Inst #2659 = t2STRH_POST
  { 2660,	6,	1,	369,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo325,0,0 },  // Inst #2660 = t2STRH_PRE
  { 2661,	6,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo326,0,0 },  // Inst #2661 = t2STRH_preidx
  { 2662,	5,	0,	363,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2662 = t2STRHi12
  { 2663,	5,	0,	363,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2663 = t2STRHi8
  { 2664,	6,	0,	360,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo327,0,0 },  // Inst #2664 = t2STRHs
  { 2665,	5,	1,	371,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2665 = t2STRT
  { 2666,	6,	1,	369,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo330,0,0 },  // Inst #2666 = t2STR_POST
  { 2667,	6,	1,	369,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo330,0,0 },  // Inst #2667 = t2STR_PRE
  { 2668,	6,	1,	368,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo326,0,0 },  // Inst #2668 = t2STR_preidx
  { 2669,	5,	0,	364,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2669 = t2STRi12
  { 2670,	5,	0,	364,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2670 = t2STRi8
  { 2671,	6,	0,	362,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2671 = t2STRs
  { 2672,	3,	0,	0,	4,	0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, NULL, ImplicitList12, OperandInfo50,0,0 },  // Inst #2672 = t2SUBS_PC_LR
  { 2673,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo272,0,0 },  // Inst #2673 = t2SUBSri
  { 2674,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo273,0,0 },  // Inst #2674 = t2SUBSrr
  { 2675,	6,	1,	238,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo274,0,0 },  // Inst #2675 = t2SUBSrs
  { 2676,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo275,0,0 },  // Inst #2676 = t2SUBri
  { 2677,	5,	1,	1,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo276,0,0 },  // Inst #2677 = t2SUBri12
  { 2678,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo277,0,0 },  // Inst #2678 = t2SUBrr
  { 2679,	7,	1,	58,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo278,0,0 },  // Inst #2679 = t2SUBrs
  { 2680,	6,	1,	306,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2680 = t2SXTAB
  { 2681,	6,	1,	306,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2681 = t2SXTAB16
  { 2682,	6,	1,	306,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2682 = t2SXTAH
  { 2683,	5,	1,	291,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo317,0,0 },  // Inst #2683 = t2SXTB
  { 2684,	5,	1,	291,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo317,0,0 },  // Inst #2684 = t2SXTB16
  { 2685,	5,	1,	291,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo317,0,0 },  // Inst #2685 = t2SXTH
  { 2686,	4,	0,	14,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2686 = t2TBB
  { 2687,	3,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo41,0,0 },  // Inst #2687 = t2TBB_JT
  { 2688,	4,	0,	14,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2688 = t2TBH
  { 2689,	3,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo41,0,0 },  // Inst #2689 = t2TBH_JT
  { 2690,	4,	0,	255,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2690 = t2TEQri
  { 2691,	4,	0,	256,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2691 = t2TEQrr
  { 2692,	5,	0,	257,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo286,0,0 },  // Inst #2692 = t2TEQrs
  { 2693,	4,	0,	255,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2693 = t2TSTri
  { 2694,	4,	0,	256,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2694 = t2TSTrr
  { 2695,	5,	0,	257,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo286,0,0 },  // Inst #2695 = t2TSTrs
  { 2696,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2696 = t2UADD16
  { 2697,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2697 = t2UADD8
  { 2698,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2698 = t2UASX
  { 2699,	6,	1,	297,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo319,0,0 },  // Inst #2699 = t2UBFX
  { 2700,	5,	1,	324,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2700 = t2UDIV
  { 2701,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2701 = t2UHADD16
  { 2702,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2702 = t2UHADD8
  { 2703,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2703 = t2UHASX
  { 2704,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2704 = t2UHSAX
  { 2705,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2705 = t2UHSUB16
  { 2706,	5,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2706 = t2UHSUB8
  { 2707,	6,	2,	323,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2707 = t2UMAAL
  { 2708,	8,	2,	323,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo320,0,0 },  // Inst #2708 = t2UMLAL
  { 2709,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2709 = t2UMULL
  { 2710,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2710 = t2UQADD16
  { 2711,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2711 = t2UQADD8
  { 2712,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2712 = t2UQASX
  { 2713,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2713 = t2UQSAX
  { 2714,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2714 = t2UQSUB16
  { 2715,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2715 = t2UQSUB8
  { 2716,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2716 = t2USAD8
  { 2717,	6,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2717 = t2USADA8
  { 2718,	6,	1,	300,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo321,0,0 },  // Inst #2718 = t2USAT
  { 2719,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo322,0,0 },  // Inst #2719 = t2USAT16
  { 2720,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2720 = t2USAX
  { 2721,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2721 = t2USUB16
  { 2722,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2722 = t2USUB8
  { 2723,	6,	1,	306,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2723 = t2UXTAB
  { 2724,	6,	1,	306,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2724 = t2UXTAB16
  { 2725,	6,	1,	306,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2725 = t2UXTAH
  { 2726,	5,	1,	291,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo317,0,0 },  // Inst #2726 = t2UXTB
  { 2727,	5,	1,	291,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo317,0,0 },  // Inst #2727 = t2UXTB16
  { 2728,	5,	1,	291,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo317,0,0 },  // Inst #2728 = t2UXTH
  { 2729,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, NULL, OperandInfo332,0,0 },  // Inst #2729 = tADC
  { 2730,	5,	1,	258,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo81,0,0 },  // Inst #2730 = tADDhirr
  { 2731,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo333,0,0 },  // Inst #2731 = tADDi3
  { 2732,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo334,0,0 },  // Inst #2732 = tADDi8
  { 2733,	5,	1,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo335,0,0 },  // Inst #2733 = tADDrSP
  { 2734,	5,	1,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo336,0,0 },  // Inst #2734 = tADDrSPi
  { 2735,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo337,0,0 },  // Inst #2735 = tADDrr
  { 2736,	5,	1,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo338,0,0 },  // Inst #2736 = tADDspi
  { 2737,	5,	1,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo339,0,0 },  // Inst #2737 = tADDspr
  { 2738,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2,0,0 },  // Inst #2738 = tADJCALLSTACKDOWN
  { 2739,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8,0,0 },  // Inst #2739 = tADJCALLSTACKUP
  { 2740,	4,	1,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo340,0,0 },  // Inst #2740 = tADR
  { 2741,	6,	2,	260,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2741 = tAND
  { 2742,	6,	2,	50,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo333,0,0 },  // Inst #2742 = tASRri
  { 2743,	6,	2,	49,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2743 = tASRrr
  { 2744,	3,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2744 = tB
  { 2745,	6,	2,	260,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2745 = tBIC
  { 2746,	1,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #2746 = tBKPT
  { 2747,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo341,0,0 },  // Inst #2747 = tBL
  { 2748,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo341,0,0 },  // Inst #2748 = tBLXi
  { 2749,	3,	0,	12,	2,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo342,0,0 },  // Inst #2749 = tBLXr
  { 2750,	3,	0,	10,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2750 = tBRIND
  { 2751,	3,	0,	14,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo343,0,0 },  // Inst #2751 = tBR_JTr
  { 2752,	3,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2752 = tBX
  { 2753,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo38,0,0 },  // Inst #2753 = tBX_CALL
  { 2754,	2,	0,	10,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2754 = tBX_RET
  { 2755,	3,	0,	10,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo344,0,0 },  // Inst #2755 = tBX_RET_vararg
  { 2756,	3,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2756 = tBcc
  { 2757,	3,	0,	14,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList3, OperandInfo37,0,0 },  // Inst #2757 = tBfar
  { 2758,	2,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2758 = tCBNZ
  { 2759,	2,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2759 = tCBZ
  { 2760,	4,	0,	242,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo346,0,0 },  // Inst #2760 = tCMNz
  { 2761,	4,	0,	242,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #2761 = tCMPhir
  { 2762,	4,	0,	241,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo347,0,0 },  // Inst #2762 = tCMPi8
  { 2763,	4,	0,	242,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo346,0,0 },  // Inst #2763 = tCMPr
  { 2764,	2,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #2764 = tCPS
  { 2765,	6,	2,	260,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2765 = tEOR
  { 2766,	3,	0,	0,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2766 = tHINT
  { 2767,	1,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #2767 = tHLT
  { 2768,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList5, OperandInfo10,0,0 },  // Inst #2768 = tInt_eh_sjlj_longjmp
  { 2769,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList13, OperandInfo288,0,0 },  // Inst #2769 = tInt_eh_sjlj_setjmp
  { 2770,	4,	0,	353,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo348,0,0 },  // Inst #2770 = tLDMIA
  { 2771,	5,	1,	354,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2771 = tLDMIA_UPD
  { 2772,	5,	1,	329,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2772 = tLDRBi
  { 2773,	5,	1,	333,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2773 = tLDRBr
  { 2774,	5,	1,	329,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2774 = tLDRHi
  { 2775,	5,	1,	333,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2775 = tLDRHr
  { 2776,	2,	1,	33,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo351,0,0 },  // Inst #2776 = tLDRLIT_ga_abs
  { 2777,	2,	1,	34,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo351,0,0 },  // Inst #2777 = tLDRLIT_ga_pcrel
  { 2778,	5,	1,	340,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc87ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2778 = tLDRSB
  { 2779,	5,	1,	340,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc88ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2779 = tLDRSH
  { 2780,	5,	1,	330,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2780 = tLDRi
  { 2781,	4,	1,	330,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8aULL, NULL, NULL, OperandInfo340,0,0 },  // Inst #2781 = tLDRpci
  { 2782,	3,	1,	327,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo87,0,0 },  // Inst #2782 = tLDRpci_pic
  { 2783,	5,	1,	334,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2783 = tLDRr
  { 2784,	5,	1,	330,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8aULL, NULL, NULL, OperandInfo352,0,0 },  // Inst #2784 = tLDRspi
  { 2785,	4,	1,	259,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo353,0,0 },  // Inst #2785 = tLEApcrel
  { 2786,	5,	1,	259,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo354,0,0 },  // Inst #2786 = tLEApcrelJT
  { 2787,	6,	2,	50,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo333,0,0 },  // Inst #2787 = tLSLri
  { 2788,	6,	2,	49,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2788 = tLSLrr
  { 2789,	6,	2,	50,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo333,0,0 },  // Inst #2789 = tLSRri
  { 2790,	6,	2,	49,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2790 = tLSRrr
  { 2791,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo355,0,0 },  // Inst #2791 = tMOVCCr_pseudo
  { 2792,	2,	1,	48,	2,	0, 0xc80ULL, NULL, ImplicitList1, OperandInfo288,0,0 },  // Inst #2792 = tMOVSr
  { 2793,	5,	2,	41,	2,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo356,0,0 },  // Inst #2793 = tMOVi8
  { 2794,	4,	1,	48,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #2794 = tMOVr
  { 2795,	6,	2,	51,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo357,0,0 },  // Inst #2795 = tMUL
  { 2796,	5,	2,	53,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo358,0,0 },  // Inst #2796 = tMVN
  { 2797,	6,	2,	260,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2797 = tORR
  { 2798,	3,	1,	258,	2,	0|(1<<MCID_NotDuplicable), 0xc80ULL, NULL, NULL, OperandInfo359,0,0 },  // Inst #2798 = tPICADD
  { 2799,	3,	0,	356,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo360,0,0 },  // Inst #2799 = tPOP
  { 2800,	3,	0,	357,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, NULL, NULL, OperandInfo360,0,0 },  // Inst #2800 = tPOP_RET
  { 2801,	3,	0,	376,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo360,0,0 },  // Inst #2801 = tPUSH
  { 2802,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo346,0,0 },  // Inst #2802 = tREV
  { 2803,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo346,0,0 },  // Inst #2803 = tREV16
  { 2804,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo346,0,0 },  // Inst #2804 = tREVSH
  { 2805,	6,	2,	49,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2805 = tROR
  { 2806,	5,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo358,0,0 },  // Inst #2806 = tRSB
  { 2807,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, NULL, OperandInfo332,0,0 },  // Inst #2807 = tSBC
  { 2808,	1,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,ARM_HasV8Ops,0 },  // Inst #2808 = tSETEND
  { 2809,	5,	1,	375,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo361,0,0 },  // Inst #2809 = tSTMIA_UPD
  { 2810,	5,	0,	363,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2810 = tSTRBi
  { 2811,	5,	0,	359,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2811 = tSTRBr
  { 2812,	5,	0,	363,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2812 = tSTRHi
  { 2813,	5,	0,	359,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2813 = tSTRHr
  { 2814,	5,	0,	364,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2814 = tSTRi
  { 2815,	5,	0,	358,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2815 = tSTRr
  { 2816,	5,	0,	364,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8aULL, NULL, NULL, OperandInfo352,0,0 },  // Inst #2816 = tSTRspi
  { 2817,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo333,0,0 },  // Inst #2817 = tSUBi3
  { 2818,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo334,0,0 },  // Inst #2818 = tSUBi8
  { 2819,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo337,0,0 },  // Inst #2819 = tSUBrr
  { 2820,	5,	1,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo338,0,0 },  // Inst #2820 = tSUBspi
  { 2821,	3,	0,	10,	2,	0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, ImplicitList2, NULL, OperandInfo50,0,0 },  // Inst #2821 = tSVC
  { 2822,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo346,0,0 },  // Inst #2822 = tSXTB
  { 2823,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo346,0,0 },  // Inst #2823 = tSXTH
  { 2824,	3,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo37,0,0 },  // Inst #2824 = tTAILJMPd
  { 2825,	3,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo37,0,0 },  // Inst #2825 = tTAILJMPdND
  { 2826,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo123,0,0 },  // Inst #2826 = tTAILJMPr
  { 2827,	0,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, 0,0,0 },  // Inst #2827 = tTPsoft
  { 2828,	0,	0,	10,	2,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, 0,0,0 },  // Inst #2828 = tTRAP
  { 2829,	4,	0,	263,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, ImplicitList1, OperandInfo346,0,0 },  // Inst #2829 = tTST
  { 2830,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo346,0,0 },  // Inst #2830 = tUXTB
  { 2831,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo346,0,0 },  // Inst #2831 = tUXTH
};


#endif // GET_INSTRINFO_MC_DESC

