/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|*Target Instruction Enum Values                                              *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/

/* Capstone Disassembler Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */


#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM

enum {
  ARM_PHI	= 0,
  ARM_INLINEASM	= 1,
  ARM_PROLOG_LABEL	= 2,
  ARM_EH_LABEL	= 3,
  ARM_GC_LABEL	= 4,
  ARM_KILL	= 5,
  ARM_EXTRACT_SUBREG	= 6,
  ARM_INSERT_SUBREG	= 7,
  ARM_IMPLICIT_DEF	= 8,
  ARM_SUBREG_TO_REG	= 9,
  ARM_COPY_TO_REGCLASS	= 10,
  ARM_DBG_VALUE	= 11,
  ARM_REG_SEQUENCE	= 12,
  ARM_COPY	= 13,
  ARM_BUNDLE	= 14,
  ARM_LIFETIME_START	= 15,
  ARM_LIFETIME_END	= 16,
  ARM_STACKMAP	= 17,
  ARM_PATCHPOINT	= 18,
  ARM_ABS	= 19,
  ARM_ADCri	= 20,
  ARM_ADCrr	= 21,
  ARM_ADCrsi	= 22,
  ARM_ADCrsr	= 23,
  ARM_ADDSri	= 24,
  ARM_ADDSrr	= 25,
  ARM_ADDSrsi	= 26,
  ARM_ADDSrsr	= 27,
  ARM_ADDri	= 28,
  ARM_ADDrr	= 29,
  ARM_ADDrsi	= 30,
  ARM_ADDrsr	= 31,
  ARM_ADJCALLSTACKDOWN	= 32,
  ARM_ADJCALLSTACKUP	= 33,
  ARM_ADR	= 34,
  ARM_AESD	= 35,
  ARM_AESE	= 36,
  ARM_AESIMC	= 37,
  ARM_AESMC	= 38,
  ARM_ANDri	= 39,
  ARM_ANDrr	= 40,
  ARM_ANDrsi	= 41,
  ARM_ANDrsr	= 42,
  ARM_ASRi	= 43,
  ARM_ASRr	= 44,
  ARM_ATOMIC_CMP_SWAP_I16	= 45,
  ARM_ATOMIC_CMP_SWAP_I32	= 46,
  ARM_ATOMIC_CMP_SWAP_I64	= 47,
  ARM_ATOMIC_CMP_SWAP_I8	= 48,
  ARM_ATOMIC_LOAD_ADD_I16	= 49,
  ARM_ATOMIC_LOAD_ADD_I32	= 50,
  ARM_ATOMIC_LOAD_ADD_I64	= 51,
  ARM_ATOMIC_LOAD_ADD_I8	= 52,
  ARM_ATOMIC_LOAD_AND_I16	= 53,
  ARM_ATOMIC_LOAD_AND_I32	= 54,
  ARM_ATOMIC_LOAD_AND_I64	= 55,
  ARM_ATOMIC_LOAD_AND_I8	= 56,
  ARM_ATOMIC_LOAD_I64	= 57,
  ARM_ATOMIC_LOAD_MAX_I16	= 58,
  ARM_ATOMIC_LOAD_MAX_I32	= 59,
  ARM_ATOMIC_LOAD_MAX_I64	= 60,
  ARM_ATOMIC_LOAD_MAX_I8	= 61,
  ARM_ATOMIC_LOAD_MIN_I16	= 62,
  ARM_ATOMIC_LOAD_MIN_I32	= 63,
  ARM_ATOMIC_LOAD_MIN_I64	= 64,
  ARM_ATOMIC_LOAD_MIN_I8	= 65,
  ARM_ATOMIC_LOAD_NAND_I16	= 66,
  ARM_ATOMIC_LOAD_NAND_I32	= 67,
  ARM_ATOMIC_LOAD_NAND_I64	= 68,
  ARM_ATOMIC_LOAD_NAND_I8	= 69,
  ARM_ATOMIC_LOAD_OR_I16	= 70,
  ARM_ATOMIC_LOAD_OR_I32	= 71,
  ARM_ATOMIC_LOAD_OR_I64	= 72,
  ARM_ATOMIC_LOAD_OR_I8	= 73,
  ARM_ATOMIC_LOAD_SUB_I16	= 74,
  ARM_ATOMIC_LOAD_SUB_I32	= 75,
  ARM_ATOMIC_LOAD_SUB_I64	= 76,
  ARM_ATOMIC_LOAD_SUB_I8	= 77,
  ARM_ATOMIC_LOAD_UMAX_I16	= 78,
  ARM_ATOMIC_LOAD_UMAX_I32	= 79,
  ARM_ATOMIC_LOAD_UMAX_I64	= 80,
  ARM_ATOMIC_LOAD_UMAX_I8	= 81,
  ARM_ATOMIC_LOAD_UMIN_I16	= 82,
  ARM_ATOMIC_LOAD_UMIN_I32	= 83,
  ARM_ATOMIC_LOAD_UMIN_I64	= 84,
  ARM_ATOMIC_LOAD_UMIN_I8	= 85,
  ARM_ATOMIC_LOAD_XOR_I16	= 86,
  ARM_ATOMIC_LOAD_XOR_I32	= 87,
  ARM_ATOMIC_LOAD_XOR_I64	= 88,
  ARM_ATOMIC_LOAD_XOR_I8	= 89,
  ARM_ATOMIC_STORE_I64	= 90,
  ARM_ATOMIC_SWAP_I16	= 91,
  ARM_ATOMIC_SWAP_I32	= 92,
  ARM_ATOMIC_SWAP_I64	= 93,
  ARM_ATOMIC_SWAP_I8	= 94,
  ARM_B	= 95,
  ARM_BCCZi64	= 96,
  ARM_BCCi64	= 97,
  ARM_BFC	= 98,
  ARM_BFI	= 99,
  ARM_BICri	= 100,
  ARM_BICrr	= 101,
  ARM_BICrsi	= 102,
  ARM_BICrsr	= 103,
  ARM_BKPT	= 104,
  ARM_BL	= 105,
  ARM_BLX	= 106,
  ARM_BLX_pred	= 107,
  ARM_BLXi	= 108,
  ARM_BL_pred	= 109,
  ARM_BMOVPCB_CALL	= 110,
  ARM_BMOVPCRX_CALL	= 111,
  ARM_BR_JTadd	= 112,
  ARM_BR_JTm	= 113,
  ARM_BR_JTr	= 114,
  ARM_BX	= 115,
  ARM_BXJ	= 116,
  ARM_BX_CALL	= 117,
  ARM_BX_RET	= 118,
  ARM_BX_pred	= 119,
  ARM_Bcc	= 120,
  ARM_CDP	= 121,
  ARM_CDP2	= 122,
  ARM_CLREX	= 123,
  ARM_CLZ	= 124,
  ARM_CMNri	= 125,
  ARM_CMNzrr	= 126,
  ARM_CMNzrsi	= 127,
  ARM_CMNzrsr	= 128,
  ARM_CMPri	= 129,
  ARM_CMPrr	= 130,
  ARM_CMPrsi	= 131,
  ARM_CMPrsr	= 132,
  ARM_CONSTPOOL_ENTRY	= 133,
  ARM_COPY_STRUCT_BYVAL_I32	= 134,
  ARM_CPS1p	= 135,
  ARM_CPS2p	= 136,
  ARM_CPS3p	= 137,
  ARM_CRC32B	= 138,
  ARM_CRC32CB	= 139,
  ARM_CRC32CH	= 140,
  ARM_CRC32CW	= 141,
  ARM_CRC32H	= 142,
  ARM_CRC32W	= 143,
  ARM_DBG	= 144,
  ARM_DMB	= 145,
  ARM_DSB	= 146,
  ARM_EORri	= 147,
  ARM_EORrr	= 148,
  ARM_EORrsi	= 149,
  ARM_EORrsr	= 150,
  ARM_FCONSTD	= 151,
  ARM_FCONSTS	= 152,
  ARM_FLDMXDB_UPD	= 153,
  ARM_FLDMXIA	= 154,
  ARM_FLDMXIA_UPD	= 155,
  ARM_FMSTAT	= 156,
  ARM_FSTMXDB_UPD	= 157,
  ARM_FSTMXIA	= 158,
  ARM_FSTMXIA_UPD	= 159,
  ARM_HINT	= 160,
  ARM_HLT	= 161,
  ARM_ISB	= 162,
  ARM_ITasm	= 163,
  ARM_Int_eh_sjlj_dispatchsetup	= 164,
  ARM_Int_eh_sjlj_longjmp	= 165,
  ARM_Int_eh_sjlj_setjmp	= 166,
  ARM_Int_eh_sjlj_setjmp_nofp	= 167,
  ARM_LDA	= 168,
  ARM_LDAB	= 169,
  ARM_LDAEX	= 170,
  ARM_LDAEXB	= 171,
  ARM_LDAEXD	= 172,
  ARM_LDAEXH	= 173,
  ARM_LDAH	= 174,
  ARM_LDC2L_OFFSET	= 175,
  ARM_LDC2L_OPTION	= 176,
  ARM_LDC2L_POST	= 177,
  ARM_LDC2L_PRE	= 178,
  ARM_LDC2_OFFSET	= 179,
  ARM_LDC2_OPTION	= 180,
  ARM_LDC2_POST	= 181,
  ARM_LDC2_PRE	= 182,
  ARM_LDCL_OFFSET	= 183,
  ARM_LDCL_OPTION	= 184,
  ARM_LDCL_POST	= 185,
  ARM_LDCL_PRE	= 186,
  ARM_LDC_OFFSET	= 187,
  ARM_LDC_OPTION	= 188,
  ARM_LDC_POST	= 189,
  ARM_LDC_PRE	= 190,
  ARM_LDMDA	= 191,
  ARM_LDMDA_UPD	= 192,
  ARM_LDMDB	= 193,
  ARM_LDMDB_UPD	= 194,
  ARM_LDMIA	= 195,
  ARM_LDMIA_RET	= 196,
  ARM_LDMIA_UPD	= 197,
  ARM_LDMIB	= 198,
  ARM_LDMIB_UPD	= 199,
  ARM_LDRBT_POST_IMM	= 200,
  ARM_LDRBT_POST_REG	= 201,
  ARM_LDRB_POST_IMM	= 202,
  ARM_LDRB_POST_REG	= 203,
  ARM_LDRB_PRE_IMM	= 204,
  ARM_LDRB_PRE_REG	= 205,
  ARM_LDRBi12	= 206,
  ARM_LDRBrs	= 207,
  ARM_LDRD	= 208,
  ARM_LDRD_POST	= 209,
  ARM_LDRD_PRE	= 210,
  ARM_LDREX	= 211,
  ARM_LDREXB	= 212,
  ARM_LDREXD	= 213,
  ARM_LDREXH	= 214,
  ARM_LDRH	= 215,
  ARM_LDRHTi	= 216,
  ARM_LDRHTr	= 217,
  ARM_LDRH_POST	= 218,
  ARM_LDRH_PRE	= 219,
  ARM_LDRSB	= 220,
  ARM_LDRSBTi	= 221,
  ARM_LDRSBTr	= 222,
  ARM_LDRSB_POST	= 223,
  ARM_LDRSB_PRE	= 224,
  ARM_LDRSH	= 225,
  ARM_LDRSHTi	= 226,
  ARM_LDRSHTr	= 227,
  ARM_LDRSH_POST	= 228,
  ARM_LDRSH_PRE	= 229,
  ARM_LDRT_POST_IMM	= 230,
  ARM_LDRT_POST_REG	= 231,
  ARM_LDR_POST_IMM	= 232,
  ARM_LDR_POST_REG	= 233,
  ARM_LDR_PRE_IMM	= 234,
  ARM_LDR_PRE_REG	= 235,
  ARM_LDRcp	= 236,
  ARM_LDRi12	= 237,
  ARM_LDRrs	= 238,
  ARM_LEApcrel	= 239,
  ARM_LEApcrelJT	= 240,
  ARM_LSLi	= 241,
  ARM_LSLr	= 242,
  ARM_LSRi	= 243,
  ARM_LSRr	= 244,
  ARM_MCR	= 245,
  ARM_MCR2	= 246,
  ARM_MCRR	= 247,
  ARM_MCRR2	= 248,
  ARM_MLA	= 249,
  ARM_MLAv5	= 250,
  ARM_MLS	= 251,
  ARM_MOVCCi	= 252,
  ARM_MOVCCi16	= 253,
  ARM_MOVCCi32imm	= 254,
  ARM_MOVCCr	= 255,
  ARM_MOVCCsi	= 256,
  ARM_MOVCCsr	= 257,
  ARM_MOVPCLR	= 258,
  ARM_MOVPCRX	= 259,
  ARM_MOVTi16	= 260,
  ARM_MOVTi16_ga_pcrel	= 261,
  ARM_MOV_ga_pcrel	= 262,
  ARM_MOV_ga_pcrel_ldr	= 263,
  ARM_MOVi	= 264,
  ARM_MOVi16	= 265,
  ARM_MOVi16_ga_pcrel	= 266,
  ARM_MOVi32imm	= 267,
  ARM_MOVr	= 268,
  ARM_MOVr_TC	= 269,
  ARM_MOVsi	= 270,
  ARM_MOVsr	= 271,
  ARM_MOVsra_flag	= 272,
  ARM_MOVsrl_flag	= 273,
  ARM_MRC	= 274,
  ARM_MRC2	= 275,
  ARM_MRRC	= 276,
  ARM_MRRC2	= 277,
  ARM_MRS	= 278,
  ARM_MRSsys	= 279,
  ARM_MSR	= 280,
  ARM_MSRi	= 281,
  ARM_MUL	= 282,
  ARM_MULv5	= 283,
  ARM_MVNCCi	= 284,
  ARM_MVNi	= 285,
  ARM_MVNr	= 286,
  ARM_MVNsi	= 287,
  ARM_MVNsr	= 288,
  ARM_ORRri	= 289,
  ARM_ORRrr	= 290,
  ARM_ORRrsi	= 291,
  ARM_ORRrsr	= 292,
  ARM_PICADD	= 293,
  ARM_PICLDR	= 294,
  ARM_PICLDRB	= 295,
  ARM_PICLDRH	= 296,
  ARM_PICLDRSB	= 297,
  ARM_PICLDRSH	= 298,
  ARM_PICSTR	= 299,
  ARM_PICSTRB	= 300,
  ARM_PICSTRH	= 301,
  ARM_PKHBT	= 302,
  ARM_PKHTB	= 303,
  ARM_PLDWi12	= 304,
  ARM_PLDWrs	= 305,
  ARM_PLDi12	= 306,
  ARM_PLDrs	= 307,
  ARM_PLIi12	= 308,
  ARM_PLIrs	= 309,
  ARM_QADD	= 310,
  ARM_QADD16	= 311,
  ARM_QADD8	= 312,
  ARM_QASX	= 313,
  ARM_QDADD	= 314,
  ARM_QDSUB	= 315,
  ARM_QSAX	= 316,
  ARM_QSUB	= 317,
  ARM_QSUB16	= 318,
  ARM_QSUB8	= 319,
  ARM_RBIT	= 320,
  ARM_REV	= 321,
  ARM_REV16	= 322,
  ARM_REVSH	= 323,
  ARM_RFEDA	= 324,
  ARM_RFEDA_UPD	= 325,
  ARM_RFEDB	= 326,
  ARM_RFEDB_UPD	= 327,
  ARM_RFEIA	= 328,
  ARM_RFEIA_UPD	= 329,
  ARM_RFEIB	= 330,
  ARM_RFEIB_UPD	= 331,
  ARM_RORi	= 332,
  ARM_RORr	= 333,
  ARM_RRX	= 334,
  ARM_RRXi	= 335,
  ARM_RSBSri	= 336,
  ARM_RSBSrsi	= 337,
  ARM_RSBSrsr	= 338,
  ARM_RSBri	= 339,
  ARM_RSBrr	= 340,
  ARM_RSBrsi	= 341,
  ARM_RSBrsr	= 342,
  ARM_RSCri	= 343,
  ARM_RSCrr	= 344,
  ARM_RSCrsi	= 345,
  ARM_RSCrsr	= 346,
  ARM_SADD16	= 347,
  ARM_SADD8	= 348,
  ARM_SASX	= 349,
  ARM_SBCri	= 350,
  ARM_SBCrr	= 351,
  ARM_SBCrsi	= 352,
  ARM_SBCrsr	= 353,
  ARM_SBFX	= 354,
  ARM_SDIV	= 355,
  ARM_SEL	= 356,
  ARM_SETEND	= 357,
  ARM_SHA1C	= 358,
  ARM_SHA1H	= 359,
  ARM_SHA1M	= 360,
  ARM_SHA1P	= 361,
  ARM_SHA1SU0	= 362,
  ARM_SHA1SU1	= 363,
  ARM_SHA256H	= 364,
  ARM_SHA256H2	= 365,
  ARM_SHA256SU0	= 366,
  ARM_SHA256SU1	= 367,
  ARM_SHADD16	= 368,
  ARM_SHADD8	= 369,
  ARM_SHASX	= 370,
  ARM_SHSAX	= 371,
  ARM_SHSUB16	= 372,
  ARM_SHSUB8	= 373,
  ARM_SMC	= 374,
  ARM_SMLABB	= 375,
  ARM_SMLABT	= 376,
  ARM_SMLAD	= 377,
  ARM_SMLADX	= 378,
  ARM_SMLAL	= 379,
  ARM_SMLALBB	= 380,
  ARM_SMLALBT	= 381,
  ARM_SMLALD	= 382,
  ARM_SMLALDX	= 383,
  ARM_SMLALTB	= 384,
  ARM_SMLALTT	= 385,
  ARM_SMLALv5	= 386,
  ARM_SMLATB	= 387,
  ARM_SMLATT	= 388,
  ARM_SMLAWB	= 389,
  ARM_SMLAWT	= 390,
  ARM_SMLSD	= 391,
  ARM_SMLSDX	= 392,
  ARM_SMLSLD	= 393,
  ARM_SMLSLDX	= 394,
  ARM_SMMLA	= 395,
  ARM_SMMLAR	= 396,
  ARM_SMMLS	= 397,
  ARM_SMMLSR	= 398,
  ARM_SMMUL	= 399,
  ARM_SMMULR	= 400,
  ARM_SMUAD	= 401,
  ARM_SMUADX	= 402,
  ARM_SMULBB	= 403,
  ARM_SMULBT	= 404,
  ARM_SMULL	= 405,
  ARM_SMULLv5	= 406,
  ARM_SMULTB	= 407,
  ARM_SMULTT	= 408,
  ARM_SMULWB	= 409,
  ARM_SMULWT	= 410,
  ARM_SMUSD	= 411,
  ARM_SMUSDX	= 412,
  ARM_SRSDA	= 413,
  ARM_SRSDA_UPD	= 414,
  ARM_SRSDB	= 415,
  ARM_SRSDB_UPD	= 416,
  ARM_SRSIA	= 417,
  ARM_SRSIA_UPD	= 418,
  ARM_SRSIB	= 419,
  ARM_SRSIB_UPD	= 420,
  ARM_SSAT	= 421,
  ARM_SSAT16	= 422,
  ARM_SSAX	= 423,
  ARM_SSUB16	= 424,
  ARM_SSUB8	= 425,
  ARM_STC2L_OFFSET	= 426,
  ARM_STC2L_OPTION	= 427,
  ARM_STC2L_POST	= 428,
  ARM_STC2L_PRE	= 429,
  ARM_STC2_OFFSET	= 430,
  ARM_STC2_OPTION	= 431,
  ARM_STC2_POST	= 432,
  ARM_STC2_PRE	= 433,
  ARM_STCL_OFFSET	= 434,
  ARM_STCL_OPTION	= 435,
  ARM_STCL_POST	= 436,
  ARM_STCL_PRE	= 437,
  ARM_STC_OFFSET	= 438,
  ARM_STC_OPTION	= 439,
  ARM_STC_POST	= 440,
  ARM_STC_PRE	= 441,
  ARM_STL	= 442,
  ARM_STLB	= 443,
  ARM_STLEX	= 444,
  ARM_STLEXB	= 445,
  ARM_STLEXD	= 446,
  ARM_STLEXH	= 447,
  ARM_STLH	= 448,
  ARM_STMDA	= 449,
  ARM_STMDA_UPD	= 450,
  ARM_STMDB	= 451,
  ARM_STMDB_UPD	= 452,
  ARM_STMIA	= 453,
  ARM_STMIA_UPD	= 454,
  ARM_STMIB	= 455,
  ARM_STMIB_UPD	= 456,
  ARM_STRBT_POST_IMM	= 457,
  ARM_STRBT_POST_REG	= 458,
  ARM_STRB_POST_IMM	= 459,
  ARM_STRB_POST_REG	= 460,
  ARM_STRB_PRE_IMM	= 461,
  ARM_STRB_PRE_REG	= 462,
  ARM_STRBi12	= 463,
  ARM_STRBi_preidx	= 464,
  ARM_STRBr_preidx	= 465,
  ARM_STRBrs	= 466,
  ARM_STRD	= 467,
  ARM_STRD_POST	= 468,
  ARM_STRD_PRE	= 469,
  ARM_STREX	= 470,
  ARM_STREXB	= 471,
  ARM_STREXD	= 472,
  ARM_STREXH	= 473,
  ARM_STRH	= 474,
  ARM_STRHTi	= 475,
  ARM_STRHTr	= 476,
  ARM_STRH_POST	= 477,
  ARM_STRH_PRE	= 478,
  ARM_STRH_preidx	= 479,
  ARM_STRT_POST_IMM	= 480,
  ARM_STRT_POST_REG	= 481,
  ARM_STR_POST_IMM	= 482,
  ARM_STR_POST_REG	= 483,
  ARM_STR_PRE_IMM	= 484,
  ARM_STR_PRE_REG	= 485,
  ARM_STRi12	= 486,
  ARM_STRi_preidx	= 487,
  ARM_STRr_preidx	= 488,
  ARM_STRrs	= 489,
  ARM_SUBS_PC_LR	= 490,
  ARM_SUBSri	= 491,
  ARM_SUBSrr	= 492,
  ARM_SUBSrsi	= 493,
  ARM_SUBSrsr	= 494,
  ARM_SUBri	= 495,
  ARM_SUBrr	= 496,
  ARM_SUBrsi	= 497,
  ARM_SUBrsr	= 498,
  ARM_SVC	= 499,
  ARM_SWP	= 500,
  ARM_SWPB	= 501,
  ARM_SXTAB	= 502,
  ARM_SXTAB16	= 503,
  ARM_SXTAH	= 504,
  ARM_SXTB	= 505,
  ARM_SXTB16	= 506,
  ARM_SXTH	= 507,
  ARM_TAILJMPd	= 508,
  ARM_TAILJMPr	= 509,
  ARM_TCRETURNdi	= 510,
  ARM_TCRETURNri	= 511,
  ARM_TEQri	= 512,
  ARM_TEQrr	= 513,
  ARM_TEQrsi	= 514,
  ARM_TEQrsr	= 515,
  ARM_TPsoft	= 516,
  ARM_TRAP	= 517,
  ARM_TRAPNaCl	= 518,
  ARM_TSTri	= 519,
  ARM_TSTrr	= 520,
  ARM_TSTrsi	= 521,
  ARM_TSTrsr	= 522,
  ARM_UADD16	= 523,
  ARM_UADD8	= 524,
  ARM_UASX	= 525,
  ARM_UBFX	= 526,
  ARM_UDIV	= 527,
  ARM_UHADD16	= 528,
  ARM_UHADD8	= 529,
  ARM_UHASX	= 530,
  ARM_UHSAX	= 531,
  ARM_UHSUB16	= 532,
  ARM_UHSUB8	= 533,
  ARM_UMAAL	= 534,
  ARM_UMAALv5	= 535,
  ARM_UMLAL	= 536,
  ARM_UMLALv5	= 537,
  ARM_UMULL	= 538,
  ARM_UMULLv5	= 539,
  ARM_UQADD16	= 540,
  ARM_UQADD8	= 541,
  ARM_UQASX	= 542,
  ARM_UQSAX	= 543,
  ARM_UQSUB16	= 544,
  ARM_UQSUB8	= 545,
  ARM_USAD8	= 546,
  ARM_USADA8	= 547,
  ARM_USAT	= 548,
  ARM_USAT16	= 549,
  ARM_USAX	= 550,
  ARM_USUB16	= 551,
  ARM_USUB8	= 552,
  ARM_UXTAB	= 553,
  ARM_UXTAB16	= 554,
  ARM_UXTAH	= 555,
  ARM_UXTB	= 556,
  ARM_UXTB16	= 557,
  ARM_UXTH	= 558,
  ARM_VABALsv2i64	= 559,
  ARM_VABALsv4i32	= 560,
  ARM_VABALsv8i16	= 561,
  ARM_VABALuv2i64	= 562,
  ARM_VABALuv4i32	= 563,
  ARM_VABALuv8i16	= 564,
  ARM_VABAsv16i8	= 565,
  ARM_VABAsv2i32	= 566,
  ARM_VABAsv4i16	= 567,
  ARM_VABAsv4i32	= 568,
  ARM_VABAsv8i16	= 569,
  ARM_VABAsv8i8	= 570,
  ARM_VABAuv16i8	= 571,
  ARM_VABAuv2i32	= 572,
  ARM_VABAuv4i16	= 573,
  ARM_VABAuv4i32	= 574,
  ARM_VABAuv8i16	= 575,
  ARM_VABAuv8i8	= 576,
  ARM_VABDLsv2i64	= 577,
  ARM_VABDLsv4i32	= 578,
  ARM_VABDLsv8i16	= 579,
  ARM_VABDLuv2i64	= 580,
  ARM_VABDLuv4i32	= 581,
  ARM_VABDLuv8i16	= 582,
  ARM_VABDfd	= 583,
  ARM_VABDfq	= 584,
  ARM_VABDsv16i8	= 585,
  ARM_VABDsv2i32	= 586,
  ARM_VABDsv4i16	= 587,
  ARM_VABDsv4i32	= 588,
  ARM_VABDsv8i16	= 589,
  ARM_VABDsv8i8	= 590,
  ARM_VABDuv16i8	= 591,
  ARM_VABDuv2i32	= 592,
  ARM_VABDuv4i16	= 593,
  ARM_VABDuv4i32	= 594,
  ARM_VABDuv8i16	= 595,
  ARM_VABDuv8i8	= 596,
  ARM_VABSD	= 597,
  ARM_VABSS	= 598,
  ARM_VABSfd	= 599,
  ARM_VABSfq	= 600,
  ARM_VABSv16i8	= 601,
  ARM_VABSv2i32	= 602,
  ARM_VABSv4i16	= 603,
  ARM_VABSv4i32	= 604,
  ARM_VABSv8i16	= 605,
  ARM_VABSv8i8	= 606,
  ARM_VACGEd	= 607,
  ARM_VACGEq	= 608,
  ARM_VACGTd	= 609,
  ARM_VACGTq	= 610,
  ARM_VADDD	= 611,
  ARM_VADDHNv2i32	= 612,
  ARM_VADDHNv4i16	= 613,
  ARM_VADDHNv8i8	= 614,
  ARM_VADDLsv2i64	= 615,
  ARM_VADDLsv4i32	= 616,
  ARM_VADDLsv8i16	= 617,
  ARM_VADDLuv2i64	= 618,
  ARM_VADDLuv4i32	= 619,
  ARM_VADDLuv8i16	= 620,
  ARM_VADDS	= 621,
  ARM_VADDWsv2i64	= 622,
  ARM_VADDWsv4i32	= 623,
  ARM_VADDWsv8i16	= 624,
  ARM_VADDWuv2i64	= 625,
  ARM_VADDWuv4i32	= 626,
  ARM_VADDWuv8i16	= 627,
  ARM_VADDfd	= 628,
  ARM_VADDfq	= 629,
  ARM_VADDv16i8	= 630,
  ARM_VADDv1i64	= 631,
  ARM_VADDv2i32	= 632,
  ARM_VADDv2i64	= 633,
  ARM_VADDv4i16	= 634,
  ARM_VADDv4i32	= 635,
  ARM_VADDv8i16	= 636,
  ARM_VADDv8i8	= 637,
  ARM_VANDd	= 638,
  ARM_VANDq	= 639,
  ARM_VBICd	= 640,
  ARM_VBICiv2i32	= 641,
  ARM_VBICiv4i16	= 642,
  ARM_VBICiv4i32	= 643,
  ARM_VBICiv8i16	= 644,
  ARM_VBICq	= 645,
  ARM_VBIFd	= 646,
  ARM_VBIFq	= 647,
  ARM_VBITd	= 648,
  ARM_VBITq	= 649,
  ARM_VBSLd	= 650,
  ARM_VBSLq	= 651,
  ARM_VCEQfd	= 652,
  ARM_VCEQfq	= 653,
  ARM_VCEQv16i8	= 654,
  ARM_VCEQv2i32	= 655,
  ARM_VCEQv4i16	= 656,
  ARM_VCEQv4i32	= 657,
  ARM_VCEQv8i16	= 658,
  ARM_VCEQv8i8	= 659,
  ARM_VCEQzv16i8	= 660,
  ARM_VCEQzv2f32	= 661,
  ARM_VCEQzv2i32	= 662,
  ARM_VCEQzv4f32	= 663,
  ARM_VCEQzv4i16	= 664,
  ARM_VCEQzv4i32	= 665,
  ARM_VCEQzv8i16	= 666,
  ARM_VCEQzv8i8	= 667,
  ARM_VCGEfd	= 668,
  ARM_VCGEfq	= 669,
  ARM_VCGEsv16i8	= 670,
  ARM_VCGEsv2i32	= 671,
  ARM_VCGEsv4i16	= 672,
  ARM_VCGEsv4i32	= 673,
  ARM_VCGEsv8i16	= 674,
  ARM_VCGEsv8i8	= 675,
  ARM_VCGEuv16i8	= 676,
  ARM_VCGEuv2i32	= 677,
  ARM_VCGEuv4i16	= 678,
  ARM_VCGEuv4i32	= 679,
  ARM_VCGEuv8i16	= 680,
  ARM_VCGEuv8i8	= 681,
  ARM_VCGEzv16i8	= 682,
  ARM_VCGEzv2f32	= 683,
  ARM_VCGEzv2i32	= 684,
  ARM_VCGEzv4f32	= 685,
  ARM_VCGEzv4i16	= 686,
  ARM_VCGEzv4i32	= 687,
  ARM_VCGEzv8i16	= 688,
  ARM_VCGEzv8i8	= 689,
  ARM_VCGTfd	= 690,
  ARM_VCGTfq	= 691,
  ARM_VCGTsv16i8	= 692,
  ARM_VCGTsv2i32	= 693,
  ARM_VCGTsv4i16	= 694,
  ARM_VCGTsv4i32	= 695,
  ARM_VCGTsv8i16	= 696,
  ARM_VCGTsv8i8	= 697,
  ARM_VCGTuv16i8	= 698,
  ARM_VCGTuv2i32	= 699,
  ARM_VCGTuv4i16	= 700,
  ARM_VCGTuv4i32	= 701,
  ARM_VCGTuv8i16	= 702,
  ARM_VCGTuv8i8	= 703,
  ARM_VCGTzv16i8	= 704,
  ARM_VCGTzv2f32	= 705,
  ARM_VCGTzv2i32	= 706,
  ARM_VCGTzv4f32	= 707,
  ARM_VCGTzv4i16	= 708,
  ARM_VCGTzv4i32	= 709,
  ARM_VCGTzv8i16	= 710,
  ARM_VCGTzv8i8	= 711,
  ARM_VCLEzv16i8	= 712,
  ARM_VCLEzv2f32	= 713,
  ARM_VCLEzv2i32	= 714,
  ARM_VCLEzv4f32	= 715,
  ARM_VCLEzv4i16	= 716,
  ARM_VCLEzv4i32	= 717,
  ARM_VCLEzv8i16	= 718,
  ARM_VCLEzv8i8	= 719,
  ARM_VCLSv16i8	= 720,
  ARM_VCLSv2i32	= 721,
  ARM_VCLSv4i16	= 722,
  ARM_VCLSv4i32	= 723,
  ARM_VCLSv8i16	= 724,
  ARM_VCLSv8i8	= 725,
  ARM_VCLTzv16i8	= 726,
  ARM_VCLTzv2f32	= 727,
  ARM_VCLTzv2i32	= 728,
  ARM_VCLTzv4f32	= 729,
  ARM_VCLTzv4i16	= 730,
  ARM_VCLTzv4i32	= 731,
  ARM_VCLTzv8i16	= 732,
  ARM_VCLTzv8i8	= 733,
  ARM_VCLZv16i8	= 734,
  ARM_VCLZv2i32	= 735,
  ARM_VCLZv4i16	= 736,
  ARM_VCLZv4i32	= 737,
  ARM_VCLZv8i16	= 738,
  ARM_VCLZv8i8	= 739,
  ARM_VCMPD	= 740,
  ARM_VCMPED	= 741,
  ARM_VCMPES	= 742,
  ARM_VCMPEZD	= 743,
  ARM_VCMPEZS	= 744,
  ARM_VCMPS	= 745,
  ARM_VCMPZD	= 746,
  ARM_VCMPZS	= 747,
  ARM_VCNTd	= 748,
  ARM_VCNTq	= 749,
  ARM_VCVTANSD	= 750,
  ARM_VCVTANSQ	= 751,
  ARM_VCVTANUD	= 752,
  ARM_VCVTANUQ	= 753,
  ARM_VCVTASD	= 754,
  ARM_VCVTASS	= 755,
  ARM_VCVTAUD	= 756,
  ARM_VCVTAUS	= 757,
  ARM_VCVTBDH	= 758,
  ARM_VCVTBHD	= 759,
  ARM_VCVTBHS	= 760,
  ARM_VCVTBSH	= 761,
  ARM_VCVTDS	= 762,
  ARM_VCVTMNSD	= 763,
  ARM_VCVTMNSQ	= 764,
  ARM_VCVTMNUD	= 765,
  ARM_VCVTMNUQ	= 766,
  ARM_VCVTMSD	= 767,
  ARM_VCVTMSS	= 768,
  ARM_VCVTMUD	= 769,
  ARM_VCVTMUS	= 770,
  ARM_VCVTNNSD	= 771,
  ARM_VCVTNNSQ	= 772,
  ARM_VCVTNNUD	= 773,
  ARM_VCVTNNUQ	= 774,
  ARM_VCVTNSD	= 775,
  ARM_VCVTNSS	= 776,
  ARM_VCVTNUD	= 777,
  ARM_VCVTNUS	= 778,
  ARM_VCVTPNSD	= 779,
  ARM_VCVTPNSQ	= 780,
  ARM_VCVTPNUD	= 781,
  ARM_VCVTPNUQ	= 782,
  ARM_VCVTPSD	= 783,
  ARM_VCVTPSS	= 784,
  ARM_VCVTPUD	= 785,
  ARM_VCVTPUS	= 786,
  ARM_VCVTSD	= 787,
  ARM_VCVTTDH	= 788,
  ARM_VCVTTHD	= 789,
  ARM_VCVTTHS	= 790,
  ARM_VCVTTSH	= 791,
  ARM_VCVTf2h	= 792,
  ARM_VCVTf2sd	= 793,
  ARM_VCVTf2sq	= 794,
  ARM_VCVTf2ud	= 795,
  ARM_VCVTf2uq	= 796,
  ARM_VCVTf2xsd	= 797,
  ARM_VCVTf2xsq	= 798,
  ARM_VCVTf2xud	= 799,
  ARM_VCVTf2xuq	= 800,
  ARM_VCVTh2f	= 801,
  ARM_VCVTs2fd	= 802,
  ARM_VCVTs2fq	= 803,
  ARM_VCVTu2fd	= 804,
  ARM_VCVTu2fq	= 805,
  ARM_VCVTxs2fd	= 806,
  ARM_VCVTxs2fq	= 807,
  ARM_VCVTxu2fd	= 808,
  ARM_VCVTxu2fq	= 809,
  ARM_VDIVD	= 810,
  ARM_VDIVS	= 811,
  ARM_VDUP16d	= 812,
  ARM_VDUP16q	= 813,
  ARM_VDUP32d	= 814,
  ARM_VDUP32q	= 815,
  ARM_VDUP8d	= 816,
  ARM_VDUP8q	= 817,
  ARM_VDUPLN16d	= 818,
  ARM_VDUPLN16q	= 819,
  ARM_VDUPLN32d	= 820,
  ARM_VDUPLN32q	= 821,
  ARM_VDUPLN8d	= 822,
  ARM_VDUPLN8q	= 823,
  ARM_VDUPfdf	= 824,
  ARM_VDUPfqf	= 825,
  ARM_VEORd	= 826,
  ARM_VEORq	= 827,
  ARM_VEXTd16	= 828,
  ARM_VEXTd32	= 829,
  ARM_VEXTd8	= 830,
  ARM_VEXTq16	= 831,
  ARM_VEXTq32	= 832,
  ARM_VEXTq64	= 833,
  ARM_VEXTq8	= 834,
  ARM_VFMAD	= 835,
  ARM_VFMAS	= 836,
  ARM_VFMAfd	= 837,
  ARM_VFMAfq	= 838,
  ARM_VFMSD	= 839,
  ARM_VFMSS	= 840,
  ARM_VFMSfd	= 841,
  ARM_VFMSfq	= 842,
  ARM_VFNMAD	= 843,
  ARM_VFNMAS	= 844,
  ARM_VFNMSD	= 845,
  ARM_VFNMSS	= 846,
  ARM_VGETLNi32	= 847,
  ARM_VGETLNs16	= 848,
  ARM_VGETLNs8	= 849,
  ARM_VGETLNu16	= 850,
  ARM_VGETLNu8	= 851,
  ARM_VHADDsv16i8	= 852,
  ARM_VHADDsv2i32	= 853,
  ARM_VHADDsv4i16	= 854,
  ARM_VHADDsv4i32	= 855,
  ARM_VHADDsv8i16	= 856,
  ARM_VHADDsv8i8	= 857,
  ARM_VHADDuv16i8	= 858,
  ARM_VHADDuv2i32	= 859,
  ARM_VHADDuv4i16	= 860,
  ARM_VHADDuv4i32	= 861,
  ARM_VHADDuv8i16	= 862,
  ARM_VHADDuv8i8	= 863,
  ARM_VHSUBsv16i8	= 864,
  ARM_VHSUBsv2i32	= 865,
  ARM_VHSUBsv4i16	= 866,
  ARM_VHSUBsv4i32	= 867,
  ARM_VHSUBsv8i16	= 868,
  ARM_VHSUBsv8i8	= 869,
  ARM_VHSUBuv16i8	= 870,
  ARM_VHSUBuv2i32	= 871,
  ARM_VHSUBuv4i16	= 872,
  ARM_VHSUBuv4i32	= 873,
  ARM_VHSUBuv8i16	= 874,
  ARM_VHSUBuv8i8	= 875,
  ARM_VLD1DUPd16	= 876,
  ARM_VLD1DUPd16wb_fixed	= 877,
  ARM_VLD1DUPd16wb_register	= 878,
  ARM_VLD1DUPd32	= 879,
  ARM_VLD1DUPd32wb_fixed	= 880,
  ARM_VLD1DUPd32wb_register	= 881,
  ARM_VLD1DUPd8	= 882,
  ARM_VLD1DUPd8wb_fixed	= 883,
  ARM_VLD1DUPd8wb_register	= 884,
  ARM_VLD1DUPq16	= 885,
  ARM_VLD1DUPq16wb_fixed	= 886,
  ARM_VLD1DUPq16wb_register	= 887,
  ARM_VLD1DUPq32	= 888,
  ARM_VLD1DUPq32wb_fixed	= 889,
  ARM_VLD1DUPq32wb_register	= 890,
  ARM_VLD1DUPq8	= 891,
  ARM_VLD1DUPq8wb_fixed	= 892,
  ARM_VLD1DUPq8wb_register	= 893,
  ARM_VLD1LNd16	= 894,
  ARM_VLD1LNd16_UPD	= 895,
  ARM_VLD1LNd32	= 896,
  ARM_VLD1LNd32_UPD	= 897,
  ARM_VLD1LNd8	= 898,
  ARM_VLD1LNd8_UPD	= 899,
  ARM_VLD1LNdAsm_16	= 900,
  ARM_VLD1LNdAsm_32	= 901,
  ARM_VLD1LNdAsm_8	= 902,
  ARM_VLD1LNdWB_fixed_Asm_16	= 903,
  ARM_VLD1LNdWB_fixed_Asm_32	= 904,
  ARM_VLD1LNdWB_fixed_Asm_8	= 905,
  ARM_VLD1LNdWB_register_Asm_16	= 906,
  ARM_VLD1LNdWB_register_Asm_32	= 907,
  ARM_VLD1LNdWB_register_Asm_8	= 908,
  ARM_VLD1LNq16Pseudo	= 909,
  ARM_VLD1LNq16Pseudo_UPD	= 910,
  ARM_VLD1LNq32Pseudo	= 911,
  ARM_VLD1LNq32Pseudo_UPD	= 912,
  ARM_VLD1LNq8Pseudo	= 913,
  ARM_VLD1LNq8Pseudo_UPD	= 914,
  ARM_VLD1d16	= 915,
  ARM_VLD1d16Q	= 916,
  ARM_VLD1d16Qwb_fixed	= 917,
  ARM_VLD1d16Qwb_register	= 918,
  ARM_VLD1d16T	= 919,
  ARM_VLD1d16Twb_fixed	= 920,
  ARM_VLD1d16Twb_register	= 921,
  ARM_VLD1d16wb_fixed	= 922,
  ARM_VLD1d16wb_register	= 923,
  ARM_VLD1d32	= 924,
  ARM_VLD1d32Q	= 925,
  ARM_VLD1d32Qwb_fixed	= 926,
  ARM_VLD1d32Qwb_register	= 927,
  ARM_VLD1d32T	= 928,
  ARM_VLD1d32Twb_fixed	= 929,
  ARM_VLD1d32Twb_register	= 930,
  ARM_VLD1d32wb_fixed	= 931,
  ARM_VLD1d32wb_register	= 932,
  ARM_VLD1d64	= 933,
  ARM_VLD1d64Q	= 934,
  ARM_VLD1d64QPseudo	= 935,
  ARM_VLD1d64Qwb_fixed	= 936,
  ARM_VLD1d64Qwb_register	= 937,
  ARM_VLD1d64T	= 938,
  ARM_VLD1d64TPseudo	= 939,
  ARM_VLD1d64Twb_fixed	= 940,
  ARM_VLD1d64Twb_register	= 941,
  ARM_VLD1d64wb_fixed	= 942,
  ARM_VLD1d64wb_register	= 943,
  ARM_VLD1d8	= 944,
  ARM_VLD1d8Q	= 945,
  ARM_VLD1d8Qwb_fixed	= 946,
  ARM_VLD1d8Qwb_register	= 947,
  ARM_VLD1d8T	= 948,
  ARM_VLD1d8Twb_fixed	= 949,
  ARM_VLD1d8Twb_register	= 950,
  ARM_VLD1d8wb_fixed	= 951,
  ARM_VLD1d8wb_register	= 952,
  ARM_VLD1q16	= 953,
  ARM_VLD1q16wb_fixed	= 954,
  ARM_VLD1q16wb_register	= 955,
  ARM_VLD1q32	= 956,
  ARM_VLD1q32wb_fixed	= 957,
  ARM_VLD1q32wb_register	= 958,
  ARM_VLD1q64	= 959,
  ARM_VLD1q64wb_fixed	= 960,
  ARM_VLD1q64wb_register	= 961,
  ARM_VLD1q8	= 962,
  ARM_VLD1q8wb_fixed	= 963,
  ARM_VLD1q8wb_register	= 964,
  ARM_VLD2DUPd16	= 965,
  ARM_VLD2DUPd16wb_fixed	= 966,
  ARM_VLD2DUPd16wb_register	= 967,
  ARM_VLD2DUPd16x2	= 968,
  ARM_VLD2DUPd16x2wb_fixed	= 969,
  ARM_VLD2DUPd16x2wb_register	= 970,
  ARM_VLD2DUPd32	= 971,
  ARM_VLD2DUPd32wb_fixed	= 972,
  ARM_VLD2DUPd32wb_register	= 973,
  ARM_VLD2DUPd32x2	= 974,
  ARM_VLD2DUPd32x2wb_fixed	= 975,
  ARM_VLD2DUPd32x2wb_register	= 976,
  ARM_VLD2DUPd8	= 977,
  ARM_VLD2DUPd8wb_fixed	= 978,
  ARM_VLD2DUPd8wb_register	= 979,
  ARM_VLD2DUPd8x2	= 980,
  ARM_VLD2DUPd8x2wb_fixed	= 981,
  ARM_VLD2DUPd8x2wb_register	= 982,
  ARM_VLD2LNd16	= 983,
  ARM_VLD2LNd16Pseudo	= 984,
  ARM_VLD2LNd16Pseudo_UPD	= 985,
  ARM_VLD2LNd16_UPD	= 986,
  ARM_VLD2LNd32	= 987,
  ARM_VLD2LNd32Pseudo	= 988,
  ARM_VLD2LNd32Pseudo_UPD	= 989,
  ARM_VLD2LNd32_UPD	= 990,
  ARM_VLD2LNd8	= 991,
  ARM_VLD2LNd8Pseudo	= 992,
  ARM_VLD2LNd8Pseudo_UPD	= 993,
  ARM_VLD2LNd8_UPD	= 994,
  ARM_VLD2LNdAsm_16	= 995,
  ARM_VLD2LNdAsm_32	= 996,
  ARM_VLD2LNdAsm_8	= 997,
  ARM_VLD2LNdWB_fixed_Asm_16	= 998,
  ARM_VLD2LNdWB_fixed_Asm_32	= 999,
  ARM_VLD2LNdWB_fixed_Asm_8	= 1000,
  ARM_VLD2LNdWB_register_Asm_16	= 1001,
  ARM_VLD2LNdWB_register_Asm_32	= 1002,
  ARM_VLD2LNdWB_register_Asm_8	= 1003,
  ARM_VLD2LNq16	= 1004,
  ARM_VLD2LNq16Pseudo	= 1005,
  ARM_VLD2LNq16Pseudo_UPD	= 1006,
  ARM_VLD2LNq16_UPD	= 1007,
  ARM_VLD2LNq32	= 1008,
  ARM_VLD2LNq32Pseudo	= 1009,
  ARM_VLD2LNq32Pseudo_UPD	= 1010,
  ARM_VLD2LNq32_UPD	= 1011,
  ARM_VLD2LNqAsm_16	= 1012,
  ARM_VLD2LNqAsm_32	= 1013,
  ARM_VLD2LNqWB_fixed_Asm_16	= 1014,
  ARM_VLD2LNqWB_fixed_Asm_32	= 1015,
  ARM_VLD2LNqWB_register_Asm_16	= 1016,
  ARM_VLD2LNqWB_register_Asm_32	= 1017,
  ARM_VLD2b16	= 1018,
  ARM_VLD2b16wb_fixed	= 1019,
  ARM_VLD2b16wb_register	= 1020,
  ARM_VLD2b32	= 1021,
  ARM_VLD2b32wb_fixed	= 1022,
  ARM_VLD2b32wb_register	= 1023,
  ARM_VLD2b8	= 1024,
  ARM_VLD2b8wb_fixed	= 1025,
  ARM_VLD2b8wb_register	= 1026,
  ARM_VLD2d16	= 1027,
  ARM_VLD2d16wb_fixed	= 1028,
  ARM_VLD2d16wb_register	= 1029,
  ARM_VLD2d32	= 1030,
  ARM_VLD2d32wb_fixed	= 1031,
  ARM_VLD2d32wb_register	= 1032,
  ARM_VLD2d8	= 1033,
  ARM_VLD2d8wb_fixed	= 1034,
  ARM_VLD2d8wb_register	= 1035,
  ARM_VLD2q16	= 1036,
  ARM_VLD2q16Pseudo	= 1037,
  ARM_VLD2q16PseudoWB_fixed	= 1038,
  ARM_VLD2q16PseudoWB_register	= 1039,
  ARM_VLD2q16wb_fixed	= 1040,
  ARM_VLD2q16wb_register	= 1041,
  ARM_VLD2q32	= 1042,
  ARM_VLD2q32Pseudo	= 1043,
  ARM_VLD2q32PseudoWB_fixed	= 1044,
  ARM_VLD2q32PseudoWB_register	= 1045,
  ARM_VLD2q32wb_fixed	= 1046,
  ARM_VLD2q32wb_register	= 1047,
  ARM_VLD2q8	= 1048,
  ARM_VLD2q8Pseudo	= 1049,
  ARM_VLD2q8PseudoWB_fixed	= 1050,
  ARM_VLD2q8PseudoWB_register	= 1051,
  ARM_VLD2q8wb_fixed	= 1052,
  ARM_VLD2q8wb_register	= 1053,
  ARM_VLD3DUPd16	= 1054,
  ARM_VLD3DUPd16Pseudo	= 1055,
  ARM_VLD3DUPd16Pseudo_UPD	= 1056,
  ARM_VLD3DUPd16_UPD	= 1057,
  ARM_VLD3DUPd32	= 1058,
  ARM_VLD3DUPd32Pseudo	= 1059,
  ARM_VLD3DUPd32Pseudo_UPD	= 1060,
  ARM_VLD3DUPd32_UPD	= 1061,
  ARM_VLD3DUPd8	= 1062,
  ARM_VLD3DUPd8Pseudo	= 1063,
  ARM_VLD3DUPd8Pseudo_UPD	= 1064,
  ARM_VLD3DUPd8_UPD	= 1065,
  ARM_VLD3DUPdAsm_16	= 1066,
  ARM_VLD3DUPdAsm_32	= 1067,
  ARM_VLD3DUPdAsm_8	= 1068,
  ARM_VLD3DUPdWB_fixed_Asm_16	= 1069,
  ARM_VLD3DUPdWB_fixed_Asm_32	= 1070,
  ARM_VLD3DUPdWB_fixed_Asm_8	= 1071,
  ARM_VLD3DUPdWB_register_Asm_16	= 1072,
  ARM_VLD3DUPdWB_register_Asm_32	= 1073,
  ARM_VLD3DUPdWB_register_Asm_8	= 1074,
  ARM_VLD3DUPq16	= 1075,
  ARM_VLD3DUPq16_UPD	= 1076,
  ARM_VLD3DUPq32	= 1077,
  ARM_VLD3DUPq32_UPD	= 1078,
  ARM_VLD3DUPq8	= 1079,
  ARM_VLD3DUPq8_UPD	= 1080,
  ARM_VLD3DUPqAsm_16	= 1081,
  ARM_VLD3DUPqAsm_32	= 1082,
  ARM_VLD3DUPqAsm_8	= 1083,
  ARM_VLD3DUPqWB_fixed_Asm_16	= 1084,
  ARM_VLD3DUPqWB_fixed_Asm_32	= 1085,
  ARM_VLD3DUPqWB_fixed_Asm_8	= 1086,
  ARM_VLD3DUPqWB_register_Asm_16	= 1087,
  ARM_VLD3DUPqWB_register_Asm_32	= 1088,
  ARM_VLD3DUPqWB_register_Asm_8	= 1089,
  ARM_VLD3LNd16	= 1090,
  ARM_VLD3LNd16Pseudo	= 1091,
  ARM_VLD3LNd16Pseudo_UPD	= 1092,
  ARM_VLD3LNd16_UPD	= 1093,
  ARM_VLD3LNd32	= 1094,
  ARM_VLD3LNd32Pseudo	= 1095,
  ARM_VLD3LNd32Pseudo_UPD	= 1096,
  ARM_VLD3LNd32_UPD	= 1097,
  ARM_VLD3LNd8	= 1098,
  ARM_VLD3LNd8Pseudo	= 1099,
  ARM_VLD3LNd8Pseudo_UPD	= 1100,
  ARM_VLD3LNd8_UPD	= 1101,
  ARM_VLD3LNdAsm_16	= 1102,
  ARM_VLD3LNdAsm_32	= 1103,
  ARM_VLD3LNdAsm_8	= 1104,
  ARM_VLD3LNdWB_fixed_Asm_16	= 1105,
  ARM_VLD3LNdWB_fixed_Asm_32	= 1106,
  ARM_VLD3LNdWB_fixed_Asm_8	= 1107,
  ARM_VLD3LNdWB_register_Asm_16	= 1108,
  ARM_VLD3LNdWB_register_Asm_32	= 1109,
  ARM_VLD3LNdWB_register_Asm_8	= 1110,
  ARM_VLD3LNq16	= 1111,
  ARM_VLD3LNq16Pseudo	= 1112,
  ARM_VLD3LNq16Pseudo_UPD	= 1113,
  ARM_VLD3LNq16_UPD	= 1114,
  ARM_VLD3LNq32	= 1115,
  ARM_VLD3LNq32Pseudo	= 1116,
  ARM_VLD3LNq32Pseudo_UPD	= 1117,
  ARM_VLD3LNq32_UPD	= 1118,
  ARM_VLD3LNqAsm_16	= 1119,
  ARM_VLD3LNqAsm_32	= 1120,
  ARM_VLD3LNqWB_fixed_Asm_16	= 1121,
  ARM_VLD3LNqWB_fixed_Asm_32	= 1122,
  ARM_VLD3LNqWB_register_Asm_16	= 1123,
  ARM_VLD3LNqWB_register_Asm_32	= 1124,
  ARM_VLD3d16	= 1125,
  ARM_VLD3d16Pseudo	= 1126,
  ARM_VLD3d16Pseudo_UPD	= 1127,
  ARM_VLD3d16_UPD	= 1128,
  ARM_VLD3d32	= 1129,
  ARM_VLD3d32Pseudo	= 1130,
  ARM_VLD3d32Pseudo_UPD	= 1131,
  ARM_VLD3d32_UPD	= 1132,
  ARM_VLD3d8	= 1133,
  ARM_VLD3d8Pseudo	= 1134,
  ARM_VLD3d8Pseudo_UPD	= 1135,
  ARM_VLD3d8_UPD	= 1136,
  ARM_VLD3dAsm_16	= 1137,
  ARM_VLD3dAsm_32	= 1138,
  ARM_VLD3dAsm_8	= 1139,
  ARM_VLD3dWB_fixed_Asm_16	= 1140,
  ARM_VLD3dWB_fixed_Asm_32	= 1141,
  ARM_VLD3dWB_fixed_Asm_8	= 1142,
  ARM_VLD3dWB_register_Asm_16	= 1143,
  ARM_VLD3dWB_register_Asm_32	= 1144,
  ARM_VLD3dWB_register_Asm_8	= 1145,
  ARM_VLD3q16	= 1146,
  ARM_VLD3q16Pseudo_UPD	= 1147,
  ARM_VLD3q16_UPD	= 1148,
  ARM_VLD3q16oddPseudo	= 1149,
  ARM_VLD3q16oddPseudo_UPD	= 1150,
  ARM_VLD3q32	= 1151,
  ARM_VLD3q32Pseudo_UPD	= 1152,
  ARM_VLD3q32_UPD	= 1153,
  ARM_VLD3q32oddPseudo	= 1154,
  ARM_VLD3q32oddPseudo_UPD	= 1155,
  ARM_VLD3q8	= 1156,
  ARM_VLD3q8Pseudo_UPD	= 1157,
  ARM_VLD3q8_UPD	= 1158,
  ARM_VLD3q8oddPseudo	= 1159,
  ARM_VLD3q8oddPseudo_UPD	= 1160,
  ARM_VLD3qAsm_16	= 1161,
  ARM_VLD3qAsm_32	= 1162,
  ARM_VLD3qAsm_8	= 1163,
  ARM_VLD3qWB_fixed_Asm_16	= 1164,
  ARM_VLD3qWB_fixed_Asm_32	= 1165,
  ARM_VLD3qWB_fixed_Asm_8	= 1166,
  ARM_VLD3qWB_register_Asm_16	= 1167,
  ARM_VLD3qWB_register_Asm_32	= 1168,
  ARM_VLD3qWB_register_Asm_8	= 1169,
  ARM_VLD4DUPd16	= 1170,
  ARM_VLD4DUPd16Pseudo	= 1171,
  ARM_VLD4DUPd16Pseudo_UPD	= 1172,
  ARM_VLD4DUPd16_UPD	= 1173,
  ARM_VLD4DUPd32	= 1174,
  ARM_VLD4DUPd32Pseudo	= 1175,
  ARM_VLD4DUPd32Pseudo_UPD	= 1176,
  ARM_VLD4DUPd32_UPD	= 1177,
  ARM_VLD4DUPd8	= 1178,
  ARM_VLD4DUPd8Pseudo	= 1179,
  ARM_VLD4DUPd8Pseudo_UPD	= 1180,
  ARM_VLD4DUPd8_UPD	= 1181,
  ARM_VLD4DUPdAsm_16	= 1182,
  ARM_VLD4DUPdAsm_32	= 1183,
  ARM_VLD4DUPdAsm_8	= 1184,
  ARM_VLD4DUPdWB_fixed_Asm_16	= 1185,
  ARM_VLD4DUPdWB_fixed_Asm_32	= 1186,
  ARM_VLD4DUPdWB_fixed_Asm_8	= 1187,
  ARM_VLD4DUPdWB_register_Asm_16	= 1188,
  ARM_VLD4DUPdWB_register_Asm_32	= 1189,
  ARM_VLD4DUPdWB_register_Asm_8	= 1190,
  ARM_VLD4DUPq16	= 1191,
  ARM_VLD4DUPq16_UPD	= 1192,
  ARM_VLD4DUPq32	= 1193,
  ARM_VLD4DUPq32_UPD	= 1194,
  ARM_VLD4DUPq8	= 1195,
  ARM_VLD4DUPq8_UPD	= 1196,
  ARM_VLD4DUPqAsm_16	= 1197,
  ARM_VLD4DUPqAsm_32	= 1198,
  ARM_VLD4DUPqAsm_8	= 1199,
  ARM_VLD4DUPqWB_fixed_Asm_16	= 1200,
  ARM_VLD4DUPqWB_fixed_Asm_32	= 1201,
  ARM_VLD4DUPqWB_fixed_Asm_8	= 1202,
  ARM_VLD4DUPqWB_register_Asm_16	= 1203,
  ARM_VLD4DUPqWB_register_Asm_32	= 1204,
  ARM_VLD4DUPqWB_register_Asm_8	= 1205,
  ARM_VLD4LNd16	= 1206,
  ARM_VLD4LNd16Pseudo	= 1207,
  ARM_VLD4LNd16Pseudo_UPD	= 1208,
  ARM_VLD4LNd16_UPD	= 1209,
  ARM_VLD4LNd32	= 1210,
  ARM_VLD4LNd32Pseudo	= 1211,
  ARM_VLD4LNd32Pseudo_UPD	= 1212,
  ARM_VLD4LNd32_UPD	= 1213,
  ARM_VLD4LNd8	= 1214,
  ARM_VLD4LNd8Pseudo	= 1215,
  ARM_VLD4LNd8Pseudo_UPD	= 1216,
  ARM_VLD4LNd8_UPD	= 1217,
  ARM_VLD4LNdAsm_16	= 1218,
  ARM_VLD4LNdAsm_32	= 1219,
  ARM_VLD4LNdAsm_8	= 1220,
  ARM_VLD4LNdWB_fixed_Asm_16	= 1221,
  ARM_VLD4LNdWB_fixed_Asm_32	= 1222,
  ARM_VLD4LNdWB_fixed_Asm_8	= 1223,
  ARM_VLD4LNdWB_register_Asm_16	= 1224,
  ARM_VLD4LNdWB_register_Asm_32	= 1225,
  ARM_VLD4LNdWB_register_Asm_8	= 1226,
  ARM_VLD4LNq16	= 1227,
  ARM_VLD4LNq16Pseudo	= 1228,
  ARM_VLD4LNq16Pseudo_UPD	= 1229,
  ARM_VLD4LNq16_UPD	= 1230,
  ARM_VLD4LNq32	= 1231,
  ARM_VLD4LNq32Pseudo	= 1232,
  ARM_VLD4LNq32Pseudo_UPD	= 1233,
  ARM_VLD4LNq32_UPD	= 1234,
  ARM_VLD4LNqAsm_16	= 1235,
  ARM_VLD4LNqAsm_32	= 1236,
  ARM_VLD4LNqWB_fixed_Asm_16	= 1237,
  ARM_VLD4LNqWB_fixed_Asm_32	= 1238,
  ARM_VLD4LNqWB_register_Asm_16	= 1239,
  ARM_VLD4LNqWB_register_Asm_32	= 1240,
  ARM_VLD4d16	= 1241,
  ARM_VLD4d16Pseudo	= 1242,
  ARM_VLD4d16Pseudo_UPD	= 1243,
  ARM_VLD4d16_UPD	= 1244,
  ARM_VLD4d32	= 1245,
  ARM_VLD4d32Pseudo	= 1246,
  ARM_VLD4d32Pseudo_UPD	= 1247,
  ARM_VLD4d32_UPD	= 1248,
  ARM_VLD4d8	= 1249,
  ARM_VLD4d8Pseudo	= 1250,
  ARM_VLD4d8Pseudo_UPD	= 1251,
  ARM_VLD4d8_UPD	= 1252,
  ARM_VLD4dAsm_16	= 1253,
  ARM_VLD4dAsm_32	= 1254,
  ARM_VLD4dAsm_8	= 1255,
  ARM_VLD4dWB_fixed_Asm_16	= 1256,
  ARM_VLD4dWB_fixed_Asm_32	= 1257,
  ARM_VLD4dWB_fixed_Asm_8	= 1258,
  ARM_VLD4dWB_register_Asm_16	= 1259,
  ARM_VLD4dWB_register_Asm_32	= 1260,
  ARM_VLD4dWB_register_Asm_8	= 1261,
  ARM_VLD4q16	= 1262,
  ARM_VLD4q16Pseudo_UPD	= 1263,
  ARM_VLD4q16_UPD	= 1264,
  ARM_VLD4q16oddPseudo	= 1265,
  ARM_VLD4q16oddPseudo_UPD	= 1266,
  ARM_VLD4q32	= 1267,
  ARM_VLD4q32Pseudo_UPD	= 1268,
  ARM_VLD4q32_UPD	= 1269,
  ARM_VLD4q32oddPseudo	= 1270,
  ARM_VLD4q32oddPseudo_UPD	= 1271,
  ARM_VLD4q8	= 1272,
  ARM_VLD4q8Pseudo_UPD	= 1273,
  ARM_VLD4q8_UPD	= 1274,
  ARM_VLD4q8oddPseudo	= 1275,
  ARM_VLD4q8oddPseudo_UPD	= 1276,
  ARM_VLD4qAsm_16	= 1277,
  ARM_VLD4qAsm_32	= 1278,
  ARM_VLD4qAsm_8	= 1279,
  ARM_VLD4qWB_fixed_Asm_16	= 1280,
  ARM_VLD4qWB_fixed_Asm_32	= 1281,
  ARM_VLD4qWB_fixed_Asm_8	= 1282,
  ARM_VLD4qWB_register_Asm_16	= 1283,
  ARM_VLD4qWB_register_Asm_32	= 1284,
  ARM_VLD4qWB_register_Asm_8	= 1285,
  ARM_VLDMDDB_UPD	= 1286,
  ARM_VLDMDIA	= 1287,
  ARM_VLDMDIA_UPD	= 1288,
  ARM_VLDMQIA	= 1289,
  ARM_VLDMSDB_UPD	= 1290,
  ARM_VLDMSIA	= 1291,
  ARM_VLDMSIA_UPD	= 1292,
  ARM_VLDRD	= 1293,
  ARM_VLDRS	= 1294,
  ARM_VMAXNMD	= 1295,
  ARM_VMAXNMND	= 1296,
  ARM_VMAXNMNQ	= 1297,
  ARM_VMAXNMS	= 1298,
  ARM_VMAXfd	= 1299,
  ARM_VMAXfq	= 1300,
  ARM_VMAXsv16i8	= 1301,
  ARM_VMAXsv2i32	= 1302,
  ARM_VMAXsv4i16	= 1303,
  ARM_VMAXsv4i32	= 1304,
  ARM_VMAXsv8i16	= 1305,
  ARM_VMAXsv8i8	= 1306,
  ARM_VMAXuv16i8	= 1307,
  ARM_VMAXuv2i32	= 1308,
  ARM_VMAXuv4i16	= 1309,
  ARM_VMAXuv4i32	= 1310,
  ARM_VMAXuv8i16	= 1311,
  ARM_VMAXuv8i8	= 1312,
  ARM_VMINNMD	= 1313,
  ARM_VMINNMND	= 1314,
  ARM_VMINNMNQ	= 1315,
  ARM_VMINNMS	= 1316,
  ARM_VMINfd	= 1317,
  ARM_VMINfq	= 1318,
  ARM_VMINsv16i8	= 1319,
  ARM_VMINsv2i32	= 1320,
  ARM_VMINsv4i16	= 1321,
  ARM_VMINsv4i32	= 1322,
  ARM_VMINsv8i16	= 1323,
  ARM_VMINsv8i8	= 1324,
  ARM_VMINuv16i8	= 1325,
  ARM_VMINuv2i32	= 1326,
  ARM_VMINuv4i16	= 1327,
  ARM_VMINuv4i32	= 1328,
  ARM_VMINuv8i16	= 1329,
  ARM_VMINuv8i8	= 1330,
  ARM_VMLAD	= 1331,
  ARM_VMLALslsv2i32	= 1332,
  ARM_VMLALslsv4i16	= 1333,
  ARM_VMLALsluv2i32	= 1334,
  ARM_VMLALsluv4i16	= 1335,
  ARM_VMLALsv2i64	= 1336,
  ARM_VMLALsv4i32	= 1337,
  ARM_VMLALsv8i16	= 1338,
  ARM_VMLALuv2i64	= 1339,
  ARM_VMLALuv4i32	= 1340,
  ARM_VMLALuv8i16	= 1341,
  ARM_VMLAS	= 1342,
  ARM_VMLAfd	= 1343,
  ARM_VMLAfq	= 1344,
  ARM_VMLAslfd	= 1345,
  ARM_VMLAslfq	= 1346,
  ARM_VMLAslv2i32	= 1347,
  ARM_VMLAslv4i16	= 1348,
  ARM_VMLAslv4i32	= 1349,
  ARM_VMLAslv8i16	= 1350,
  ARM_VMLAv16i8	= 1351,
  ARM_VMLAv2i32	= 1352,
  ARM_VMLAv4i16	= 1353,
  ARM_VMLAv4i32	= 1354,
  ARM_VMLAv8i16	= 1355,
  ARM_VMLAv8i8	= 1356,
  ARM_VMLSD	= 1357,
  ARM_VMLSLslsv2i32	= 1358,
  ARM_VMLSLslsv4i16	= 1359,
  ARM_VMLSLsluv2i32	= 1360,
  ARM_VMLSLsluv4i16	= 1361,
  ARM_VMLSLsv2i64	= 1362,
  ARM_VMLSLsv4i32	= 1363,
  ARM_VMLSLsv8i16	= 1364,
  ARM_VMLSLuv2i64	= 1365,
  ARM_VMLSLuv4i32	= 1366,
  ARM_VMLSLuv8i16	= 1367,
  ARM_VMLSS	= 1368,
  ARM_VMLSfd	= 1369,
  ARM_VMLSfq	= 1370,
  ARM_VMLSslfd	= 1371,
  ARM_VMLSslfq	= 1372,
  ARM_VMLSslv2i32	= 1373,
  ARM_VMLSslv4i16	= 1374,
  ARM_VMLSslv4i32	= 1375,
  ARM_VMLSslv8i16	= 1376,
  ARM_VMLSv16i8	= 1377,
  ARM_VMLSv2i32	= 1378,
  ARM_VMLSv4i16	= 1379,
  ARM_VMLSv4i32	= 1380,
  ARM_VMLSv8i16	= 1381,
  ARM_VMLSv8i8	= 1382,
  ARM_VMOVD	= 1383,
  ARM_VMOVDRR	= 1384,
  ARM_VMOVDcc	= 1385,
  ARM_VMOVLsv2i64	= 1386,
  ARM_VMOVLsv4i32	= 1387,
  ARM_VMOVLsv8i16	= 1388,
  ARM_VMOVLuv2i64	= 1389,
  ARM_VMOVLuv4i32	= 1390,
  ARM_VMOVLuv8i16	= 1391,
  ARM_VMOVNv2i32	= 1392,
  ARM_VMOVNv4i16	= 1393,
  ARM_VMOVNv8i8	= 1394,
  ARM_VMOVRRD	= 1395,
  ARM_VMOVRRS	= 1396,
  ARM_VMOVRS	= 1397,
  ARM_VMOVS	= 1398,
  ARM_VMOVSR	= 1399,
  ARM_VMOVSRR	= 1400,
  ARM_VMOVScc	= 1401,
  ARM_VMOVv16i8	= 1402,
  ARM_VMOVv1i64	= 1403,
  ARM_VMOVv2f32	= 1404,
  ARM_VMOVv2i32	= 1405,
  ARM_VMOVv2i64	= 1406,
  ARM_VMOVv4f32	= 1407,
  ARM_VMOVv4i16	= 1408,
  ARM_VMOVv4i32	= 1409,
  ARM_VMOVv8i16	= 1410,
  ARM_VMOVv8i8	= 1411,
  ARM_VMRS	= 1412,
  ARM_VMRS_FPEXC	= 1413,
  ARM_VMRS_FPINST	= 1414,
  ARM_VMRS_FPINST2	= 1415,
  ARM_VMRS_FPSID	= 1416,
  ARM_VMRS_MVFR0	= 1417,
  ARM_VMRS_MVFR1	= 1418,
  ARM_VMRS_MVFR2	= 1419,
  ARM_VMSR	= 1420,
  ARM_VMSR_FPEXC	= 1421,
  ARM_VMSR_FPINST	= 1422,
  ARM_VMSR_FPINST2	= 1423,
  ARM_VMSR_FPSID	= 1424,
  ARM_VMULD	= 1425,
  ARM_VMULLp64	= 1426,
  ARM_VMULLp8	= 1427,
  ARM_VMULLslsv2i32	= 1428,
  ARM_VMULLslsv4i16	= 1429,
  ARM_VMULLsluv2i32	= 1430,
  ARM_VMULLsluv4i16	= 1431,
  ARM_VMULLsv2i64	= 1432,
  ARM_VMULLsv4i32	= 1433,
  ARM_VMULLsv8i16	= 1434,
  ARM_VMULLuv2i64	= 1435,
  ARM_VMULLuv4i32	= 1436,
  ARM_VMULLuv8i16	= 1437,
  ARM_VMULS	= 1438,
  ARM_VMULfd	= 1439,
  ARM_VMULfq	= 1440,
  ARM_VMULpd	= 1441,
  ARM_VMULpq	= 1442,
  ARM_VMULslfd	= 1443,
  ARM_VMULslfq	= 1444,
  ARM_VMULslv2i32	= 1445,
  ARM_VMULslv4i16	= 1446,
  ARM_VMULslv4i32	= 1447,
  ARM_VMULslv8i16	= 1448,
  ARM_VMULv16i8	= 1449,
  ARM_VMULv2i32	= 1450,
  ARM_VMULv4i16	= 1451,
  ARM_VMULv4i32	= 1452,
  ARM_VMULv8i16	= 1453,
  ARM_VMULv8i8	= 1454,
  ARM_VMVNd	= 1455,
  ARM_VMVNq	= 1456,
  ARM_VMVNv2i32	= 1457,
  ARM_VMVNv4i16	= 1458,
  ARM_VMVNv4i32	= 1459,
  ARM_VMVNv8i16	= 1460,
  ARM_VNEGD	= 1461,
  ARM_VNEGS	= 1462,
  ARM_VNEGf32q	= 1463,
  ARM_VNEGfd	= 1464,
  ARM_VNEGs16d	= 1465,
  ARM_VNEGs16q	= 1466,
  ARM_VNEGs32d	= 1467,
  ARM_VNEGs32q	= 1468,
  ARM_VNEGs8d	= 1469,
  ARM_VNEGs8q	= 1470,
  ARM_VNMLAD	= 1471,
  ARM_VNMLAS	= 1472,
  ARM_VNMLSD	= 1473,
  ARM_VNMLSS	= 1474,
  ARM_VNMULD	= 1475,
  ARM_VNMULS	= 1476,
  ARM_VORNd	= 1477,
  ARM_VORNq	= 1478,
  ARM_VORRd	= 1479,
  ARM_VORRiv2i32	= 1480,
  ARM_VORRiv4i16	= 1481,
  ARM_VORRiv4i32	= 1482,
  ARM_VORRiv8i16	= 1483,
  ARM_VORRq	= 1484,
  ARM_VPADALsv16i8	= 1485,
  ARM_VPADALsv2i32	= 1486,
  ARM_VPADALsv4i16	= 1487,
  ARM_VPADALsv4i32	= 1488,
  ARM_VPADALsv8i16	= 1489,
  ARM_VPADALsv8i8	= 1490,
  ARM_VPADALuv16i8	= 1491,
  ARM_VPADALuv2i32	= 1492,
  ARM_VPADALuv4i16	= 1493,
  ARM_VPADALuv4i32	= 1494,
  ARM_VPADALuv8i16	= 1495,
  ARM_VPADALuv8i8	= 1496,
  ARM_VPADDLsv16i8	= 1497,
  ARM_VPADDLsv2i32	= 1498,
  ARM_VPADDLsv4i16	= 1499,
  ARM_VPADDLsv4i32	= 1500,
  ARM_VPADDLsv8i16	= 1501,
  ARM_VPADDLsv8i8	= 1502,
  ARM_VPADDLuv16i8	= 1503,
  ARM_VPADDLuv2i32	= 1504,
  ARM_VPADDLuv4i16	= 1505,
  ARM_VPADDLuv4i32	= 1506,
  ARM_VPADDLuv8i16	= 1507,
  ARM_VPADDLuv8i8	= 1508,
  ARM_VPADDf	= 1509,
  ARM_VPADDi16	= 1510,
  ARM_VPADDi32	= 1511,
  ARM_VPADDi8	= 1512,
  ARM_VPMAXf	= 1513,
  ARM_VPMAXs16	= 1514,
  ARM_VPMAXs32	= 1515,
  ARM_VPMAXs8	= 1516,
  ARM_VPMAXu16	= 1517,
  ARM_VPMAXu32	= 1518,
  ARM_VPMAXu8	= 1519,
  ARM_VPMINf	= 1520,
  ARM_VPMINs16	= 1521,
  ARM_VPMINs32	= 1522,
  ARM_VPMINs8	= 1523,
  ARM_VPMINu16	= 1524,
  ARM_VPMINu32	= 1525,
  ARM_VPMINu8	= 1526,
  ARM_VQABSv16i8	= 1527,
  ARM_VQABSv2i32	= 1528,
  ARM_VQABSv4i16	= 1529,
  ARM_VQABSv4i32	= 1530,
  ARM_VQABSv8i16	= 1531,
  ARM_VQABSv8i8	= 1532,
  ARM_VQADDsv16i8	= 1533,
  ARM_VQADDsv1i64	= 1534,
  ARM_VQADDsv2i32	= 1535,
  ARM_VQADDsv2i64	= 1536,
  ARM_VQADDsv4i16	= 1537,
  ARM_VQADDsv4i32	= 1538,
  ARM_VQADDsv8i16	= 1539,
  ARM_VQADDsv8i8	= 1540,
  ARM_VQADDuv16i8	= 1541,
  ARM_VQADDuv1i64	= 1542,
  ARM_VQADDuv2i32	= 1543,
  ARM_VQADDuv2i64	= 1544,
  ARM_VQADDuv4i16	= 1545,
  ARM_VQADDuv4i32	= 1546,
  ARM_VQADDuv8i16	= 1547,
  ARM_VQADDuv8i8	= 1548,
  ARM_VQDMLALslv2i32	= 1549,
  ARM_VQDMLALslv4i16	= 1550,
  ARM_VQDMLALv2i64	= 1551,
  ARM_VQDMLALv4i32	= 1552,
  ARM_VQDMLSLslv2i32	= 1553,
  ARM_VQDMLSLslv4i16	= 1554,
  ARM_VQDMLSLv2i64	= 1555,
  ARM_VQDMLSLv4i32	= 1556,
  ARM_VQDMULHslv2i32	= 1557,
  ARM_VQDMULHslv4i16	= 1558,
  ARM_VQDMULHslv4i32	= 1559,
  ARM_VQDMULHslv8i16	= 1560,
  ARM_VQDMULHv2i32	= 1561,
  ARM_VQDMULHv4i16	= 1562,
  ARM_VQDMULHv4i32	= 1563,
  ARM_VQDMULHv8i16	= 1564,
  ARM_VQDMULLslv2i32	= 1565,
  ARM_VQDMULLslv4i16	= 1566,
  ARM_VQDMULLv2i64	= 1567,
  ARM_VQDMULLv4i32	= 1568,
  ARM_VQMOVNsuv2i32	= 1569,
  ARM_VQMOVNsuv4i16	= 1570,
  ARM_VQMOVNsuv8i8	= 1571,
  ARM_VQMOVNsv2i32	= 1572,
  ARM_VQMOVNsv4i16	= 1573,
  ARM_VQMOVNsv8i8	= 1574,
  ARM_VQMOVNuv2i32	= 1575,
  ARM_VQMOVNuv4i16	= 1576,
  ARM_VQMOVNuv8i8	= 1577,
  ARM_VQNEGv16i8	= 1578,
  ARM_VQNEGv2i32	= 1579,
  ARM_VQNEGv4i16	= 1580,
  ARM_VQNEGv4i32	= 1581,
  ARM_VQNEGv8i16	= 1582,
  ARM_VQNEGv8i8	= 1583,
  ARM_VQRDMULHslv2i32	= 1584,
  ARM_VQRDMULHslv4i16	= 1585,
  ARM_VQRDMULHslv4i32	= 1586,
  ARM_VQRDMULHslv8i16	= 1587,
  ARM_VQRDMULHv2i32	= 1588,
  ARM_VQRDMULHv4i16	= 1589,
  ARM_VQRDMULHv4i32	= 1590,
  ARM_VQRDMULHv8i16	= 1591,
  ARM_VQRSHLsv16i8	= 1592,
  ARM_VQRSHLsv1i64	= 1593,
  ARM_VQRSHLsv2i32	= 1594,
  ARM_VQRSHLsv2i64	= 1595,
  ARM_VQRSHLsv4i16	= 1596,
  ARM_VQRSHLsv4i32	= 1597,
  ARM_VQRSHLsv8i16	= 1598,
  ARM_VQRSHLsv8i8	= 1599,
  ARM_VQRSHLuv16i8	= 1600,
  ARM_VQRSHLuv1i64	= 1601,
  ARM_VQRSHLuv2i32	= 1602,
  ARM_VQRSHLuv2i64	= 1603,
  ARM_VQRSHLuv4i16	= 1604,
  ARM_VQRSHLuv4i32	= 1605,
  ARM_VQRSHLuv8i16	= 1606,
  ARM_VQRSHLuv8i8	= 1607,
  ARM_VQRSHRNsv2i32	= 1608,
  ARM_VQRSHRNsv4i16	= 1609,
  ARM_VQRSHRNsv8i8	= 1610,
  ARM_VQRSHRNuv2i32	= 1611,
  ARM_VQRSHRNuv4i16	= 1612,
  ARM_VQRSHRNuv8i8	= 1613,
  ARM_VQRSHRUNv2i32	= 1614,
  ARM_VQRSHRUNv4i16	= 1615,
  ARM_VQRSHRUNv8i8	= 1616,
  ARM_VQSHLsiv16i8	= 1617,
  ARM_VQSHLsiv1i64	= 1618,
  ARM_VQSHLsiv2i32	= 1619,
  ARM_VQSHLsiv2i64	= 1620,
  ARM_VQSHLsiv4i16	= 1621,
  ARM_VQSHLsiv4i32	= 1622,
  ARM_VQSHLsiv8i16	= 1623,
  ARM_VQSHLsiv8i8	= 1624,
  ARM_VQSHLsuv16i8	= 1625,
  ARM_VQSHLsuv1i64	= 1626,
  ARM_VQSHLsuv2i32	= 1627,
  ARM_VQSHLsuv2i64	= 1628,
  ARM_VQSHLsuv4i16	= 1629,
  ARM_VQSHLsuv4i32	= 1630,
  ARM_VQSHLsuv8i16	= 1631,
  ARM_VQSHLsuv8i8	= 1632,
  ARM_VQSHLsv16i8	= 1633,
  ARM_VQSHLsv1i64	= 1634,
  ARM_VQSHLsv2i32	= 1635,
  ARM_VQSHLsv2i64	= 1636,
  ARM_VQSHLsv4i16	= 1637,
  ARM_VQSHLsv4i32	= 1638,
  ARM_VQSHLsv8i16	= 1639,
  ARM_VQSHLsv8i8	= 1640,
  ARM_VQSHLuiv16i8	= 1641,
  ARM_VQSHLuiv1i64	= 1642,
  ARM_VQSHLuiv2i32	= 1643,
  ARM_VQSHLuiv2i64	= 1644,
  ARM_VQSHLuiv4i16	= 1645,
  ARM_VQSHLuiv4i32	= 1646,
  ARM_VQSHLuiv8i16	= 1647,
  ARM_VQSHLuiv8i8	= 1648,
  ARM_VQSHLuv16i8	= 1649,
  ARM_VQSHLuv1i64	= 1650,
  ARM_VQSHLuv2i32	= 1651,
  ARM_VQSHLuv2i64	= 1652,
  ARM_VQSHLuv4i16	= 1653,
  ARM_VQSHLuv4i32	= 1654,
  ARM_VQSHLuv8i16	= 1655,
  ARM_VQSHLuv8i8	= 1656,
  ARM_VQSHRNsv2i32	= 1657,
  ARM_VQSHRNsv4i16	= 1658,
  ARM_VQSHRNsv8i8	= 1659,
  ARM_VQSHRNuv2i32	= 1660,
  ARM_VQSHRNuv4i16	= 1661,
  ARM_VQSHRNuv8i8	= 1662,
  ARM_VQSHRUNv2i32	= 1663,
  ARM_VQSHRUNv4i16	= 1664,
  ARM_VQSHRUNv8i8	= 1665,
  ARM_VQSUBsv16i8	= 1666,
  ARM_VQSUBsv1i64	= 1667,
  ARM_VQSUBsv2i32	= 1668,
  ARM_VQSUBsv2i64	= 1669,
  ARM_VQSUBsv4i16	= 1670,
  ARM_VQSUBsv4i32	= 1671,
  ARM_VQSUBsv8i16	= 1672,
  ARM_VQSUBsv8i8	= 1673,
  ARM_VQSUBuv16i8	= 1674,
  ARM_VQSUBuv1i64	= 1675,
  ARM_VQSUBuv2i32	= 1676,
  ARM_VQSUBuv2i64	= 1677,
  ARM_VQSUBuv4i16	= 1678,
  ARM_VQSUBuv4i32	= 1679,
  ARM_VQSUBuv8i16	= 1680,
  ARM_VQSUBuv8i8	= 1681,
  ARM_VRADDHNv2i32	= 1682,
  ARM_VRADDHNv4i16	= 1683,
  ARM_VRADDHNv8i8	= 1684,
  ARM_VRECPEd	= 1685,
  ARM_VRECPEfd	= 1686,
  ARM_VRECPEfq	= 1687,
  ARM_VRECPEq	= 1688,
  ARM_VRECPSfd	= 1689,
  ARM_VRECPSfq	= 1690,
  ARM_VREV16d8	= 1691,
  ARM_VREV16q8	= 1692,
  ARM_VREV32d16	= 1693,
  ARM_VREV32d8	= 1694,
  ARM_VREV32q16	= 1695,
  ARM_VREV32q8	= 1696,
  ARM_VREV64d16	= 1697,
  ARM_VREV64d32	= 1698,
  ARM_VREV64d8	= 1699,
  ARM_VREV64q16	= 1700,
  ARM_VREV64q32	= 1701,
  ARM_VREV64q8	= 1702,
  ARM_VRHADDsv16i8	= 1703,
  ARM_VRHADDsv2i32	= 1704,
  ARM_VRHADDsv4i16	= 1705,
  ARM_VRHADDsv4i32	= 1706,
  ARM_VRHADDsv8i16	= 1707,
  ARM_VRHADDsv8i8	= 1708,
  ARM_VRHADDuv16i8	= 1709,
  ARM_VRHADDuv2i32	= 1710,
  ARM_VRHADDuv4i16	= 1711,
  ARM_VRHADDuv4i32	= 1712,
  ARM_VRHADDuv8i16	= 1713,
  ARM_VRHADDuv8i8	= 1714,
  ARM_VRINTAD	= 1715,
  ARM_VRINTAND	= 1716,
  ARM_VRINTANQ	= 1717,
  ARM_VRINTAS	= 1718,
  ARM_VRINTMD	= 1719,
  ARM_VRINTMND	= 1720,
  ARM_VRINTMNQ	= 1721,
  ARM_VRINTMS	= 1722,
  ARM_VRINTND	= 1723,
  ARM_VRINTNND	= 1724,
  ARM_VRINTNNQ	= 1725,
  ARM_VRINTNS	= 1726,
  ARM_VRINTPD	= 1727,
  ARM_VRINTPND	= 1728,
  ARM_VRINTPNQ	= 1729,
  ARM_VRINTPS	= 1730,
  ARM_VRINTRD	= 1731,
  ARM_VRINTRS	= 1732,
  ARM_VRINTXD	= 1733,
  ARM_VRINTXND	= 1734,
  ARM_VRINTXNQ	= 1735,
  ARM_VRINTXS	= 1736,
  ARM_VRINTZD	= 1737,
  ARM_VRINTZND	= 1738,
  ARM_VRINTZNQ	= 1739,
  ARM_VRINTZS	= 1740,
  ARM_VRSHLsv16i8	= 1741,
  ARM_VRSHLsv1i64	= 1742,
  ARM_VRSHLsv2i32	= 1743,
  ARM_VRSHLsv2i64	= 1744,
  ARM_VRSHLsv4i16	= 1745,
  ARM_VRSHLsv4i32	= 1746,
  ARM_VRSHLsv8i16	= 1747,
  ARM_VRSHLsv8i8	= 1748,
  ARM_VRSHLuv16i8	= 1749,
  ARM_VRSHLuv1i64	= 1750,
  ARM_VRSHLuv2i32	= 1751,
  ARM_VRSHLuv2i64	= 1752,
  ARM_VRSHLuv4i16	= 1753,
  ARM_VRSHLuv4i32	= 1754,
  ARM_VRSHLuv8i16	= 1755,
  ARM_VRSHLuv8i8	= 1756,
  ARM_VRSHRNv2i32	= 1757,
  ARM_VRSHRNv4i16	= 1758,
  ARM_VRSHRNv8i8	= 1759,
  ARM_VRSHRsv16i8	= 1760,
  ARM_VRSHRsv1i64	= 1761,
  ARM_VRSHRsv2i32	= 1762,
  ARM_VRSHRsv2i64	= 1763,
  ARM_VRSHRsv4i16	= 1764,
  ARM_VRSHRsv4i32	= 1765,
  ARM_VRSHRsv8i16	= 1766,
  ARM_VRSHRsv8i8	= 1767,
  ARM_VRSHRuv16i8	= 1768,
  ARM_VRSHRuv1i64	= 1769,
  ARM_VRSHRuv2i32	= 1770,
  ARM_VRSHRuv2i64	= 1771,
  ARM_VRSHRuv4i16	= 1772,
  ARM_VRSHRuv4i32	= 1773,
  ARM_VRSHRuv8i16	= 1774,
  ARM_VRSHRuv8i8	= 1775,
  ARM_VRSQRTEd	= 1776,
  ARM_VRSQRTEfd	= 1777,
  ARM_VRSQRTEfq	= 1778,
  ARM_VRSQRTEq	= 1779,
  ARM_VRSQRTSfd	= 1780,
  ARM_VRSQRTSfq	= 1781,
  ARM_VRSRAsv16i8	= 1782,
  ARM_VRSRAsv1i64	= 1783,
  ARM_VRSRAsv2i32	= 1784,
  ARM_VRSRAsv2i64	= 1785,
  ARM_VRSRAsv4i16	= 1786,
  ARM_VRSRAsv4i32	= 1787,
  ARM_VRSRAsv8i16	= 1788,
  ARM_VRSRAsv8i8	= 1789,
  ARM_VRSRAuv16i8	= 1790,
  ARM_VRSRAuv1i64	= 1791,
  ARM_VRSRAuv2i32	= 1792,
  ARM_VRSRAuv2i64	= 1793,
  ARM_VRSRAuv4i16	= 1794,
  ARM_VRSRAuv4i32	= 1795,
  ARM_VRSRAuv8i16	= 1796,
  ARM_VRSRAuv8i8	= 1797,
  ARM_VRSUBHNv2i32	= 1798,
  ARM_VRSUBHNv4i16	= 1799,
  ARM_VRSUBHNv8i8	= 1800,
  ARM_VSELEQD	= 1801,
  ARM_VSELEQS	= 1802,
  ARM_VSELGED	= 1803,
  ARM_VSELGES	= 1804,
  ARM_VSELGTD	= 1805,
  ARM_VSELGTS	= 1806,
  ARM_VSELVSD	= 1807,
  ARM_VSELVSS	= 1808,
  ARM_VSETLNi16	= 1809,
  ARM_VSETLNi32	= 1810,
  ARM_VSETLNi8	= 1811,
  ARM_VSHLLi16	= 1812,
  ARM_VSHLLi32	= 1813,
  ARM_VSHLLi8	= 1814,
  ARM_VSHLLsv2i64	= 1815,
  ARM_VSHLLsv4i32	= 1816,
  ARM_VSHLLsv8i16	= 1817,
  ARM_VSHLLuv2i64	= 1818,
  ARM_VSHLLuv4i32	= 1819,
  ARM_VSHLLuv8i16	= 1820,
  ARM_VSHLiv16i8	= 1821,
  ARM_VSHLiv1i64	= 1822,
  ARM_VSHLiv2i32	= 1823,
  ARM_VSHLiv2i64	= 1824,
  ARM_VSHLiv4i16	= 1825,
  ARM_VSHLiv4i32	= 1826,
  ARM_VSHLiv8i16	= 1827,
  ARM_VSHLiv8i8	= 1828,
  ARM_VSHLsv16i8	= 1829,
  ARM_VSHLsv1i64	= 1830,
  ARM_VSHLsv2i32	= 1831,
  ARM_VSHLsv2i64	= 1832,
  ARM_VSHLsv4i16	= 1833,
  ARM_VSHLsv4i32	= 1834,
  ARM_VSHLsv8i16	= 1835,
  ARM_VSHLsv8i8	= 1836,
  ARM_VSHLuv16i8	= 1837,
  ARM_VSHLuv1i64	= 1838,
  ARM_VSHLuv2i32	= 1839,
  ARM_VSHLuv2i64	= 1840,
  ARM_VSHLuv4i16	= 1841,
  ARM_VSHLuv4i32	= 1842,
  ARM_VSHLuv8i16	= 1843,
  ARM_VSHLuv8i8	= 1844,
  ARM_VSHRNv2i32	= 1845,
  ARM_VSHRNv4i16	= 1846,
  ARM_VSHRNv8i8	= 1847,
  ARM_VSHRsv16i8	= 1848,
  ARM_VSHRsv1i64	= 1849,
  ARM_VSHRsv2i32	= 1850,
  ARM_VSHRsv2i64	= 1851,
  ARM_VSHRsv4i16	= 1852,
  ARM_VSHRsv4i32	= 1853,
  ARM_VSHRsv8i16	= 1854,
  ARM_VSHRsv8i8	= 1855,
  ARM_VSHRuv16i8	= 1856,
  ARM_VSHRuv1i64	= 1857,
  ARM_VSHRuv2i32	= 1858,
  ARM_VSHRuv2i64	= 1859,
  ARM_VSHRuv4i16	= 1860,
  ARM_VSHRuv4i32	= 1861,
  ARM_VSHRuv8i16	= 1862,
  ARM_VSHRuv8i8	= 1863,
  ARM_VSHTOD	= 1864,
  ARM_VSHTOS	= 1865,
  ARM_VSITOD	= 1866,
  ARM_VSITOS	= 1867,
  ARM_VSLIv16i8	= 1868,
  ARM_VSLIv1i64	= 1869,
  ARM_VSLIv2i32	= 1870,
  ARM_VSLIv2i64	= 1871,
  ARM_VSLIv4i16	= 1872,
  ARM_VSLIv4i32	= 1873,
  ARM_VSLIv8i16	= 1874,
  ARM_VSLIv8i8	= 1875,
  ARM_VSLTOD	= 1876,
  ARM_VSLTOS	= 1877,
  ARM_VSQRTD	= 1878,
  ARM_VSQRTS	= 1879,
  ARM_VSRAsv16i8	= 1880,
  ARM_VSRAsv1i64	= 1881,
  ARM_VSRAsv2i32	= 1882,
  ARM_VSRAsv2i64	= 1883,
  ARM_VSRAsv4i16	= 1884,
  ARM_VSRAsv4i32	= 1885,
  ARM_VSRAsv8i16	= 1886,
  ARM_VSRAsv8i8	= 1887,
  ARM_VSRAuv16i8	= 1888,
  ARM_VSRAuv1i64	= 1889,
  ARM_VSRAuv2i32	= 1890,
  ARM_VSRAuv2i64	= 1891,
  ARM_VSRAuv4i16	= 1892,
  ARM_VSRAuv4i32	= 1893,
  ARM_VSRAuv8i16	= 1894,
  ARM_VSRAuv8i8	= 1895,
  ARM_VSRIv16i8	= 1896,
  ARM_VSRIv1i64	= 1897,
  ARM_VSRIv2i32	= 1898,
  ARM_VSRIv2i64	= 1899,
  ARM_VSRIv4i16	= 1900,
  ARM_VSRIv4i32	= 1901,
  ARM_VSRIv8i16	= 1902,
  ARM_VSRIv8i8	= 1903,
  ARM_VST1LNd16	= 1904,
  ARM_VST1LNd16_UPD	= 1905,
  ARM_VST1LNd32	= 1906,
  ARM_VST1LNd32_UPD	= 1907,
  ARM_VST1LNd8	= 1908,
  ARM_VST1LNd8_UPD	= 1909,
  ARM_VST1LNdAsm_16	= 1910,
  ARM_VST1LNdAsm_32	= 1911,
  ARM_VST1LNdAsm_8	= 1912,
  ARM_VST1LNdWB_fixed_Asm_16	= 1913,
  ARM_VST1LNdWB_fixed_Asm_32	= 1914,
  ARM_VST1LNdWB_fixed_Asm_8	= 1915,
  ARM_VST1LNdWB_register_Asm_16	= 1916,
  ARM_VST1LNdWB_register_Asm_32	= 1917,
  ARM_VST1LNdWB_register_Asm_8	= 1918,
  ARM_VST1LNq16Pseudo	= 1919,
  ARM_VST1LNq16Pseudo_UPD	= 1920,
  ARM_VST1LNq32Pseudo	= 1921,
  ARM_VST1LNq32Pseudo_UPD	= 1922,
  ARM_VST1LNq8Pseudo	= 1923,
  ARM_VST1LNq8Pseudo_UPD	= 1924,
  ARM_VST1d16	= 1925,
  ARM_VST1d16Q	= 1926,
  ARM_VST1d16Qwb_fixed	= 1927,
  ARM_VST1d16Qwb_register	= 1928,
  ARM_VST1d16T	= 1929,
  ARM_VST1d16Twb_fixed	= 1930,
  ARM_VST1d16Twb_register	= 1931,
  ARM_VST1d16wb_fixed	= 1932,
  ARM_VST1d16wb_register	= 1933,
  ARM_VST1d32	= 1934,
  ARM_VST1d32Q	= 1935,
  ARM_VST1d32Qwb_fixed	= 1936,
  ARM_VST1d32Qwb_register	= 1937,
  ARM_VST1d32T	= 1938,
  ARM_VST1d32Twb_fixed	= 1939,
  ARM_VST1d32Twb_register	= 1940,
  ARM_VST1d32wb_fixed	= 1941,
  ARM_VST1d32wb_register	= 1942,
  ARM_VST1d64	= 1943,
  ARM_VST1d64Q	= 1944,
  ARM_VST1d64QPseudo	= 1945,
  ARM_VST1d64QPseudoWB_fixed	= 1946,
  ARM_VST1d64QPseudoWB_register	= 1947,
  ARM_VST1d64Qwb_fixed	= 1948,
  ARM_VST1d64Qwb_register	= 1949,
  ARM_VST1d64T	= 1950,
  ARM_VST1d64TPseudo	= 1951,
  ARM_VST1d64TPseudoWB_fixed	= 1952,
  ARM_VST1d64TPseudoWB_register	= 1953,
  ARM_VST1d64Twb_fixed	= 1954,
  ARM_VST1d64Twb_register	= 1955,
  ARM_VST1d64wb_fixed	= 1956,
  ARM_VST1d64wb_register	= 1957,
  ARM_VST1d8	= 1958,
  ARM_VST1d8Q	= 1959,
  ARM_VST1d8Qwb_fixed	= 1960,
  ARM_VST1d8Qwb_register	= 1961,
  ARM_VST1d8T	= 1962,
  ARM_VST1d8Twb_fixed	= 1963,
  ARM_VST1d8Twb_register	= 1964,
  ARM_VST1d8wb_fixed	= 1965,
  ARM_VST1d8wb_register	= 1966,
  ARM_VST1q16	= 1967,
  ARM_VST1q16wb_fixed	= 1968,
  ARM_VST1q16wb_register	= 1969,
  ARM_VST1q32	= 1970,
  ARM_VST1q32wb_fixed	= 1971,
  ARM_VST1q32wb_register	= 1972,
  ARM_VST1q64	= 1973,
  ARM_VST1q64wb_fixed	= 1974,
  ARM_VST1q64wb_register	= 1975,
  ARM_VST1q8	= 1976,
  ARM_VST1q8wb_fixed	= 1977,
  ARM_VST1q8wb_register	= 1978,
  ARM_VST2LNd16	= 1979,
  ARM_VST2LNd16Pseudo	= 1980,
  ARM_VST2LNd16Pseudo_UPD	= 1981,
  ARM_VST2LNd16_UPD	= 1982,
  ARM_VST2LNd32	= 1983,
  ARM_VST2LNd32Pseudo	= 1984,
  ARM_VST2LNd32Pseudo_UPD	= 1985,
  ARM_VST2LNd32_UPD	= 1986,
  ARM_VST2LNd8	= 1987,
  ARM_VST2LNd8Pseudo	= 1988,
  ARM_VST2LNd8Pseudo_UPD	= 1989,
  ARM_VST2LNd8_UPD	= 1990,
  ARM_VST2LNdAsm_16	= 1991,
  ARM_VST2LNdAsm_32	= 1992,
  ARM_VST2LNdAsm_8	= 1993,
  ARM_VST2LNdWB_fixed_Asm_16	= 1994,
  ARM_VST2LNdWB_fixed_Asm_32	= 1995,
  ARM_VST2LNdWB_fixed_Asm_8	= 1996,
  ARM_VST2LNdWB_register_Asm_16	= 1997,
  ARM_VST2LNdWB_register_Asm_32	= 1998,
  ARM_VST2LNdWB_register_Asm_8	= 1999,
  ARM_VST2LNq16	= 2000,
  ARM_VST2LNq16Pseudo	= 2001,
  ARM_VST2LNq16Pseudo_UPD	= 2002,
  ARM_VST2LNq16_UPD	= 2003,
  ARM_VST2LNq32	= 2004,
  ARM_VST2LNq32Pseudo	= 2005,
  ARM_VST2LNq32Pseudo_UPD	= 2006,
  ARM_VST2LNq32_UPD	= 2007,
  ARM_VST2LNqAsm_16	= 2008,
  ARM_VST2LNqAsm_32	= 2009,
  ARM_VST2LNqWB_fixed_Asm_16	= 2010,
  ARM_VST2LNqWB_fixed_Asm_32	= 2011,
  ARM_VST2LNqWB_register_Asm_16	= 2012,
  ARM_VST2LNqWB_register_Asm_32	= 2013,
  ARM_VST2b16	= 2014,
  ARM_VST2b16wb_fixed	= 2015,
  ARM_VST2b16wb_register	= 2016,
  ARM_VST2b32	= 2017,
  ARM_VST2b32wb_fixed	= 2018,
  ARM_VST2b32wb_register	= 2019,
  ARM_VST2b8	= 2020,
  ARM_VST2b8wb_fixed	= 2021,
  ARM_VST2b8wb_register	= 2022,
  ARM_VST2d16	= 2023,
  ARM_VST2d16wb_fixed	= 2024,
  ARM_VST2d16wb_register	= 2025,
  ARM_VST2d32	= 2026,
  ARM_VST2d32wb_fixed	= 2027,
  ARM_VST2d32wb_register	= 2028,
  ARM_VST2d8	= 2029,
  ARM_VST2d8wb_fixed	= 2030,
  ARM_VST2d8wb_register	= 2031,
  ARM_VST2q16	= 2032,
  ARM_VST2q16Pseudo	= 2033,
  ARM_VST2q16PseudoWB_fixed	= 2034,
  ARM_VST2q16PseudoWB_register	= 2035,
  ARM_VST2q16wb_fixed	= 2036,
  ARM_VST2q16wb_register	= 2037,
  ARM_VST2q32	= 2038,
  ARM_VST2q32Pseudo	= 2039,
  ARM_VST2q32PseudoWB_fixed	= 2040,
  ARM_VST2q32PseudoWB_register	= 2041,
  ARM_VST2q32wb_fixed	= 2042,
  ARM_VST2q32wb_register	= 2043,
  ARM_VST2q8	= 2044,
  ARM_VST2q8Pseudo	= 2045,
  ARM_VST2q8PseudoWB_fixed	= 2046,
  ARM_VST2q8PseudoWB_register	= 2047,
  ARM_VST2q8wb_fixed	= 2048,
  ARM_VST2q8wb_register	= 2049,
  ARM_VST3LNd16	= 2050,
  ARM_VST3LNd16Pseudo	= 2051,
  ARM_VST3LNd16Pseudo_UPD	= 2052,
  ARM_VST3LNd16_UPD	= 2053,
  ARM_VST3LNd32	= 2054,
  ARM_VST3LNd32Pseudo	= 2055,
  ARM_VST3LNd32Pseudo_UPD	= 2056,
  ARM_VST3LNd32_UPD	= 2057,
  ARM_VST3LNd8	= 2058,
  ARM_VST3LNd8Pseudo	= 2059,
  ARM_VST3LNd8Pseudo_UPD	= 2060,
  ARM_VST3LNd8_UPD	= 2061,
  ARM_VST3LNdAsm_16	= 2062,
  ARM_VST3LNdAsm_32	= 2063,
  ARM_VST3LNdAsm_8	= 2064,
  ARM_VST3LNdWB_fixed_Asm_16	= 2065,
  ARM_VST3LNdWB_fixed_Asm_32	= 2066,
  ARM_VST3LNdWB_fixed_Asm_8	= 2067,
  ARM_VST3LNdWB_register_Asm_16	= 2068,
  ARM_VST3LNdWB_register_Asm_32	= 2069,
  ARM_VST3LNdWB_register_Asm_8	= 2070,
  ARM_VST3LNq16	= 2071,
  ARM_VST3LNq16Pseudo	= 2072,
  ARM_VST3LNq16Pseudo_UPD	= 2073,
  ARM_VST3LNq16_UPD	= 2074,
  ARM_VST3LNq32	= 2075,
  ARM_VST3LNq32Pseudo	= 2076,
  ARM_VST3LNq32Pseudo_UPD	= 2077,
  ARM_VST3LNq32_UPD	= 2078,
  ARM_VST3LNqAsm_16	= 2079,
  ARM_VST3LNqAsm_32	= 2080,
  ARM_VST3LNqWB_fixed_Asm_16	= 2081,
  ARM_VST3LNqWB_fixed_Asm_32	= 2082,
  ARM_VST3LNqWB_register_Asm_16	= 2083,
  ARM_VST3LNqWB_register_Asm_32	= 2084,
  ARM_VST3d16	= 2085,
  ARM_VST3d16Pseudo	= 2086,
  ARM_VST3d16Pseudo_UPD	= 2087,
  ARM_VST3d16_UPD	= 2088,
  ARM_VST3d32	= 2089,
  ARM_VST3d32Pseudo	= 2090,
  ARM_VST3d32Pseudo_UPD	= 2091,
  ARM_VST3d32_UPD	= 2092,
  ARM_VST3d8	= 2093,
  ARM_VST3d8Pseudo	= 2094,
  ARM_VST3d8Pseudo_UPD	= 2095,
  ARM_VST3d8_UPD	= 2096,
  ARM_VST3dAsm_16	= 2097,
  ARM_VST3dAsm_32	= 2098,
  ARM_VST3dAsm_8	= 2099,
  ARM_VST3dWB_fixed_Asm_16	= 2100,
  ARM_VST3dWB_fixed_Asm_32	= 2101,
  ARM_VST3dWB_fixed_Asm_8	= 2102,
  ARM_VST3dWB_register_Asm_16	= 2103,
  ARM_VST3dWB_register_Asm_32	= 2104,
  ARM_VST3dWB_register_Asm_8	= 2105,
  ARM_VST3q16	= 2106,
  ARM_VST3q16Pseudo_UPD	= 2107,
  ARM_VST3q16_UPD	= 2108,
  ARM_VST3q16oddPseudo	= 2109,
  ARM_VST3q16oddPseudo_UPD	= 2110,
  ARM_VST3q32	= 2111,
  ARM_VST3q32Pseudo_UPD	= 2112,
  ARM_VST3q32_UPD	= 2113,
  ARM_VST3q32oddPseudo	= 2114,
  ARM_VST3q32oddPseudo_UPD	= 2115,
  ARM_VST3q8	= 2116,
  ARM_VST3q8Pseudo_UPD	= 2117,
  ARM_VST3q8_UPD	= 2118,
  ARM_VST3q8oddPseudo	= 2119,
  ARM_VST3q8oddPseudo_UPD	= 2120,
  ARM_VST3qAsm_16	= 2121,
  ARM_VST3qAsm_32	= 2122,
  ARM_VST3qAsm_8	= 2123,
  ARM_VST3qWB_fixed_Asm_16	= 2124,
  ARM_VST3qWB_fixed_Asm_32	= 2125,
  ARM_VST3qWB_fixed_Asm_8	= 2126,
  ARM_VST3qWB_register_Asm_16	= 2127,
  ARM_VST3qWB_register_Asm_32	= 2128,
  ARM_VST3qWB_register_Asm_8	= 2129,
  ARM_VST4LNd16	= 2130,
  ARM_VST4LNd16Pseudo	= 2131,
  ARM_VST4LNd16Pseudo_UPD	= 2132,
  ARM_VST4LNd16_UPD	= 2133,
  ARM_VST4LNd32	= 2134,
  ARM_VST4LNd32Pseudo	= 2135,
  ARM_VST4LNd32Pseudo_UPD	= 2136,
  ARM_VST4LNd32_UPD	= 2137,
  ARM_VST4LNd8	= 2138,
  ARM_VST4LNd8Pseudo	= 2139,
  ARM_VST4LNd8Pseudo_UPD	= 2140,
  ARM_VST4LNd8_UPD	= 2141,
  ARM_VST4LNdAsm_16	= 2142,
  ARM_VST4LNdAsm_32	= 2143,
  ARM_VST4LNdAsm_8	= 2144,
  ARM_VST4LNdWB_fixed_Asm_16	= 2145,
  ARM_VST4LNdWB_fixed_Asm_32	= 2146,
  ARM_VST4LNdWB_fixed_Asm_8	= 2147,
  ARM_VST4LNdWB_register_Asm_16	= 2148,
  ARM_VST4LNdWB_register_Asm_32	= 2149,
  ARM_VST4LNdWB_register_Asm_8	= 2150,
  ARM_VST4LNq16	= 2151,
  ARM_VST4LNq16Pseudo	= 2152,
  ARM_VST4LNq16Pseudo_UPD	= 2153,
  ARM_VST4LNq16_UPD	= 2154,
  ARM_VST4LNq32	= 2155,
  ARM_VST4LNq32Pseudo	= 2156,
  ARM_VST4LNq32Pseudo_UPD	= 2157,
  ARM_VST4LNq32_UPD	= 2158,
  ARM_VST4LNqAsm_16	= 2159,
  ARM_VST4LNqAsm_32	= 2160,
  ARM_VST4LNqWB_fixed_Asm_16	= 2161,
  ARM_VST4LNqWB_fixed_Asm_32	= 2162,
  ARM_VST4LNqWB_register_Asm_16	= 2163,
  ARM_VST4LNqWB_register_Asm_32	= 2164,
  ARM_VST4d16	= 2165,
  ARM_VST4d16Pseudo	= 2166,
  ARM_VST4d16Pseudo_UPD	= 2167,
  ARM_VST4d16_UPD	= 2168,
  ARM_VST4d32	= 2169,
  ARM_VST4d32Pseudo	= 2170,
  ARM_VST4d32Pseudo_UPD	= 2171,
  ARM_VST4d32_UPD	= 2172,
  ARM_VST4d8	= 2173,
  ARM_VST4d8Pseudo	= 2174,
  ARM_VST4d8Pseudo_UPD	= 2175,
  ARM_VST4d8_UPD	= 2176,
  ARM_VST4dAsm_16	= 2177,
  ARM_VST4dAsm_32	= 2178,
  ARM_VST4dAsm_8	= 2179,
  ARM_VST4dWB_fixed_Asm_16	= 2180,
  ARM_VST4dWB_fixed_Asm_32	= 2181,
  ARM_VST4dWB_fixed_Asm_8	= 2182,
  ARM_VST4dWB_register_Asm_16	= 2183,
  ARM_VST4dWB_register_Asm_32	= 2184,
  ARM_VST4dWB_register_Asm_8	= 2185,
  ARM_VST4q16	= 2186,
  ARM_VST4q16Pseudo_UPD	= 2187,
  ARM_VST4q16_UPD	= 2188,
  ARM_VST4q16oddPseudo	= 2189,
  ARM_VST4q16oddPseudo_UPD	= 2190,
  ARM_VST4q32	= 2191,
  ARM_VST4q32Pseudo_UPD	= 2192,
  ARM_VST4q32_UPD	= 2193,
  ARM_VST4q32oddPseudo	= 2194,
  ARM_VST4q32oddPseudo_UPD	= 2195,
  ARM_VST4q8	= 2196,
  ARM_VST4q8Pseudo_UPD	= 2197,
  ARM_VST4q8_UPD	= 2198,
  ARM_VST4q8oddPseudo	= 2199,
  ARM_VST4q8oddPseudo_UPD	= 2200,
  ARM_VST4qAsm_16	= 2201,
  ARM_VST4qAsm_32	= 2202,
  ARM_VST4qAsm_8	= 2203,
  ARM_VST4qWB_fixed_Asm_16	= 2204,
  ARM_VST4qWB_fixed_Asm_32	= 2205,
  ARM_VST4qWB_fixed_Asm_8	= 2206,
  ARM_VST4qWB_register_Asm_16	= 2207,
  ARM_VST4qWB_register_Asm_32	= 2208,
  ARM_VST4qWB_register_Asm_8	= 2209,
  ARM_VSTMDDB_UPD	= 2210,
  ARM_VSTMDIA	= 2211,
  ARM_VSTMDIA_UPD	= 2212,
  ARM_VSTMQIA	= 2213,
  ARM_VSTMSDB_UPD	= 2214,
  ARM_VSTMSIA	= 2215,
  ARM_VSTMSIA_UPD	= 2216,
  ARM_VSTRD	= 2217,
  ARM_VSTRS	= 2218,
  ARM_VSUBD	= 2219,
  ARM_VSUBHNv2i32	= 2220,
  ARM_VSUBHNv4i16	= 2221,
  ARM_VSUBHNv8i8	= 2222,
  ARM_VSUBLsv2i64	= 2223,
  ARM_VSUBLsv4i32	= 2224,
  ARM_VSUBLsv8i16	= 2225,
  ARM_VSUBLuv2i64	= 2226,
  ARM_VSUBLuv4i32	= 2227,
  ARM_VSUBLuv8i16	= 2228,
  ARM_VSUBS	= 2229,
  ARM_VSUBWsv2i64	= 2230,
  ARM_VSUBWsv4i32	= 2231,
  ARM_VSUBWsv8i16	= 2232,
  ARM_VSUBWuv2i64	= 2233,
  ARM_VSUBWuv4i32	= 2234,
  ARM_VSUBWuv8i16	= 2235,
  ARM_VSUBfd	= 2236,
  ARM_VSUBfq	= 2237,
  ARM_VSUBv16i8	= 2238,
  ARM_VSUBv1i64	= 2239,
  ARM_VSUBv2i32	= 2240,
  ARM_VSUBv2i64	= 2241,
  ARM_VSUBv4i16	= 2242,
  ARM_VSUBv4i32	= 2243,
  ARM_VSUBv8i16	= 2244,
  ARM_VSUBv8i8	= 2245,
  ARM_VSWPd	= 2246,
  ARM_VSWPq	= 2247,
  ARM_VTBL1	= 2248,
  ARM_VTBL2	= 2249,
  ARM_VTBL3	= 2250,
  ARM_VTBL3Pseudo	= 2251,
  ARM_VTBL4	= 2252,
  ARM_VTBL4Pseudo	= 2253,
  ARM_VTBX1	= 2254,
  ARM_VTBX2	= 2255,
  ARM_VTBX3	= 2256,
  ARM_VTBX3Pseudo	= 2257,
  ARM_VTBX4	= 2258,
  ARM_VTBX4Pseudo	= 2259,
  ARM_VTOSHD	= 2260,
  ARM_VTOSHS	= 2261,
  ARM_VTOSIRD	= 2262,
  ARM_VTOSIRS	= 2263,
  ARM_VTOSIZD	= 2264,
  ARM_VTOSIZS	= 2265,
  ARM_VTOSLD	= 2266,
  ARM_VTOSLS	= 2267,
  ARM_VTOUHD	= 2268,
  ARM_VTOUHS	= 2269,
  ARM_VTOUIRD	= 2270,
  ARM_VTOUIRS	= 2271,
  ARM_VTOUIZD	= 2272,
  ARM_VTOUIZS	= 2273,
  ARM_VTOULD	= 2274,
  ARM_VTOULS	= 2275,
  ARM_VTRNd16	= 2276,
  ARM_VTRNd32	= 2277,
  ARM_VTRNd8	= 2278,
  ARM_VTRNq16	= 2279,
  ARM_VTRNq32	= 2280,
  ARM_VTRNq8	= 2281,
  ARM_VTSTv16i8	= 2282,
  ARM_VTSTv2i32	= 2283,
  ARM_VTSTv4i16	= 2284,
  ARM_VTSTv4i32	= 2285,
  ARM_VTSTv8i16	= 2286,
  ARM_VTSTv8i8	= 2287,
  ARM_VUHTOD	= 2288,
  ARM_VUHTOS	= 2289,
  ARM_VUITOD	= 2290,
  ARM_VUITOS	= 2291,
  ARM_VULTOD	= 2292,
  ARM_VULTOS	= 2293,
  ARM_VUZPd16	= 2294,
  ARM_VUZPd8	= 2295,
  ARM_VUZPq16	= 2296,
  ARM_VUZPq32	= 2297,
  ARM_VUZPq8	= 2298,
  ARM_VZIPd16	= 2299,
  ARM_VZIPd8	= 2300,
  ARM_VZIPq16	= 2301,
  ARM_VZIPq32	= 2302,
  ARM_VZIPq8	= 2303,
  ARM_sysLDMDA	= 2304,
  ARM_sysLDMDA_UPD	= 2305,
  ARM_sysLDMDB	= 2306,
  ARM_sysLDMDB_UPD	= 2307,
  ARM_sysLDMIA	= 2308,
  ARM_sysLDMIA_UPD	= 2309,
  ARM_sysLDMIB	= 2310,
  ARM_sysLDMIB_UPD	= 2311,
  ARM_sysSTMDA	= 2312,
  ARM_sysSTMDA_UPD	= 2313,
  ARM_sysSTMDB	= 2314,
  ARM_sysSTMDB_UPD	= 2315,
  ARM_sysSTMIA	= 2316,
  ARM_sysSTMIA_UPD	= 2317,
  ARM_sysSTMIB	= 2318,
  ARM_sysSTMIB_UPD	= 2319,
  ARM_t2ABS	= 2320,
  ARM_t2ADCri	= 2321,
  ARM_t2ADCrr	= 2322,
  ARM_t2ADCrs	= 2323,
  ARM_t2ADDSri	= 2324,
  ARM_t2ADDSrr	= 2325,
  ARM_t2ADDSrs	= 2326,
  ARM_t2ADDri	= 2327,
  ARM_t2ADDri12	= 2328,
  ARM_t2ADDrr	= 2329,
  ARM_t2ADDrs	= 2330,
  ARM_t2ADR	= 2331,
  ARM_t2ANDri	= 2332,
  ARM_t2ANDrr	= 2333,
  ARM_t2ANDrs	= 2334,
  ARM_t2ASRri	= 2335,
  ARM_t2ASRrr	= 2336,
  ARM_t2B	= 2337,
  ARM_t2BFC	= 2338,
  ARM_t2BFI	= 2339,
  ARM_t2BICri	= 2340,
  ARM_t2BICrr	= 2341,
  ARM_t2BICrs	= 2342,
  ARM_t2BR_JT	= 2343,
  ARM_t2BXJ	= 2344,
  ARM_t2Bcc	= 2345,
  ARM_t2CDP	= 2346,
  ARM_t2CDP2	= 2347,
  ARM_t2CLREX	= 2348,
  ARM_t2CLZ	= 2349,
  ARM_t2CMNri	= 2350,
  ARM_t2CMNzrr	= 2351,
  ARM_t2CMNzrs	= 2352,
  ARM_t2CMPri	= 2353,
  ARM_t2CMPrr	= 2354,
  ARM_t2CMPrs	= 2355,
  ARM_t2CPS1p	= 2356,
  ARM_t2CPS2p	= 2357,
  ARM_t2CPS3p	= 2358,
  ARM_t2CRC32B	= 2359,
  ARM_t2CRC32CB	= 2360,
  ARM_t2CRC32CH	= 2361,
  ARM_t2CRC32CW	= 2362,
  ARM_t2CRC32H	= 2363,
  ARM_t2CRC32W	= 2364,
  ARM_t2DBG	= 2365,
  ARM_t2DCPS1	= 2366,
  ARM_t2DCPS2	= 2367,
  ARM_t2DCPS3	= 2368,
  ARM_t2DMB	= 2369,
  ARM_t2DSB	= 2370,
  ARM_t2EORri	= 2371,
  ARM_t2EORrr	= 2372,
  ARM_t2EORrs	= 2373,
  ARM_t2HINT	= 2374,
  ARM_t2ISB	= 2375,
  ARM_t2IT	= 2376,
  ARM_t2Int_eh_sjlj_setjmp	= 2377,
  ARM_t2Int_eh_sjlj_setjmp_nofp	= 2378,
  ARM_t2LDA	= 2379,
  ARM_t2LDAB	= 2380,
  ARM_t2LDAEX	= 2381,
  ARM_t2LDAEXB	= 2382,
  ARM_t2LDAEXD	= 2383,
  ARM_t2LDAEXH	= 2384,
  ARM_t2LDAH	= 2385,
  ARM_t2LDC2L_OFFSET	= 2386,
  ARM_t2LDC2L_OPTION	= 2387,
  ARM_t2LDC2L_POST	= 2388,
  ARM_t2LDC2L_PRE	= 2389,
  ARM_t2LDC2_OFFSET	= 2390,
  ARM_t2LDC2_OPTION	= 2391,
  ARM_t2LDC2_POST	= 2392,
  ARM_t2LDC2_PRE	= 2393,
  ARM_t2LDCL_OFFSET	= 2394,
  ARM_t2LDCL_OPTION	= 2395,
  ARM_t2LDCL_POST	= 2396,
  ARM_t2LDCL_PRE	= 2397,
  ARM_t2LDC_OFFSET	= 2398,
  ARM_t2LDC_OPTION	= 2399,
  ARM_t2LDC_POST	= 2400,
  ARM_t2LDC_PRE	= 2401,
  ARM_t2LDMDB	= 2402,
  ARM_t2LDMDB_UPD	= 2403,
  ARM_t2LDMIA	= 2404,
  ARM_t2LDMIA_RET	= 2405,
  ARM_t2LDMIA_UPD	= 2406,
  ARM_t2LDRBT	= 2407,
  ARM_t2LDRB_POST	= 2408,
  ARM_t2LDRB_PRE	= 2409,
  ARM_t2LDRBi12	= 2410,
  ARM_t2LDRBi8	= 2411,
  ARM_t2LDRBpci	= 2412,
  ARM_t2LDRBpcrel	= 2413,
  ARM_t2LDRBs	= 2414,
  ARM_t2LDRD_POST	= 2415,
  ARM_t2LDRD_PRE	= 2416,
  ARM_t2LDRDi8	= 2417,
  ARM_t2LDREX	= 2418,
  ARM_t2LDREXB	= 2419,
  ARM_t2LDREXD	= 2420,
  ARM_t2LDREXH	= 2421,
  ARM_t2LDRHT	= 2422,
  ARM_t2LDRH_POST	= 2423,
  ARM_t2LDRH_PRE	= 2424,
  ARM_t2LDRHi12	= 2425,
  ARM_t2LDRHi8	= 2426,
  ARM_t2LDRHpci	= 2427,
  ARM_t2LDRHpcrel	= 2428,
  ARM_t2LDRHs	= 2429,
  ARM_t2LDRSBT	= 2430,
  ARM_t2LDRSB_POST	= 2431,
  ARM_t2LDRSB_PRE	= 2432,
  ARM_t2LDRSBi12	= 2433,
  ARM_t2LDRSBi8	= 2434,
  ARM_t2LDRSBpci	= 2435,
  ARM_t2LDRSBpcrel	= 2436,
  ARM_t2LDRSBs	= 2437,
  ARM_t2LDRSHT	= 2438,
  ARM_t2LDRSH_POST	= 2439,
  ARM_t2LDRSH_PRE	= 2440,
  ARM_t2LDRSHi12	= 2441,
  ARM_t2LDRSHi8	= 2442,
  ARM_t2LDRSHpci	= 2443,
  ARM_t2LDRSHpcrel	= 2444,
  ARM_t2LDRSHs	= 2445,
  ARM_t2LDRT	= 2446,
  ARM_t2LDR_POST	= 2447,
  ARM_t2LDR_PRE	= 2448,
  ARM_t2LDRi12	= 2449,
  ARM_t2LDRi8	= 2450,
  ARM_t2LDRpci	= 2451,
  ARM_t2LDRpci_pic	= 2452,
  ARM_t2LDRpcrel	= 2453,
  ARM_t2LDRs	= 2454,
  ARM_t2LEApcrel	= 2455,
  ARM_t2LEApcrelJT	= 2456,
  ARM_t2LSLri	= 2457,
  ARM_t2LSLrr	= 2458,
  ARM_t2LSRri	= 2459,
  ARM_t2LSRrr	= 2460,
  ARM_t2MCR	= 2461,
  ARM_t2MCR2	= 2462,
  ARM_t2MCRR	= 2463,
  ARM_t2MCRR2	= 2464,
  ARM_t2MLA	= 2465,
  ARM_t2MLS	= 2466,
  ARM_t2MOVCCasr	= 2467,
  ARM_t2MOVCCi	= 2468,
  ARM_t2MOVCCi16	= 2469,
  ARM_t2MOVCCi32imm	= 2470,
  ARM_t2MOVCClsl	= 2471,
  ARM_t2MOVCClsr	= 2472,
  ARM_t2MOVCCr	= 2473,
  ARM_t2MOVCCror	= 2474,
  ARM_t2MOVSsi	= 2475,
  ARM_t2MOVSsr	= 2476,
  ARM_t2MOVTi16	= 2477,
  ARM_t2MOVTi16_ga_pcrel	= 2478,
  ARM_t2MOV_ga_pcrel	= 2479,
  ARM_t2MOVi	= 2480,
  ARM_t2MOVi16	= 2481,
  ARM_t2MOVi16_ga_pcrel	= 2482,
  ARM_t2MOVi32imm	= 2483,
  ARM_t2MOVr	= 2484,
  ARM_t2MOVsi	= 2485,
  ARM_t2MOVsr	= 2486,
  ARM_t2MOVsra_flag	= 2487,
  ARM_t2MOVsrl_flag	= 2488,
  ARM_t2MRC	= 2489,
  ARM_t2MRC2	= 2490,
  ARM_t2MRRC	= 2491,
  ARM_t2MRRC2	= 2492,
  ARM_t2MRS_AR	= 2493,
  ARM_t2MRS_M	= 2494,
  ARM_t2MRSsys_AR	= 2495,
  ARM_t2MSR_AR	= 2496,
  ARM_t2MSR_M	= 2497,
  ARM_t2MUL	= 2498,
  ARM_t2MVNCCi	= 2499,
  ARM_t2MVNi	= 2500,
  ARM_t2MVNr	= 2501,
  ARM_t2MVNs	= 2502,
  ARM_t2ORNri	= 2503,
  ARM_t2ORNrr	= 2504,
  ARM_t2ORNrs	= 2505,
  ARM_t2ORRri	= 2506,
  ARM_t2ORRrr	= 2507,
  ARM_t2ORRrs	= 2508,
  ARM_t2PKHBT	= 2509,
  ARM_t2PKHTB	= 2510,
  ARM_t2PLDWi12	= 2511,
  ARM_t2PLDWi8	= 2512,
  ARM_t2PLDWs	= 2513,
  ARM_t2PLDi12	= 2514,
  ARM_t2PLDi8	= 2515,
  ARM_t2PLDpci	= 2516,
  ARM_t2PLDs	= 2517,
  ARM_t2PLIi12	= 2518,
  ARM_t2PLIi8	= 2519,
  ARM_t2PLIpci	= 2520,
  ARM_t2PLIs	= 2521,
  ARM_t2QADD	= 2522,
  ARM_t2QADD16	= 2523,
  ARM_t2QADD8	= 2524,
  ARM_t2QASX	= 2525,
  ARM_t2QDADD	= 2526,
  ARM_t2QDSUB	= 2527,
  ARM_t2QSAX	= 2528,
  ARM_t2QSUB	= 2529,
  ARM_t2QSUB16	= 2530,
  ARM_t2QSUB8	= 2531,
  ARM_t2RBIT	= 2532,
  ARM_t2REV	= 2533,
  ARM_t2REV16	= 2534,
  ARM_t2REVSH	= 2535,
  ARM_t2RFEDB	= 2536,
  ARM_t2RFEDBW	= 2537,
  ARM_t2RFEIA	= 2538,
  ARM_t2RFEIAW	= 2539,
  ARM_t2RORri	= 2540,
  ARM_t2RORrr	= 2541,
  ARM_t2RRX	= 2542,
  ARM_t2RSBSri	= 2543,
  ARM_t2RSBSrs	= 2544,
  ARM_t2RSBri	= 2545,
  ARM_t2RSBrr	= 2546,
  ARM_t2RSBrs	= 2547,
  ARM_t2SADD16	= 2548,
  ARM_t2SADD8	= 2549,
  ARM_t2SASX	= 2550,
  ARM_t2SBCri	= 2551,
  ARM_t2SBCrr	= 2552,
  ARM_t2SBCrs	= 2553,
  ARM_t2SBFX	= 2554,
  ARM_t2SDIV	= 2555,
  ARM_t2SEL	= 2556,
  ARM_t2SHADD16	= 2557,
  ARM_t2SHADD8	= 2558,
  ARM_t2SHASX	= 2559,
  ARM_t2SHSAX	= 2560,
  ARM_t2SHSUB16	= 2561,
  ARM_t2SHSUB8	= 2562,
  ARM_t2SMC	= 2563,
  ARM_t2SMLABB	= 2564,
  ARM_t2SMLABT	= 2565,
  ARM_t2SMLAD	= 2566,
  ARM_t2SMLADX	= 2567,
  ARM_t2SMLAL	= 2568,
  ARM_t2SMLALBB	= 2569,
  ARM_t2SMLALBT	= 2570,
  ARM_t2SMLALD	= 2571,
  ARM_t2SMLALDX	= 2572,
  ARM_t2SMLALTB	= 2573,
  ARM_t2SMLALTT	= 2574,
  ARM_t2SMLATB	= 2575,
  ARM_t2SMLATT	= 2576,
  ARM_t2SMLAWB	= 2577,
  ARM_t2SMLAWT	= 2578,
  ARM_t2SMLSD	= 2579,
  ARM_t2SMLSDX	= 2580,
  ARM_t2SMLSLD	= 2581,
  ARM_t2SMLSLDX	= 2582,
  ARM_t2SMMLA	= 2583,
  ARM_t2SMMLAR	= 2584,
  ARM_t2SMMLS	= 2585,
  ARM_t2SMMLSR	= 2586,
  ARM_t2SMMUL	= 2587,
  ARM_t2SMMULR	= 2588,
  ARM_t2SMUAD	= 2589,
  ARM_t2SMUADX	= 2590,
  ARM_t2SMULBB	= 2591,
  ARM_t2SMULBT	= 2592,
  ARM_t2SMULL	= 2593,
  ARM_t2SMULTB	= 2594,
  ARM_t2SMULTT	= 2595,
  ARM_t2SMULWB	= 2596,
  ARM_t2SMULWT	= 2597,
  ARM_t2SMUSD	= 2598,
  ARM_t2SMUSDX	= 2599,
  ARM_t2SRSDB	= 2600,
  ARM_t2SRSDB_UPD	= 2601,
  ARM_t2SRSIA	= 2602,
  ARM_t2SRSIA_UPD	= 2603,
  ARM_t2SSAT	= 2604,
  ARM_t2SSAT16	= 2605,
  ARM_t2SSAX	= 2606,
  ARM_t2SSUB16	= 2607,
  ARM_t2SSUB8	= 2608,
  ARM_t2STC2L_OFFSET	= 2609,
  ARM_t2STC2L_OPTION	= 2610,
  ARM_t2STC2L_POST	= 2611,
  ARM_t2STC2L_PRE	= 2612,
  ARM_t2STC2_OFFSET	= 2613,
  ARM_t2STC2_OPTION	= 2614,
  ARM_t2STC2_POST	= 2615,
  ARM_t2STC2_PRE	= 2616,
  ARM_t2STCL_OFFSET	= 2617,
  ARM_t2STCL_OPTION	= 2618,
  ARM_t2STCL_POST	= 2619,
  ARM_t2STCL_PRE	= 2620,
  ARM_t2STC_OFFSET	= 2621,
  ARM_t2STC_OPTION	= 2622,
  ARM_t2STC_POST	= 2623,
  ARM_t2STC_PRE	= 2624,
  ARM_t2STL	= 2625,
  ARM_t2STLB	= 2626,
  ARM_t2STLEX	= 2627,
  ARM_t2STLEXB	= 2628,
  ARM_t2STLEXD	= 2629,
  ARM_t2STLEXH	= 2630,
  ARM_t2STLH	= 2631,
  ARM_t2STMDB	= 2632,
  ARM_t2STMDB_UPD	= 2633,
  ARM_t2STMIA	= 2634,
  ARM_t2STMIA_UPD	= 2635,
  ARM_t2STRBT	= 2636,
  ARM_t2STRB_POST	= 2637,
  ARM_t2STRB_PRE	= 2638,
  ARM_t2STRB_preidx	= 2639,
  ARM_t2STRBi12	= 2640,
  ARM_t2STRBi8	= 2641,
  ARM_t2STRBs	= 2642,
  ARM_t2STRD_POST	= 2643,
  ARM_t2STRD_PRE	= 2644,
  ARM_t2STRDi8	= 2645,
  ARM_t2STREX	= 2646,
  ARM_t2STREXB	= 2647,
  ARM_t2STREXD	= 2648,
  ARM_t2STREXH	= 2649,
  ARM_t2STRHT	= 2650,
  ARM_t2STRH_POST	= 2651,
  ARM_t2STRH_PRE	= 2652,
  ARM_t2STRH_preidx	= 2653,
  ARM_t2STRHi12	= 2654,
  ARM_t2STRHi8	= 2655,
  ARM_t2STRHs	= 2656,
  ARM_t2STRT	= 2657,
  ARM_t2STR_POST	= 2658,
  ARM_t2STR_PRE	= 2659,
  ARM_t2STR_preidx	= 2660,
  ARM_t2STRi12	= 2661,
  ARM_t2STRi8	= 2662,
  ARM_t2STRs	= 2663,
  ARM_t2SUBS_PC_LR	= 2664,
  ARM_t2SUBSri	= 2665,
  ARM_t2SUBSrr	= 2666,
  ARM_t2SUBSrs	= 2667,
  ARM_t2SUBri	= 2668,
  ARM_t2SUBri12	= 2669,
  ARM_t2SUBrr	= 2670,
  ARM_t2SUBrs	= 2671,
  ARM_t2SXTAB	= 2672,
  ARM_t2SXTAB16	= 2673,
  ARM_t2SXTAH	= 2674,
  ARM_t2SXTB	= 2675,
  ARM_t2SXTB16	= 2676,
  ARM_t2SXTH	= 2677,
  ARM_t2TBB	= 2678,
  ARM_t2TBB_JT	= 2679,
  ARM_t2TBH	= 2680,
  ARM_t2TBH_JT	= 2681,
  ARM_t2TEQri	= 2682,
  ARM_t2TEQrr	= 2683,
  ARM_t2TEQrs	= 2684,
  ARM_t2TSTri	= 2685,
  ARM_t2TSTrr	= 2686,
  ARM_t2TSTrs	= 2687,
  ARM_t2UADD16	= 2688,
  ARM_t2UADD8	= 2689,
  ARM_t2UASX	= 2690,
  ARM_t2UBFX	= 2691,
  ARM_t2UDIV	= 2692,
  ARM_t2UHADD16	= 2693,
  ARM_t2UHADD8	= 2694,
  ARM_t2UHASX	= 2695,
  ARM_t2UHSAX	= 2696,
  ARM_t2UHSUB16	= 2697,
  ARM_t2UHSUB8	= 2698,
  ARM_t2UMAAL	= 2699,
  ARM_t2UMLAL	= 2700,
  ARM_t2UMULL	= 2701,
  ARM_t2UQADD16	= 2702,
  ARM_t2UQADD8	= 2703,
  ARM_t2UQASX	= 2704,
  ARM_t2UQSAX	= 2705,
  ARM_t2UQSUB16	= 2706,
  ARM_t2UQSUB8	= 2707,
  ARM_t2USAD8	= 2708,
  ARM_t2USADA8	= 2709,
  ARM_t2USAT	= 2710,
  ARM_t2USAT16	= 2711,
  ARM_t2USAX	= 2712,
  ARM_t2USUB16	= 2713,
  ARM_t2USUB8	= 2714,
  ARM_t2UXTAB	= 2715,
  ARM_t2UXTAB16	= 2716,
  ARM_t2UXTAH	= 2717,
  ARM_t2UXTB	= 2718,
  ARM_t2UXTB16	= 2719,
  ARM_t2UXTH	= 2720,
  ARM_tADC	= 2721,
  ARM_tADDhirr	= 2722,
  ARM_tADDi3	= 2723,
  ARM_tADDi8	= 2724,
  ARM_tADDrSP	= 2725,
  ARM_tADDrSPi	= 2726,
  ARM_tADDrr	= 2727,
  ARM_tADDspi	= 2728,
  ARM_tADDspr	= 2729,
  ARM_tADJCALLSTACKDOWN	= 2730,
  ARM_tADJCALLSTACKUP	= 2731,
  ARM_tADR	= 2732,
  ARM_tAND	= 2733,
  ARM_tASRri	= 2734,
  ARM_tASRrr	= 2735,
  ARM_tB	= 2736,
  ARM_tBIC	= 2737,
  ARM_tBKPT	= 2738,
  ARM_tBL	= 2739,
  ARM_tBLXi	= 2740,
  ARM_tBLXr	= 2741,
  ARM_tBRIND	= 2742,
  ARM_tBR_JTr	= 2743,
  ARM_tBX	= 2744,
  ARM_tBX_CALL	= 2745,
  ARM_tBX_RET	= 2746,
  ARM_tBX_RET_vararg	= 2747,
  ARM_tBcc	= 2748,
  ARM_tBfar	= 2749,
  ARM_tCBNZ	= 2750,
  ARM_tCBZ	= 2751,
  ARM_tCMNz	= 2752,
  ARM_tCMPhir	= 2753,
  ARM_tCMPi8	= 2754,
  ARM_tCMPr	= 2755,
  ARM_tCPS	= 2756,
  ARM_tEOR	= 2757,
  ARM_tHINT	= 2758,
  ARM_tHLT	= 2759,
  ARM_tInt_eh_sjlj_longjmp	= 2760,
  ARM_tInt_eh_sjlj_setjmp	= 2761,
  ARM_tLDMIA	= 2762,
  ARM_tLDMIA_UPD	= 2763,
  ARM_tLDRBi	= 2764,
  ARM_tLDRBr	= 2765,
  ARM_tLDRHi	= 2766,
  ARM_tLDRHr	= 2767,
  ARM_tLDRSB	= 2768,
  ARM_tLDRSH	= 2769,
  ARM_tLDRi	= 2770,
  ARM_tLDRpci	= 2771,
  ARM_tLDRpci_pic	= 2772,
  ARM_tLDRr	= 2773,
  ARM_tLDRspi	= 2774,
  ARM_tLEApcrel	= 2775,
  ARM_tLEApcrelJT	= 2776,
  ARM_tLSLri	= 2777,
  ARM_tLSLrr	= 2778,
  ARM_tLSRri	= 2779,
  ARM_tLSRrr	= 2780,
  ARM_tMOVCCr_pseudo	= 2781,
  ARM_tMOVSr	= 2782,
  ARM_tMOVi8	= 2783,
  ARM_tMOVr	= 2784,
  ARM_tMUL	= 2785,
  ARM_tMVN	= 2786,
  ARM_tORR	= 2787,
  ARM_tPICADD	= 2788,
  ARM_tPOP	= 2789,
  ARM_tPOP_RET	= 2790,
  ARM_tPUSH	= 2791,
  ARM_tREV	= 2792,
  ARM_tREV16	= 2793,
  ARM_tREVSH	= 2794,
  ARM_tROR	= 2795,
  ARM_tRSB	= 2796,
  ARM_tSBC	= 2797,
  ARM_tSETEND	= 2798,
  ARM_tSTMIA_UPD	= 2799,
  ARM_tSTRBi	= 2800,
  ARM_tSTRBr	= 2801,
  ARM_tSTRHi	= 2802,
  ARM_tSTRHr	= 2803,
  ARM_tSTRi	= 2804,
  ARM_tSTRr	= 2805,
  ARM_tSTRspi	= 2806,
  ARM_tSUBi3	= 2807,
  ARM_tSUBi8	= 2808,
  ARM_tSUBrr	= 2809,
  ARM_tSUBspi	= 2810,
  ARM_tSVC	= 2811,
  ARM_tSXTB	= 2812,
  ARM_tSXTH	= 2813,
  ARM_tTAILJMPd	= 2814,
  ARM_tTAILJMPdND	= 2815,
  ARM_tTAILJMPr	= 2816,
  ARM_tTPsoft	= 2817,
  ARM_tTRAP	= 2818,
  ARM_tTST	= 2819,
  ARM_tUXTB	= 2820,
  ARM_tUXTH	= 2821,
  ARM_INSTRUCTION_LIST_END = 2822
};

#endif // GET_INSTRINFO_ENUM

/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|*                                                                            *|
|*Target Instruction Descriptors                                              *|
|*                                                                            *|
|* Automatically generated file, do not edit!                                 *|
|*                                                                            *|
\*===----------------------------------------------------------------------===*/


#ifdef GET_INSTRINFO_MC_DESC
#undef GET_INSTRINFO_MC_DESC

static  uint16_t ImplicitList1[] = { ARM_CPSR, 0 };
static  uint16_t ImplicitList2[] = { ARM_SP, 0 };
static  uint16_t ImplicitList3[] = { ARM_LR, 0 };
static  uint16_t ImplicitList4[] = { ARM_FPSCR_NZCV, 0 };
static  uint16_t ImplicitList5[] = { ARM_R7, ARM_LR, ARM_SP, 0 };
static  uint16_t ImplicitList6[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 0 };
static  uint16_t ImplicitList7[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, 0 };
static  uint16_t ImplicitList8[] = { ARM_R0, ARM_R12, ARM_LR, ARM_CPSR, 0 };
static  uint16_t ImplicitList9[] = { ARM_FPSCR, 0 };
static  uint16_t ImplicitList10[] = { ARM_ITSTATE, 0 };
static  uint16_t ImplicitList11[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 0 };
static uint16_t ImplicitList12[] = { ARM_PC, 0 };
static uint16_t ImplicitList13[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R12, ARM_CPSR, 0 };

static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo4[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo5[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo6[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo7[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo8[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo9[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo10[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo11[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo12[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo13[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo14[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo15[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo16[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo17[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo18[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo19[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo20[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo21[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo22[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo23[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo24[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo25[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo26[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo27[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo28[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo29[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo30[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo31[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo32[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo33[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo34[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo35[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo36[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo37[] = { { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo38[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo39[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo40[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo41[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo42[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo43[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo44[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo45[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo46[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo47[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo48[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo49[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo50[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo51[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo52[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo53[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo54[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo55[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo56[] = { { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo57[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo58[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo59[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo60[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo61[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo62[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo63[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo64[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo65[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo66[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo67[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo68[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo69[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo70[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo71[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo72[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo73[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo74[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo75[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo76[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo77[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo78[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo79[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo80[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo81[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo82[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo83[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo84[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo85[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo86[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo87[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo88[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo89[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo90[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo91[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo92[] = { { ARM_GPRwithAPSRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo93[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo94[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo95[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo96[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo97[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo98[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo99[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo100[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo101[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo102[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo103[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo104[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo105[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo106[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo107[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo108[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo109[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo110[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo111[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo112[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo113[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo114[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo115[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo116[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo117[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo118[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo119[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo120[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo121[] = { { ARM_tcGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo122[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo123[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo124[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo125[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo126[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo127[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo128[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo129[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo130[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo131[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo132[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo133[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo134[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo135[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo136[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo137[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo138[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo139[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo140[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo141[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo142[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo143[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo144[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo145[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo146[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo147[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo148[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo149[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo150[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo151[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo152[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo153[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo154[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo155[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo156[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo157[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo158[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo159[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo160[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo161[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo162[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo163[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo164[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo165[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo166[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo167[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo168[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo169[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo170[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo171[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo172[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo173[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo174[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo175[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo176[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo177[] = { { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo178[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo179[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo180[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo181[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo182[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo183[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo184[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo185[] = { { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo186[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo187[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo188[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo189[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((4 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((3 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo190[] = { { ARM_DPairRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo191[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo192[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo193[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo194[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo195[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo196[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo197[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo198[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo199[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo200[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo201[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo202[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo203[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo204[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo205[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo206[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo207[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo208[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo209[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo210[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo211[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo212[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo213[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo214[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo215[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_VFP2RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo216[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo217[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPR_8RegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo218[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo219[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo220[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo221[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo222[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo223[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo224[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo225[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo226[] = { { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_SPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo227[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo228[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo229[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo230[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo231[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo232[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo233[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo234[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo235[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo236[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo237[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo238[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo239[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo240[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo241[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo242[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo243[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo244[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo245[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo246[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo247[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo248[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo249[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo250[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo251[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo252[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo253[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo254[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_QQQQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo255[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo256[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo257[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo258[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo259[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo260[] = { { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo261[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo262[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo263[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo264[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo265[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_DPairRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo266[] = { { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_QQPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_DPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo267[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo268[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo269[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo270[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo271[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo272[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo273[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo274[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo275[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo276[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo277[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo278[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo279[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo280[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo281[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo282[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo283[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo284[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo285[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo286[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo287[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo288[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo289[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo290[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo291[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo292[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((2 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo293[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo294[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo295[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo296[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo297[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo298[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo299[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo300[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo301[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo302[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo303[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo304[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo305[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo306[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo307[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo308[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo309[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo310[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo311[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo312[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo313[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo314[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo315[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo316[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo317[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo318[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo319[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((1 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo320[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo321[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo322[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo323[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo324[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo325[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo326[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo327[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo328[] = { { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo329[] = { { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, (1 << MCOI_EARLY_CLOBBER) }, { ARM_GPRnopcRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo330[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_rGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo331[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo332[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo333[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo334[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo335[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo336[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo337[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo338[] = { { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRspRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo339[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo340[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo341[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, };
static MCOperandInfo OperandInfo342[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo343[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo344[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_PCREL, 0 }, };
static MCOperandInfo OperandInfo345[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo346[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo347[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo348[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo349[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo350[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo351[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo352[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo353[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo354[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo355[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo356[] = { { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_CCRRegClassID, 0|(1<<MCOI_OptionalDef), MCOI_OPERAND_UNKNOWN, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo357[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo358[] = { { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };
static MCOperandInfo OperandInfo359[] = { { ARM_GPRRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { ARM_tGPRRegClassID, 0, MCOI_OPERAND_REGISTER, ((0 << 16) | (1 << MCOI_TIED_TO)) }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0|(1<<MCOI_Predicate), MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, };

static MCInstrDesc ARMInsts[] = {
  { 0,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #0 = PHI
  { 1,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #1 = INLINEASM
  { 2,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #2 = PROLOG_LABEL
  { 3,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #3 = EH_LABEL
  { 4,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #4 = GC_LABEL
  { 5,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #5 = KILL
  { 6,	3,	1,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #6 = EXTRACT_SUBREG
  { 7,	4,	1,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo4,0,0 },  // Inst #7 = INSERT_SUBREG
  { 8,	1,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #8 = IMPLICIT_DEF
  { 9,	4,	1,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo6,0,0 },  // Inst #9 = SUBREG_TO_REG
  { 10,	3,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #10 = COPY_TO_REGCLASS
  { 11,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #11 = DBG_VALUE
  { 12,	1,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #12 = REG_SEQUENCE
  { 13,	2,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_CheapAsAMove), 0x0ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #13 = COPY
  { 14,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #14 = BUNDLE
  { 15,	1,	0,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #15 = LIFETIME_START
  { 16,	1,	0,	0,	0,	0|(1<<MCID_Pseudo), 0x0ULL, NULL, NULL, OperandInfo2,0,0 },  // Inst #16 = LIFETIME_END
  { 17,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo8,0,0 },  // Inst #17 = STACKMAP
  { 18,	6,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Call)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo9,0,0 },  // Inst #18 = PATCHPOINT
  { 19,	2,	1,	588,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo10,0,0 },  // Inst #19 = ABS
  { 20,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo11,0,0 },  // Inst #20 = ADCri
  { 21,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,0 },  // Inst #21 = ADCrr
  { 22,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,0 },  // Inst #22 = ADCrsi
  { 23,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,0 },  // Inst #23 = ADCrsr
  { 24,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo15,0,0 },  // Inst #24 = ADDSri
  { 25,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo16,0,0 },  // Inst #25 = ADDSrr
  { 26,	6,	1,	3,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo17,0,0 },  // Inst #26 = ADDSrsi
  { 27,	7,	1,	5,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo18,0,0 },  // Inst #27 = ADDSrsr
  { 28,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #28 = ADDri
  { 29,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #29 = ADDrr
  { 30,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #30 = ADDrsi
  { 31,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #31 = ADDrsr
  { 32,	3,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo20,0,0 },  // Inst #32 = ADJCALLSTACKDOWN
  { 33,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo21,0,0 },  // Inst #33 = ADJCALLSTACKUP
  { 34,	4,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xd01ULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #34 = ADR
  { 35,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #35 = AESD
  { 36,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #36 = AESE
  { 37,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #37 = AESIMC
  { 38,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #38 = AESMC
  { 39,	6,	1,	263,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #39 = ANDri
  { 40,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #40 = ANDrr
  { 41,	7,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #41 = ANDrsi
  { 42,	8,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #42 = ANDrsr
  { 43,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #43 = ASRi
  { 44,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #44 = ASRr
  { 45,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo26,0,0 },  // Inst #45 = ATOMIC_CMP_SWAP_I16
  { 46,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo26,0,0 },  // Inst #46 = ATOMIC_CMP_SWAP_I32
  { 47,	8,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo27,0,0 },  // Inst #47 = ATOMIC_CMP_SWAP_I64
  { 48,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo26,0,0 },  // Inst #48 = ATOMIC_CMP_SWAP_I8
  { 49,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #49 = ATOMIC_LOAD_ADD_I16
  { 50,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #50 = ATOMIC_LOAD_ADD_I32
  { 51,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #51 = ATOMIC_LOAD_ADD_I64
  { 52,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #52 = ATOMIC_LOAD_ADD_I8
  { 53,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #53 = ATOMIC_LOAD_AND_I16
  { 54,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #54 = ATOMIC_LOAD_AND_I32
  { 55,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #55 = ATOMIC_LOAD_AND_I64
  { 56,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #56 = ATOMIC_LOAD_AND_I8
  { 57,	4,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #57 = ATOMIC_LOAD_I64
  { 58,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #58 = ATOMIC_LOAD_MAX_I16
  { 59,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #59 = ATOMIC_LOAD_MAX_I32
  { 60,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #60 = ATOMIC_LOAD_MAX_I64
  { 61,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #61 = ATOMIC_LOAD_MAX_I8
  { 62,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #62 = ATOMIC_LOAD_MIN_I16
  { 63,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #63 = ATOMIC_LOAD_MIN_I32
  { 64,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #64 = ATOMIC_LOAD_MIN_I64
  { 65,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #65 = ATOMIC_LOAD_MIN_I8
  { 66,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #66 = ATOMIC_LOAD_NAND_I16
  { 67,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #67 = ATOMIC_LOAD_NAND_I32
  { 68,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #68 = ATOMIC_LOAD_NAND_I64
  { 69,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #69 = ATOMIC_LOAD_NAND_I8
  { 70,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #70 = ATOMIC_LOAD_OR_I16
  { 71,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #71 = ATOMIC_LOAD_OR_I32
  { 72,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #72 = ATOMIC_LOAD_OR_I64
  { 73,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #73 = ATOMIC_LOAD_OR_I8
  { 74,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #74 = ATOMIC_LOAD_SUB_I16
  { 75,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #75 = ATOMIC_LOAD_SUB_I32
  { 76,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #76 = ATOMIC_LOAD_SUB_I64
  { 77,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #77 = ATOMIC_LOAD_SUB_I8
  { 78,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #78 = ATOMIC_LOAD_UMAX_I16
  { 79,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #79 = ATOMIC_LOAD_UMAX_I32
  { 80,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #80 = ATOMIC_LOAD_UMAX_I64
  { 81,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #81 = ATOMIC_LOAD_UMAX_I8
  { 82,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #82 = ATOMIC_LOAD_UMIN_I16
  { 83,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #83 = ATOMIC_LOAD_UMIN_I32
  { 84,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #84 = ATOMIC_LOAD_UMIN_I64
  { 85,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #85 = ATOMIC_LOAD_UMIN_I8
  { 86,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #86 = ATOMIC_LOAD_XOR_I16
  { 87,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #87 = ATOMIC_LOAD_XOR_I32
  { 88,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #88 = ATOMIC_LOAD_XOR_I64
  { 89,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #89 = ATOMIC_LOAD_XOR_I8
  { 90,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #90 = ATOMIC_STORE_I64
  { 91,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #91 = ATOMIC_SWAP_I16
  { 92,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #92 = ATOMIC_SWAP_I32
  { 93,	6,	2,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo29,0,0 },  // Inst #93 = ATOMIC_SWAP_I64
  { 94,	4,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo28,0,0 },  // Inst #94 = ATOMIC_SWAP_I8
  { 95,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo30,0,0 },  // Inst #95 = B
  { 96,	4,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo31,0,0 },  // Inst #96 = BCCZi64
  { 97,	6,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, ImplicitList1, OperandInfo32,0,0 },  // Inst #97 = BCCi64
  { 98,	5,	1,	277,	4,	0|(1<<MCID_Predicable), 0x201ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #98 = BFC
  { 99,	6,	1,	277,	4,	0|(1<<MCID_Predicable), 0x201ULL, NULL, NULL, OperandInfo34,0,0 },  // Inst #99 = BFI
  { 100,	6,	1,	263,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #100 = BICri
  { 101,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #101 = BICrr
  { 102,	7,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #102 = BICrsi
  { 103,	8,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #103 = BICrsr
  { 104,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #104 = BKPT
  { 105,	1,	0,	12,	4,	0|(1<<MCID_Call), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo30,0,0 },  // Inst #105 = BL
  { 106,	1,	0,	12,	4,	0|(1<<MCID_Call), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo35,0,0 },  // Inst #106 = BLX
  { 107,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x180ULL, ImplicitList2, ImplicitList3, OperandInfo36,0,0 },  // Inst #107 = BLX_pred
  { 108,	1,	0,	13,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x180ULL, NULL, NULL, OperandInfo30,0,0 },  // Inst #108 = BLXi
  { 109,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0x100ULL, ImplicitList2, ImplicitList3, OperandInfo37,0,0 },  // Inst #109 = BL_pred
  { 110,	1,	0,	10,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo30,0,0 },  // Inst #110 = BMOVPCB_CALL
  { 111,	1,	0,	10,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo38,0,0 },  // Inst #111 = BMOVPCRX_CALL
  { 112,	4,	0,	14,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo39,0,0 },  // Inst #112 = BR_JTadd
  { 113,	5,	0,	14,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo40,0,0 },  // Inst #113 = BR_JTm
  { 114,	3,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo41,0,0 },  // Inst #114 = BR_JTr
  { 115,	1,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x180ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #115 = BX
  { 116,	3,	0,	15,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #116 = BXJ
  { 117,	1,	0,	10,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo38,0,0 },  // Inst #117 = BX_CALL
  { 118,	2,	0,	10,	4,	0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #118 = BX_RET
  { 119,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x180ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #119 = BX_pred
  { 120,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #120 = Bcc
  { 121,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo43,0,0 },  // Inst #121 = CDP
  { 122,	6,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo44,0,0 },  // Inst #122 = CDP2
  { 123,	0,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, 0,0,0 },  // Inst #123 = CLREX
  { 124,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #124 = CLZ
  { 125,	4,	0,	17,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #125 = CMNri
  { 126,	4,	0,	18,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #126 = CMNzrr
  { 127,	5,	0,	19,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #127 = CMNzrsi
  { 128,	6,	0,	20,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #128 = CMNzrsr
  { 129,	4,	0,	17,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #129 = CMPri
  { 130,	4,	0,	18,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #130 = CMPrr
  { 131,	5,	0,	19,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #131 = CMPrsi
  { 132,	6,	0,	20,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #132 = CMPrsr
  { 133,	3,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #133 = CONSTPOOL_ENTRY
  { 134,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo39,0,0 },  // Inst #134 = COPY_STRUCT_BYVAL_I32
  { 135,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #135 = CPS1p
  { 136,	2,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #136 = CPS2p
  { 137,	3,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo48,0,0 },  // Inst #137 = CPS3p
  { 138,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #138 = CRC32B
  { 139,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #139 = CRC32CB
  { 140,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #140 = CRC32CH
  { 141,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #141 = CRC32CW
  { 142,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #142 = CRC32H
  { 143,	3,	1,	0,	4,	0, 0xd00ULL, NULL, NULL, OperandInfo49,0,0 },  // Inst #143 = CRC32W
  { 144,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #144 = DBG
  { 145,	1,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #145 = DMB
  { 146,	1,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #146 = DSB
  { 147,	6,	1,	263,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #147 = EORri
  { 148,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #148 = EORrr
  { 149,	7,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #149 = EORrsi
  { 150,	8,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #150 = EORrsr
  { 151,	4,	1,	485,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #151 = FCONSTD
  { 152,	4,	1,	486,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x8c00ULL, NULL, NULL, OperandInfo52,0,0 },  // Inst #152 = FCONSTS
  { 153,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #153 = FLDMXDB_UPD
  { 154,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #154 = FLDMXIA
  { 155,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #155 = FLDMXIA_UPD
  { 156,	2,	0,	505,	4,	0|(1<<MCID_Predicable), 0x8c00ULL, ImplicitList4, ImplicitList1, OperandInfo42,0,0 },  // Inst #156 = FMSTAT
  { 157,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #157 = FSTMXDB_UPD
  { 158,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b04ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #158 = FSTMXIA
  { 159,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects), 0x8b64ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #159 = FSTMXIA_UPD
  { 160,	3,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #160 = HINT
  { 161,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #161 = HLT
  { 162,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #162 = ISB
  { 163,	2,	0,	375,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #163 = ITasm
  { 164,	0,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, 0,0,0 },  // Inst #164 = Int_eh_sjlj_dispatchsetup
  { 165,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList5, OperandInfo10,0,0 },  // Inst #165 = Int_eh_sjlj_longjmp
  { 166,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList6, OperandInfo10,0,0 },  // Inst #166 = Int_eh_sjlj_setjmp
  { 167,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList7, OperandInfo10,0,0 },  // Inst #167 = Int_eh_sjlj_setjmp_nofp
  { 168,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #168 = LDA
  { 169,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #169 = LDAB
  { 170,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #170 = LDAEX
  { 171,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #171 = LDAEXB
  { 172,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo56,0,0 },  // Inst #172 = LDAEXD
  { 173,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #173 = LDAEXH
  { 174,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #174 = LDAH
  { 175,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #175 = LDC2L_OFFSET
  { 176,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #176 = LDC2L_OPTION
  { 177,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #177 = LDC2L_POST
  { 178,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #178 = LDC2L_PRE
  { 179,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #179 = LDC2_OFFSET
  { 180,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #180 = LDC2_OPTION
  { 181,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #181 = LDC2_POST
  { 182,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #182 = LDC2_PRE
  { 183,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #183 = LDCL_OFFSET
  { 184,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #184 = LDCL_OPTION
  { 185,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #185 = LDCL_POST
  { 186,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #186 = LDCL_PRE
  { 187,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #187 = LDC_OFFSET
  { 188,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #188 = LDC_OPTION
  { 189,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #189 = LDC_POST
  { 190,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #190 = LDC_PRE
  { 191,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #191 = LDMDA
  { 192,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #192 = LDMDA_UPD
  { 193,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #193 = LDMDB
  { 194,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #194 = LDMDB_UPD
  { 195,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #195 = LDMIA
  { 196,	5,	1,	354,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #196 = LDMIA_RET
  { 197,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #197 = LDMIA_UPD
  { 198,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #198 = LDMIB
  { 199,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #199 = LDMIB_UPD
  { 200,	7,	2,	340,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #200 = LDRBT_POST_IMM
  { 201,	7,	2,	340,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #201 = LDRBT_POST_REG
  { 202,	7,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #202 = LDRB_POST_IMM
  { 203,	7,	2,	340,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #203 = LDRB_POST_REG
  { 204,	6,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #204 = LDRB_PRE_IMM
  { 205,	7,	2,	340,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #205 = LDRB_PRE_REG
  { 206,	5,	1,	324,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, NULL, NULL, OperandInfo61,0,0 },  // Inst #206 = LDRBi12
  { 207,	6,	1,	325,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, NULL, NULL, OperandInfo62,0,0 },  // Inst #207 = LDRBrs
  { 208,	7,	2,	349,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x403ULL, NULL, NULL, OperandInfo63,0,0 },  // Inst #208 = LDRD
  { 209,	8,	3,	351,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x443ULL, NULL, NULL, OperandInfo64,0,0 },  // Inst #209 = LDRD_POST
  { 210,	8,	3,	351,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x423ULL, NULL, NULL, OperandInfo64,0,0 },  // Inst #210 = LDRD_PRE
  { 211,	4,	1,	326,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #211 = LDREX
  { 212,	4,	1,	326,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #212 = LDREXB
  { 213,	4,	1,	326,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo56,0,0 },  // Inst #213 = LDREXD
  { 214,	4,	1,	326,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #214 = LDREXH
  { 215,	6,	1,	334,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, NULL, NULL, OperandInfo65,0,0 },  // Inst #215 = LDRH
  { 216,	6,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #216 = LDRHTi
  { 217,	7,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo66,0,0 },  // Inst #217 = LDRHTr
  { 218,	7,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #218 = LDRH_POST
  { 219,	7,	2,	342,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #219 = LDRH_PRE
  { 220,	6,	1,	287,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, NULL, NULL, OperandInfo65,0,0 },  // Inst #220 = LDRSB
  { 221,	6,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #221 = LDRSBTi
  { 222,	7,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo66,0,0 },  // Inst #222 = LDRSBTr
  { 223,	7,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #223 = LDRSB_POST
  { 224,	7,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #224 = LDRSB_PRE
  { 225,	6,	1,	287,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x403ULL, NULL, NULL, OperandInfo65,0,0 },  // Inst #225 = LDRSH
  { 226,	6,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #226 = LDRSHTi
  { 227,	7,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo66,0,0 },  // Inst #227 = LDRSHTr
  { 228,	7,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x443ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #228 = LDRSH_POST
  { 229,	7,	2,	288,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x423ULL, NULL, NULL, OperandInfo67,0,0 },  // Inst #229 = LDRSH_PRE
  { 230,	7,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #230 = LDRT_POST_IMM
  { 231,	7,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #231 = LDRT_POST_REG
  { 232,	7,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #232 = LDR_POST_IMM
  { 233,	7,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x342ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #233 = LDR_POST_REG
  { 234,	6,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #234 = LDR_PRE_IMM
  { 235,	7,	2,	343,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x322ULL, NULL, NULL, OperandInfo59,0,0 },  // Inst #235 = LDR_PRE_REG
  { 236,	5,	1,	335,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #236 = LDRcp
  { 237,	5,	1,	327,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x310ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #237 = LDRi12
  { 238,	6,	1,	286,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x300ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #238 = LDRrs
  { 239,	4,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo69,0,0 },  // Inst #239 = LEApcrel
  { 240,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo70,0,0 },  // Inst #240 = LEApcrelJT
  { 241,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #241 = LSLi
  { 242,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #242 = LSLr
  { 243,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #243 = LSRi
  { 244,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #244 = LSRr
  { 245,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo71,0,0 },  // Inst #245 = MCR
  { 246,	6,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo72,0,0 },  // Inst #246 = MCR2
  { 247,	7,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo73,0,0 },  // Inst #247 = MCRR
  { 248,	5,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo74,0,0 },  // Inst #248 = MCRR2
  { 249,	7,	1,	278,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo75,0,0 },  // Inst #249 = MLA
  { 250,	7,	1,	278,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo76,0,0 },  // Inst #250 = MLAv5
  { 251,	6,	1,	278,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #251 = MLS
  { 252,	5,	1,	38,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #252 = MOVCCi
  { 253,	5,	1,	39,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #253 = MOVCCi16
  { 254,	5,	1,	272,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo78,0,0 },  // Inst #254 = MOVCCi32imm
  { 255,	5,	1,	41,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #255 = MOVCCr
  { 256,	6,	1,	267,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo80,0,0 },  // Inst #256 = MOVCCsi
  { 257,	7,	1,	267,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo81,0,0 },  // Inst #257 = MOVCCsr
  { 258,	2,	0,	10,	4,	0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x180ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #258 = MOVPCLR
  { 259,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #259 = MOVPCRX
  { 260,	5,	1,	39,	4,	0|(1<<MCID_Predicable), 0x2201ULL, NULL, NULL, OperandInfo82,0,0 },  // Inst #260 = MOVTi16
  { 261,	4,	1,	39,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo83,0,0 },  // Inst #261 = MOVTi16_ga_pcrel
  { 262,	2,	1,	274,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo84,0,0 },  // Inst #262 = MOV_ga_pcrel
  { 263,	2,	1,	275,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo84,0,0 },  // Inst #263 = MOV_ga_pcrel_ldr
  { 264,	5,	1,	39,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, NULL, NULL, OperandInfo85,0,0 },  // Inst #264 = MOVi
  { 265,	4,	1,	39,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0x2201ULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #265 = MOVi16
  { 266,	3,	1,	39,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo86,0,0 },  // Inst #266 = MOVi16_ga_pcrel
  { 267,	2,	1,	273,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo84,0,0 },  // Inst #267 = MOVi32imm
  { 268,	5,	1,	46,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, NULL, NULL, OperandInfo87,0,0 },  // Inst #268 = MOVr
  { 269,	5,	1,	46,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, NULL, NULL, OperandInfo88,0,0 },  // Inst #269 = MOVr_TC
  { 270,	6,	1,	268,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, NULL, NULL, OperandInfo89,0,0 },  // Inst #270 = MOVsi
  { 271,	7,	1,	268,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, NULL, NULL, OperandInfo90,0,0 },  // Inst #271 = MOVsr
  { 272,	2,	1,	269,	0,	0|(1<<MCID_Pseudo), 0x2000ULL, NULL, ImplicitList1, OperandInfo10,0,0 },  // Inst #272 = MOVsra_flag
  { 273,	2,	1,	269,	0,	0|(1<<MCID_Pseudo), 0x2000ULL, NULL, ImplicitList1, OperandInfo10,0,0 },  // Inst #273 = MOVsrl_flag
  { 274,	8,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo91,0,0 },  // Inst #274 = MRC
  { 275,	6,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo92,0,0 },  // Inst #275 = MRC2
  { 276,	7,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo73,0,0 },  // Inst #276 = MRRC
  { 277,	5,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo74,0,0 },  // Inst #277 = MRRC2
  { 278,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo93,0,0 },  // Inst #278 = MRS
  { 279,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo93,0,0 },  // Inst #279 = MRSsys
  { 280,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo94,0,0 },  // Inst #280 = MSR
  { 281,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo95,0,0 },  // Inst #281 = MSRi
  { 282,	6,	1,	279,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #282 = MUL
  { 283,	6,	1,	279,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo96,0,0 },  // Inst #283 = MULv5
  { 284,	5,	1,	38,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo33,0,0 },  // Inst #284 = MVNCCi
  { 285,	5,	1,	50,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0x2201ULL, NULL, NULL, OperandInfo85,0,0 },  // Inst #285 = MVNi
  { 286,	5,	1,	271,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2201ULL, NULL, NULL, OperandInfo87,0,0 },  // Inst #286 = MVNr
  { 287,	6,	1,	52,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x3501ULL, NULL, NULL, OperandInfo89,0,0 },  // Inst #287 = MVNsi
  { 288,	7,	1,	270,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x2281ULL, NULL, NULL, OperandInfo97,0,0 },  // Inst #288 = MVNsr
  { 289,	6,	1,	263,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #289 = ORRri
  { 290,	6,	1,	264,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #290 = ORRrr
  { 291,	7,	1,	265,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #291 = ORRrsi
  { 292,	8,	1,	266,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #292 = ORRrsr
  { 293,	5,	1,	53,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo15,0,0 },  // Inst #293 = PICADD
  { 294,	5,	1,	285,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #294 = PICLDR
  { 295,	5,	1,	334,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #295 = PICLDRB
  { 296,	5,	1,	334,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #296 = PICLDRH
  { 297,	5,	1,	287,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #297 = PICLDRSB
  { 298,	5,	1,	287,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #298 = PICLDRSH
  { 299,	5,	0,	357,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #299 = PICSTR
  { 300,	5,	0,	358,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #300 = PICSTRB
  { 301,	5,	0,	358,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #301 = PICSTRH
  { 302,	6,	1,	56,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo98,0,0 },  // Inst #302 = PKHBT
  { 303,	6,	1,	57,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo98,0,0 },  // Inst #303 = PKHTB
  { 304,	2,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo99,0,0 },  // Inst #304 = PLDWi12
  { 305,	3,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo100,0,0 },  // Inst #305 = PLDWrs
  { 306,	2,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo99,0,0 },  // Inst #306 = PLDi12
  { 307,	3,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo100,0,0 },  // Inst #307 = PLDrs
  { 308,	2,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo99,0,0 },  // Inst #308 = PLIi12
  { 309,	3,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore), 0xd00ULL, NULL, NULL, OperandInfo100,0,0 },  // Inst #309 = PLIrs
  { 310,	5,	1,	298,	4,	0|(1<<MCID_Predicable), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #310 = QADD
  { 311,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #311 = QADD16
  { 312,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #312 = QADD8
  { 313,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #313 = QASX
  { 314,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #314 = QDADD
  { 315,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #315 = QDSUB
  { 316,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #316 = QSAX
  { 317,	5,	1,	298,	4,	0|(1<<MCID_Predicable), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #317 = QSUB
  { 318,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #318 = QSUB16
  { 319,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #319 = QSUB8
  { 320,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #320 = RBIT
  { 321,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #321 = REV
  { 322,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #322 = REV16
  { 323,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #323 = REVSH
  { 324,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #324 = RFEDA
  { 325,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #325 = RFEDA_UPD
  { 326,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #326 = RFEDB
  { 327,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #327 = RFEDB_UPD
  { 328,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #328 = RFEIA
  { 329,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #329 = RFEIA_UPD
  { 330,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #330 = RFEIB
  { 331,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo35,0,0 },  // Inst #331 = RFEIB_UPD
  { 332,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #332 = RORi
  { 333,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo25,0,0 },  // Inst #333 = RORr
  { 334,	2,	1,	48,	0,	0|(1<<MCID_Pseudo), 0x2000ULL, ImplicitList1, NULL, OperandInfo10,0,0 },  // Inst #334 = RRX
  { 335,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo87,0,0 },  // Inst #335 = RRXi
  { 336,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo15,0,0 },  // Inst #336 = RSBSri
  { 337,	6,	1,	3,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo17,0,0 },  // Inst #337 = RSBSrsi
  { 338,	7,	1,	5,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo18,0,0 },  // Inst #338 = RSBSrsr
  { 339,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #339 = RSBri
  { 340,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #340 = RSBrr
  { 341,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #341 = RSBrsi
  { 342,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #342 = RSBrsr
  { 343,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo11,0,0 },  // Inst #343 = RSCri
  { 344,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,0 },  // Inst #344 = RSCrr
  { 345,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,0 },  // Inst #345 = RSCrsi
  { 346,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo19,0,0 },  // Inst #346 = RSCrsr
  { 347,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #347 = SADD16
  { 348,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #348 = SADD8
  { 349,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #349 = SASX
  { 350,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo11,0,0 },  // Inst #350 = SBCri
  { 351,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo12,0,0 },  // Inst #351 = SBCrr
  { 352,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo13,0,0 },  // Inst #352 = SBCrsi
  { 353,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo14,0,0 },  // Inst #353 = SBCrsr
  { 354,	6,	1,	277,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, NULL, NULL, OperandInfo102,0,0 },  // Inst #354 = SBFX
  { 355,	5,	1,	323,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #355 = SDIV
  { 356,	5,	1,	276,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #356 = SEL
  { 357,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo5,ARM_HasV8Ops,0 },  // Inst #357 = SETEND
  { 358,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #358 = SHA1C
  { 359,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #359 = SHA1H
  { 360,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #360 = SHA1M
  { 361,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #361 = SHA1P
  { 362,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #362 = SHA1SU0
  { 363,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #363 = SHA1SU1
  { 364,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #364 = SHA256H
  { 365,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #365 = SHA256H2
  { 366,	3,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo23,0,0 },  // Inst #366 = SHA256SU0
  { 367,	4,	1,	0,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo103,0,0 },  // Inst #367 = SHA256SU1
  { 368,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #368 = SHADD16
  { 369,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #369 = SHADD8
  { 370,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #370 = SHASX
  { 371,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #371 = SHSAX
  { 372,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #372 = SHSUB16
  { 373,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #373 = SHSUB8
  { 374,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #374 = SMC
  { 375,	6,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #375 = SMLABB
  { 376,	6,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #376 = SMLABT
  { 377,	6,	1,	318,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #377 = SMLAD
  { 378,	6,	1,	318,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #378 = SMLADX
  { 379,	9,	2,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #379 = SMLAL
  { 380,	6,	2,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #380 = SMLALBB
  { 381,	6,	2,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #381 = SMLALBT
  { 382,	6,	2,	282,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #382 = SMLALD
  { 383,	6,	2,	282,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #383 = SMLALDX
  { 384,	6,	2,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #384 = SMLALTB
  { 385,	6,	2,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #385 = SMLALTT
  { 386,	9,	2,	280,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #386 = SMLALv5
  { 387,	6,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #387 = SMLATB
  { 388,	6,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #388 = SMLATT
  { 389,	6,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #389 = SMLAWB
  { 390,	6,	1,	284,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #390 = SMLAWT
  { 391,	6,	1,	315,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #391 = SMLSD
  { 392,	6,	1,	315,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo104,0,0 },  // Inst #392 = SMLSDX
  { 393,	6,	2,	282,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #393 = SMLSLD
  { 394,	6,	2,	282,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo106,0,0 },  // Inst #394 = SMLSLDX
  { 395,	6,	1,	278,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #395 = SMMLA
  { 396,	6,	1,	278,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #396 = SMMLAR
  { 397,	6,	1,	278,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #397 = SMMLS
  { 398,	6,	1,	278,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #398 = SMMLSR
  { 399,	5,	1,	279,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #399 = SMMUL
  { 400,	5,	1,	279,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #400 = SMMULR
  { 401,	5,	1,	313,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #401 = SMUAD
  { 402,	5,	1,	313,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #402 = SMUADX
  { 403,	5,	1,	283,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #403 = SMULBB
  { 404,	5,	1,	283,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #404 = SMULBT
  { 405,	7,	2,	320,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo75,0,0 },  // Inst #405 = SMULL
  { 406,	7,	2,	281,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #406 = SMULLv5
  { 407,	5,	1,	283,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #407 = SMULTB
  { 408,	5,	1,	283,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #408 = SMULTT
  { 409,	5,	1,	283,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #409 = SMULWB
  { 410,	5,	1,	283,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #410 = SMULWT
  { 411,	5,	1,	308,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #411 = SMUSD
  { 412,	5,	1,	308,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #412 = SMUSDX
  { 413,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #413 = SRSDA
  { 414,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #414 = SRSDA_UPD
  { 415,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #415 = SRSDB
  { 416,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #416 = SRSDB_UPD
  { 417,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #417 = SRSIA
  { 418,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #418 = SRSIA_UPD
  { 419,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #419 = SRSIB
  { 420,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #420 = SRSIB_UPD
  { 421,	6,	1,	299,	4,	0|(1<<MCID_Predicable), 0x680ULL, NULL, NULL, OperandInfo108,0,0 },  // Inst #421 = SSAT
  { 422,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, NULL, NULL, OperandInfo109,0,0 },  // Inst #422 = SSAT16
  { 423,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #423 = SSAX
  { 424,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #424 = SSUB16
  { 425,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #425 = SSUB8
  { 426,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #426 = STC2L_OFFSET
  { 427,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #427 = STC2L_OPTION
  { 428,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #428 = STC2L_POST
  { 429,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #429 = STC2L_PRE
  { 430,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #430 = STC2_OFFSET
  { 431,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #431 = STC2_OPTION
  { 432,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #432 = STC2_POST
  { 433,	4,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo57,0,0 },  // Inst #433 = STC2_PRE
  { 434,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #434 = STCL_OFFSET
  { 435,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #435 = STCL_OPTION
  { 436,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #436 = STCL_POST
  { 437,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #437 = STCL_PRE
  { 438,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #438 = STC_OFFSET
  { 439,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #439 = STC_OPTION
  { 440,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x140ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #440 = STC_POST
  { 441,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x120ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #441 = STC_PRE
  { 442,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #442 = STL
  { 443,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #443 = STLB
  { 444,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #444 = STLEX
  { 445,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #445 = STLEXB
  { 446,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo111,0,0 },  // Inst #446 = STLEXD
  { 447,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #447 = STLEXH
  { 448,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x580ULL, NULL, NULL, OperandInfo55,0,0 },  // Inst #448 = STLH
  { 449,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #449 = STMDA
  { 450,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #450 = STMDA_UPD
  { 451,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #451 = STMDB
  { 452,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #452 = STMDB_UPD
  { 453,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #453 = STMIA
  { 454,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #454 = STMIA_UPD
  { 455,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #455 = STMIB
  { 456,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #456 = STMIB_UPD
  { 457,	7,	1,	364,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #457 = STRBT_POST_IMM
  { 458,	7,	1,	364,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #458 = STRBT_POST_REG
  { 459,	7,	1,	365,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #459 = STRB_POST_IMM
  { 460,	7,	1,	364,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #460 = STRB_POST_REG
  { 461,	6,	1,	365,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo113,0,0 },  // Inst #461 = STRB_PRE_IMM
  { 462,	7,	1,	364,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #462 = STRB_PRE_REG
  { 463,	5,	0,	358,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, NULL, NULL, OperandInfo61,0,0 },  // Inst #463 = STRBi12
  { 464,	7,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #464 = STRBi_preidx
  { 465,	7,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #465 = STRBr_preidx
  { 466,	6,	0,	359,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, NULL, NULL, OperandInfo62,0,0 },  // Inst #466 = STRBrs
  { 467,	7,	0,	370,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x483ULL, NULL, NULL, OperandInfo63,0,0 },  // Inst #467 = STRD
  { 468,	8,	1,	371,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4c3ULL, NULL, NULL, OperandInfo115,0,0 },  // Inst #468 = STRD_POST
  { 469,	8,	1,	371,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x4a3ULL, NULL, NULL, OperandInfo115,0,0 },  // Inst #469 = STRD_PRE
  { 470,	5,	1,	360,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #470 = STREX
  { 471,	5,	1,	360,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #471 = STREXB
  { 472,	5,	1,	360,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x580ULL, NULL, NULL, OperandInfo111,0,0 },  // Inst #472 = STREXD
  { 473,	5,	1,	360,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x580ULL, NULL, NULL, OperandInfo110,0,0 },  // Inst #473 = STREXH
  { 474,	6,	0,	358,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x483ULL, NULL, NULL, OperandInfo65,0,0 },  // Inst #474 = STRH
  { 475,	6,	1,	364,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, NULL, NULL, OperandInfo113,0,0 },  // Inst #475 = STRHTi
  { 476,	7,	1,	364,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4c3ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #476 = STRHTr
  { 477,	7,	1,	364,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x4c3ULL, NULL, NULL, OperandInfo116,0,0 },  // Inst #477 = STRH_POST
  { 478,	7,	1,	364,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x4a3ULL, NULL, NULL, OperandInfo116,0,0 },  // Inst #478 = STRH_PRE
  { 479,	7,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo117,0,0 },  // Inst #479 = STRH_preidx
  { 480,	7,	1,	366,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #480 = STRT_POST_IMM
  { 481,	7,	1,	366,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #481 = STRT_POST_REG
  { 482,	7,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #482 = STR_POST_IMM
  { 483,	7,	1,	366,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3c2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #483 = STR_POST_REG
  { 484,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo113,0,0 },  // Inst #484 = STR_PRE_IMM
  { 485,	7,	1,	366,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x3a2ULL, NULL, NULL, OperandInfo112,0,0 },  // Inst #485 = STR_PRE_REG
  { 486,	5,	0,	357,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x390ULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #486 = STRi12
  { 487,	7,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #487 = STRi_preidx
  { 488,	7,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo114,0,0 },  // Inst #488 = STRr_preidx
  { 489,	6,	0,	361,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x380ULL, NULL, NULL, OperandInfo68,0,0 },  // Inst #489 = STRrs
  { 490,	3,	0,	74,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo20,0,0 },  // Inst #490 = SUBS_PC_LR
  { 491,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo15,0,0 },  // Inst #491 = SUBSri
  { 492,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo16,0,0 },  // Inst #492 = SUBSrr
  { 493,	6,	1,	3,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo17,0,0 },  // Inst #493 = SUBSrsi
  { 494,	7,	1,	5,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo18,0,0 },  // Inst #494 = SUBSrsr
  { 495,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo11,0,0 },  // Inst #495 = SUBri
  { 496,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x201ULL, NULL, NULL, OperandInfo12,0,0 },  // Inst #496 = SUBrr
  { 497,	7,	1,	3,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x1501ULL, NULL, NULL, OperandInfo13,0,0 },  // Inst #497 = SUBrsi
  { 498,	8,	1,	4,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x281ULL, NULL, NULL, OperandInfo19,0,0 },  // Inst #498 = SUBrsr
  { 499,	3,	0,	10,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x100ULL, ImplicitList2, NULL, OperandInfo50,0,0 },  // Inst #499 = SVC
  { 500,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo118,0,0 },  // Inst #500 = SWP
  { 501,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, OperandInfo118,0,0 },  // Inst #501 = SWPB
  { 502,	6,	1,	303,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo119,0,0 },  // Inst #502 = SXTAB
  { 503,	6,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, NULL, NULL, OperandInfo119,0,0 },  // Inst #503 = SXTAB16
  { 504,	6,	1,	303,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo119,0,0 },  // Inst #504 = SXTAH
  { 505,	5,	1,	289,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #505 = SXTB
  { 506,	5,	1,	289,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #506 = SXTB16
  { 507,	5,	1,	289,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #507 = SXTH
  { 508,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo30,0,0 },  // Inst #508 = TAILJMPd
  { 509,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo121,0,0 },  // Inst #509 = TAILJMPr
  { 510,	1,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, NULL, OperandInfo2,0,0 },  // Inst #510 = TCRETURNdi
  { 511,	1,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator), 0x0ULL, ImplicitList2, NULL, OperandInfo121,0,0 },  // Inst #511 = TCRETURNri
  { 512,	4,	0,	77,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #512 = TEQri
  { 513,	4,	0,	78,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #513 = TEQrr
  { 514,	5,	0,	79,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #514 = TEQrsi
  { 515,	6,	0,	80,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #515 = TEQrsr
  { 516,	0,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, 0,0,0 },  // Inst #516 = TPsoft
  { 517,	0,	0,	0,	4,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, 0,0,0 },  // Inst #517 = TRAP
  { 518,	0,	0,	0,	4,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xd00ULL, NULL, NULL, 0,0,0 },  // Inst #518 = TRAPNaCl
  { 519,	4,	0,	77,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x201ULL, NULL, ImplicitList1, OperandInfo22,0,0 },  // Inst #519 = TSTri
  { 520,	4,	0,	78,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x201ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #520 = TSTrr
  { 521,	5,	0,	79,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x1501ULL, NULL, ImplicitList1, OperandInfo46,0,0 },  // Inst #521 = TSTrsi
  { 522,	6,	0,	80,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0x281ULL, NULL, ImplicitList1, OperandInfo47,0,0 },  // Inst #522 = TSTrsr
  { 523,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #523 = UADD16
  { 524,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #524 = UADD8
  { 525,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #525 = UASX
  { 526,	6,	1,	277,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x201ULL, NULL, NULL, OperandInfo122,0,0 },  // Inst #526 = UBFX
  { 527,	5,	1,	323,	4,	0|(1<<MCID_Predicable), 0x600ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #527 = UDIV
  { 528,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #528 = UHADD16
  { 529,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #529 = UHADD8
  { 530,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #530 = UHASX
  { 531,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #531 = UHSAX
  { 532,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #532 = UHSUB16
  { 533,	5,	1,	302,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #533 = UHSUB8
  { 534,	6,	2,	280,	4,	0|(1<<MCID_Predicable), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #534 = UMAAL
  { 535,	6,	2,	280,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo123,0,0 },  // Inst #535 = UMAALv5
  { 536,	9,	2,	280,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #536 = UMLAL
  { 537,	9,	2,	280,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo105,0,0 },  // Inst #537 = UMLALv5
  { 538,	7,	2,	320,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x80ULL, NULL, NULL, OperandInfo75,0,0 },  // Inst #538 = UMULL
  { 539,	7,	2,	281,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x0ULL, NULL, NULL, OperandInfo107,0,0 },  // Inst #539 = UMULLv5
  { 540,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #540 = UQADD16
  { 541,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #541 = UQADD8
  { 542,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #542 = UQASX
  { 543,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #543 = UQSAX
  { 544,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #544 = UQSUB16
  { 545,	5,	1,	298,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #545 = UQSUB8
  { 546,	5,	1,	306,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #546 = USAD8
  { 547,	6,	1,	307,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x80ULL, NULL, NULL, OperandInfo77,0,0 },  // Inst #547 = USADA8
  { 548,	6,	1,	299,	4,	0|(1<<MCID_Predicable), 0x680ULL, NULL, NULL, OperandInfo108,0,0 },  // Inst #548 = USAT
  { 549,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x680ULL, NULL, NULL, OperandInfo109,0,0 },  // Inst #549 = USAT16
  { 550,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #550 = USAX
  { 551,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #551 = USUB16
  { 552,	5,	1,	300,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x200ULL, NULL, NULL, OperandInfo101,0,0 },  // Inst #552 = USUB8
  { 553,	6,	1,	303,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo119,0,0 },  // Inst #553 = UXTAB
  { 554,	6,	1,	303,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x700ULL, NULL, NULL, OperandInfo119,0,0 },  // Inst #554 = UXTAB16
  { 555,	6,	1,	303,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo119,0,0 },  // Inst #555 = UXTAH
  { 556,	5,	1,	289,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #556 = UXTB
  { 557,	5,	1,	289,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #557 = UXTB16
  { 558,	5,	1,	289,	4,	0|(1<<MCID_Predicable), 0x700ULL, NULL, NULL, OperandInfo120,0,0 },  // Inst #558 = UXTH
  { 559,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #559 = VABALsv2i64
  { 560,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #560 = VABALsv4i32
  { 561,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #561 = VABALsv8i16
  { 562,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #562 = VABALuv2i64
  { 563,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #563 = VABALuv4i32
  { 564,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #564 = VABALuv8i16
  { 565,	6,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #565 = VABAsv16i8
  { 566,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #566 = VABAsv2i32
  { 567,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #567 = VABAsv4i16
  { 568,	6,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #568 = VABAsv4i32
  { 569,	6,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #569 = VABAsv8i16
  { 570,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #570 = VABAsv8i8
  { 571,	6,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #571 = VABAuv16i8
  { 572,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #572 = VABAuv2i32
  { 573,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #573 = VABAuv4i16
  { 574,	6,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #574 = VABAuv4i32
  { 575,	6,	1,	399,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #575 = VABAuv8i16
  { 576,	6,	1,	398,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #576 = VABAuv8i8
  { 577,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #577 = VABDLsv2i64
  { 578,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #578 = VABDLsv4i32
  { 579,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #579 = VABDLsv8i16
  { 580,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #580 = VABDLuv2i64
  { 581,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #581 = VABDLuv4i32
  { 582,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #582 = VABDLuv8i16
  { 583,	5,	1,	440,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #583 = VABDfd
  { 584,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #584 = VABDfq
  { 585,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #585 = VABDsv16i8
  { 586,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #586 = VABDsv2i32
  { 587,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #587 = VABDsv4i16
  { 588,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #588 = VABDsv4i32
  { 589,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #589 = VABDsv8i16
  { 590,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #590 = VABDsv8i8
  { 591,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #591 = VABDuv16i8
  { 592,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #592 = VABDuv2i32
  { 593,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #593 = VABDuv4i16
  { 594,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #594 = VABDuv4i32
  { 595,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #595 = VABDuv8i16
  { 596,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #596 = VABDuv8i8
  { 597,	4,	1,	435,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #597 = VABSD
  { 598,	4,	1,	436,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #598 = VABSS
  { 599,	4,	1,	400,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #599 = VABSfd
  { 600,	4,	1,	401,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #600 = VABSfq
  { 601,	4,	1,	402,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #601 = VABSv16i8
  { 602,	4,	1,	403,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #602 = VABSv2i32
  { 603,	4,	1,	403,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #603 = VABSv4i16
  { 604,	4,	1,	402,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #604 = VABSv4i32
  { 605,	4,	1,	402,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #605 = VABSv8i16
  { 606,	4,	1,	403,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #606 = VABSv8i8
  { 607,	5,	1,	404,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #607 = VACGEd
  { 608,	5,	1,	405,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #608 = VACGEq
  { 609,	5,	1,	404,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #609 = VACGTd
  { 610,	5,	1,	405,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #610 = VACGTq
  { 611,	5,	1,	446,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #611 = VADDD
  { 612,	5,	1,	419,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #612 = VADDHNv2i32
  { 613,	5,	1,	419,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #613 = VADDHNv4i16
  { 614,	5,	1,	419,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #614 = VADDHNv8i8
  { 615,	5,	1,	377,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #615 = VADDLsv2i64
  { 616,	5,	1,	377,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #616 = VADDLsv4i32
  { 617,	5,	1,	377,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #617 = VADDLsv8i16
  { 618,	5,	1,	377,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #618 = VADDLuv2i64
  { 619,	5,	1,	377,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #619 = VADDLuv4i32
  { 620,	5,	1,	377,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #620 = VADDLuv8i16
  { 621,	5,	1,	443,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #621 = VADDS
  { 622,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #622 = VADDWsv2i64
  { 623,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #623 = VADDWsv4i32
  { 624,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #624 = VADDWsv8i16
  { 625,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #625 = VADDWuv2i64
  { 626,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #626 = VADDWuv4i32
  { 627,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #627 = VADDWuv8i16
  { 628,	5,	1,	440,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #628 = VADDfd
  { 629,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #629 = VADDfq
  { 630,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #630 = VADDv16i8
  { 631,	5,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #631 = VADDv1i64
  { 632,	5,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #632 = VADDv2i32
  { 633,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #633 = VADDv2i64
  { 634,	5,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #634 = VADDv4i16
  { 635,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #635 = VADDv4i32
  { 636,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #636 = VADDv8i16
  { 637,	5,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #637 = VADDv8i8
  { 638,	5,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #638 = VANDd
  { 639,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #639 = VANDq
  { 640,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #640 = VBICd
  { 641,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #641 = VBICiv2i32
  { 642,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #642 = VBICiv4i16
  { 643,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #643 = VBICiv4i32
  { 644,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #644 = VBICiv8i16
  { 645,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #645 = VBICq
  { 646,	6,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #646 = VBIFd
  { 647,	6,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #647 = VBIFq
  { 648,	6,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #648 = VBITd
  { 649,	6,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #649 = VBITq
  { 650,	6,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #650 = VBSLd
  { 651,	6,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #651 = VBSLq
  { 652,	5,	1,	404,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #652 = VCEQfd
  { 653,	5,	1,	405,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #653 = VCEQfq
  { 654,	5,	1,	406,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #654 = VCEQv16i8
  { 655,	5,	1,	407,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #655 = VCEQv2i32
  { 656,	5,	1,	407,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #656 = VCEQv4i16
  { 657,	5,	1,	406,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #657 = VCEQv4i32
  { 658,	5,	1,	406,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #658 = VCEQv8i16
  { 659,	5,	1,	407,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #659 = VCEQv8i8
  { 660,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #660 = VCEQzv16i8
  { 661,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #661 = VCEQzv2f32
  { 662,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #662 = VCEQzv2i32
  { 663,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #663 = VCEQzv4f32
  { 664,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #664 = VCEQzv4i16
  { 665,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #665 = VCEQzv4i32
  { 666,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #666 = VCEQzv8i16
  { 667,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #667 = VCEQzv8i8
  { 668,	5,	1,	404,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #668 = VCGEfd
  { 669,	5,	1,	405,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #669 = VCGEfq
  { 670,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #670 = VCGEsv16i8
  { 671,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #671 = VCGEsv2i32
  { 672,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #672 = VCGEsv4i16
  { 673,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #673 = VCGEsv4i32
  { 674,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #674 = VCGEsv8i16
  { 675,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #675 = VCGEsv8i8
  { 676,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #676 = VCGEuv16i8
  { 677,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #677 = VCGEuv2i32
  { 678,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #678 = VCGEuv4i16
  { 679,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #679 = VCGEuv4i32
  { 680,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #680 = VCGEuv8i16
  { 681,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #681 = VCGEuv8i8
  { 682,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #682 = VCGEzv16i8
  { 683,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #683 = VCGEzv2f32
  { 684,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #684 = VCGEzv2i32
  { 685,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #685 = VCGEzv4f32
  { 686,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #686 = VCGEzv4i16
  { 687,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #687 = VCGEzv4i32
  { 688,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #688 = VCGEzv8i16
  { 689,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #689 = VCGEzv8i8
  { 690,	5,	1,	404,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #690 = VCGTfd
  { 691,	5,	1,	405,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #691 = VCGTfq
  { 692,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #692 = VCGTsv16i8
  { 693,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #693 = VCGTsv2i32
  { 694,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #694 = VCGTsv4i16
  { 695,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #695 = VCGTsv4i32
  { 696,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #696 = VCGTsv8i16
  { 697,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #697 = VCGTsv8i8
  { 698,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #698 = VCGTuv16i8
  { 699,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #699 = VCGTuv2i32
  { 700,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #700 = VCGTuv4i16
  { 701,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #701 = VCGTuv4i32
  { 702,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #702 = VCGTuv8i16
  { 703,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #703 = VCGTuv8i8
  { 704,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #704 = VCGTzv16i8
  { 705,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #705 = VCGTzv2f32
  { 706,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #706 = VCGTzv2i32
  { 707,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #707 = VCGTzv4f32
  { 708,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #708 = VCGTzv4i16
  { 709,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #709 = VCGTzv4i32
  { 710,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #710 = VCGTzv8i16
  { 711,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #711 = VCGTzv8i8
  { 712,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #712 = VCLEzv16i8
  { 713,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #713 = VCLEzv2f32
  { 714,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #714 = VCLEzv2i32
  { 715,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #715 = VCLEzv4f32
  { 716,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #716 = VCLEzv4i16
  { 717,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #717 = VCLEzv4i32
  { 718,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #718 = VCLEzv8i16
  { 719,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #719 = VCLEzv8i8
  { 720,	4,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #720 = VCLSv16i8
  { 721,	4,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #721 = VCLSv2i32
  { 722,	4,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #722 = VCLSv4i16
  { 723,	4,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #723 = VCLSv4i32
  { 724,	4,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #724 = VCLSv8i16
  { 725,	4,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #725 = VCLSv8i8
  { 726,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #726 = VCLTzv16i8
  { 727,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #727 = VCLTzv2f32
  { 728,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #728 = VCLTzv2i32
  { 729,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #729 = VCLTzv4f32
  { 730,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #730 = VCLTzv4i16
  { 731,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #731 = VCLTzv4i32
  { 732,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #732 = VCLTzv8i16
  { 733,	4,	1,	408,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #733 = VCLTzv8i8
  { 734,	4,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #734 = VCLZv16i8
  { 735,	4,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #735 = VCLZv2i32
  { 736,	4,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #736 = VCLZv4i16
  { 737,	4,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #737 = VCLZv4i32
  { 738,	4,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #738 = VCLZv8i16
  { 739,	4,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #739 = VCLZv8i8
  { 740,	4,	0,	437,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, ImplicitList4, OperandInfo130,0,0 },  // Inst #740 = VCMPD
  { 741,	4,	0,	437,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, ImplicitList4, OperandInfo130,0,0 },  // Inst #741 = VCMPED
  { 742,	4,	0,	438,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, ImplicitList4, OperandInfo131,0,0 },  // Inst #742 = VCMPES
  { 743,	3,	0,	437,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, ImplicitList4, OperandInfo138,0,0 },  // Inst #743 = VCMPEZD
  { 744,	3,	0,	438,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, ImplicitList4, OperandInfo139,0,0 },  // Inst #744 = VCMPEZS
  { 745,	4,	0,	438,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, NULL, ImplicitList4, OperandInfo131,0,0 },  // Inst #745 = VCMPS
  { 746,	3,	0,	437,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, ImplicitList4, OperandInfo138,0,0 },  // Inst #746 = VCMPZD
  { 747,	3,	0,	438,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28780ULL, NULL, ImplicitList4, OperandInfo139,0,0 },  // Inst #747 = VCMPZS
  { 748,	4,	1,	382,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #748 = VCNTd
  { 749,	4,	1,	383,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #749 = VCNTq
  { 750,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #750 = VCVTANSD
  { 751,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #751 = VCVTANSQ
  { 752,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #752 = VCVTANUD
  { 753,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #753 = VCVTANUQ
  { 754,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #754 = VCVTASD
  { 755,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #755 = VCVTASS
  { 756,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #756 = VCVTAUD
  { 757,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #757 = VCVTAUS
  { 758,	4,	1,	472,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #758 = VCVTBDH
  { 759,	4,	1,	472,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #759 = VCVTBHD
  { 760,	4,	1,	473,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #760 = VCVTBHS
  { 761,	4,	1,	474,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #761 = VCVTBSH
  { 762,	4,	1,	475,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #762 = VCVTDS
  { 763,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #763 = VCVTMNSD
  { 764,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #764 = VCVTMNSQ
  { 765,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #765 = VCVTMNUD
  { 766,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #766 = VCVTMNUQ
  { 767,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #767 = VCVTMSD
  { 768,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #768 = VCVTMSS
  { 769,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #769 = VCVTMUD
  { 770,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #770 = VCVTMUS
  { 771,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #771 = VCVTNNSD
  { 772,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #772 = VCVTNNSQ
  { 773,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #773 = VCVTNNUD
  { 774,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #774 = VCVTNNUQ
  { 775,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #775 = VCVTNSD
  { 776,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #776 = VCVTNSS
  { 777,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #777 = VCVTNUD
  { 778,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #778 = VCVTNUS
  { 779,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #779 = VCVTPNSD
  { 780,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #780 = VCVTPNSQ
  { 781,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #781 = VCVTPNUD
  { 782,	2,	1,	472,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #782 = VCVTPNUQ
  { 783,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #783 = VCVTPSD
  { 784,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #784 = VCVTPSS
  { 785,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo141,0,0 },  // Inst #785 = VCVTPUD
  { 786,	2,	1,	472,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #786 = VCVTPUS
  { 787,	4,	1,	476,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #787 = VCVTSD
  { 788,	4,	1,	472,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #788 = VCVTTDH
  { 789,	4,	1,	472,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #789 = VCVTTHD
  { 790,	4,	1,	473,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #790 = VCVTTHS
  { 791,	4,	1,	474,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #791 = VCVTTSH
  { 792,	4,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #792 = VCVTf2h
  { 793,	4,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #793 = VCVTf2sd
  { 794,	4,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #794 = VCVTf2sq
  { 795,	4,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #795 = VCVTf2ud
  { 796,	4,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #796 = VCVTf2uq
  { 797,	5,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #797 = VCVTf2xsd
  { 798,	5,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #798 = VCVTf2xsq
  { 799,	5,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #799 = VCVTf2xud
  { 800,	5,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #800 = VCVTf2xuq
  { 801,	4,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #801 = VCVTh2f
  { 802,	4,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #802 = VCVTs2fd
  { 803,	4,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #803 = VCVTs2fq
  { 804,	4,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #804 = VCVTu2fd
  { 805,	4,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #805 = VCVTu2fq
  { 806,	5,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #806 = VCVTxs2fd
  { 807,	5,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #807 = VCVTxs2fq
  { 808,	5,	1,	478,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #808 = VCVTxu2fd
  { 809,	5,	1,	477,	4,	0|(1<<MCID_Predicable), 0x11080ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #809 = VCVTxu2fq
  { 810,	5,	1,	586,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #810 = VDIVD
  { 811,	5,	1,	584,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #811 = VDIVS
  { 812,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #812 = VDUP16d
  { 813,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo150,0,0 },  // Inst #813 = VDUP16q
  { 814,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #814 = VDUP32d
  { 815,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo150,0,0 },  // Inst #815 = VDUP32q
  { 816,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo149,0,0 },  // Inst #816 = VDUP8d
  { 817,	4,	1,	494,	4,	0|(1<<MCID_Predicable), 0x10e80ULL, NULL, NULL, OperandInfo150,0,0 },  // Inst #817 = VDUP8q
  { 818,	5,	1,	492,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #818 = VDUPLN16d
  { 819,	5,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #819 = VDUPLN16q
  { 820,	5,	1,	492,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #820 = VDUPLN32d
  { 821,	5,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #821 = VDUPLN32q
  { 822,	5,	1,	492,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #822 = VDUPLN8d
  { 823,	5,	1,	493,	4,	0|(1<<MCID_Predicable), 0x11100ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #823 = VDUPLN8q
  { 824,	4,	1,	492,	4,	0|(1<<MCID_Predicable), 0x10000ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #824 = VDUPfdf
  { 825,	4,	1,	492,	4,	0|(1<<MCID_Predicable), 0x10000ULL, NULL, NULL, OperandInfo152,0,0 },  // Inst #825 = VDUPfqf
  { 826,	5,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #826 = VEORd
  { 827,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #827 = VEORq
  { 828,	6,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo153,0,0 },  // Inst #828 = VEXTd16
  { 829,	6,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo153,0,0 },  // Inst #829 = VEXTd32
  { 830,	6,	1,	394,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo153,0,0 },  // Inst #830 = VEXTd8
  { 831,	6,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo154,0,0 },  // Inst #831 = VEXTq16
  { 832,	6,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo154,0,0 },  // Inst #832 = VEXTq32
  { 833,	6,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo154,0,0 },  // Inst #833 = VEXTq64
  { 834,	6,	1,	395,	4,	0|(1<<MCID_Predicable), 0x11380ULL, NULL, NULL, OperandInfo154,0,0 },  // Inst #834 = VEXTq8
  { 835,	6,	1,	460,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #835 = VFMAD
  { 836,	6,	1,	461,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #836 = VFMAS
  { 837,	6,	1,	470,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #837 = VFMAfd
  { 838,	6,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #838 = VFMAfq
  { 839,	6,	1,	460,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #839 = VFMSD
  { 840,	6,	1,	461,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #840 = VFMSS
  { 841,	6,	1,	470,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #841 = VFMSfd
  { 842,	6,	1,	471,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #842 = VFMSfq
  { 843,	6,	1,	460,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #843 = VFNMAD
  { 844,	6,	1,	461,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #844 = VFNMAS
  { 845,	6,	1,	460,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #845 = VFNMSD
  { 846,	6,	1,	461,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #846 = VFNMSS
  { 847,	5,	1,	501,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #847 = VGETLNi32
  { 848,	5,	1,	502,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #848 = VGETLNs16
  { 849,	5,	1,	502,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #849 = VGETLNs8
  { 850,	5,	1,	501,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #850 = VGETLNu16
  { 851,	5,	1,	501,	4,	0|(1<<MCID_Predicable), 0x10d80ULL, NULL, NULL, OperandInfo156,0,0 },  // Inst #851 = VGETLNu8
  { 852,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #852 = VHADDsv16i8
  { 853,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #853 = VHADDsv2i32
  { 854,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #854 = VHADDsv4i16
  { 855,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #855 = VHADDsv4i32
  { 856,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #856 = VHADDsv8i16
  { 857,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #857 = VHADDsv8i8
  { 858,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #858 = VHADDuv16i8
  { 859,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #859 = VHADDuv2i32
  { 860,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #860 = VHADDuv4i16
  { 861,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #861 = VHADDuv4i32
  { 862,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #862 = VHADDuv8i16
  { 863,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #863 = VHADDuv8i8
  { 864,	5,	1,	386,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #864 = VHSUBsv16i8
  { 865,	5,	1,	387,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #865 = VHSUBsv2i32
  { 866,	5,	1,	387,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #866 = VHSUBsv4i16
  { 867,	5,	1,	386,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #867 = VHSUBsv4i32
  { 868,	5,	1,	386,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #868 = VHSUBsv8i16
  { 869,	5,	1,	387,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #869 = VHSUBsv8i8
  { 870,	5,	1,	386,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #870 = VHSUBuv16i8
  { 871,	5,	1,	387,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #871 = VHSUBuv2i32
  { 872,	5,	1,	387,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #872 = VHSUBuv4i16
  { 873,	5,	1,	386,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #873 = VHSUBuv4i32
  { 874,	5,	1,	386,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #874 = VHSUBuv8i16
  { 875,	5,	1,	387,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #875 = VHSUBuv8i8
  { 876,	5,	1,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #876 = VLD1DUPd16
  { 877,	6,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #877 = VLD1DUPd16wb_fixed
  { 878,	7,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #878 = VLD1DUPd16wb_register
  { 879,	5,	1,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #879 = VLD1DUPd32
  { 880,	6,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #880 = VLD1DUPd32wb_fixed
  { 881,	7,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #881 = VLD1DUPd32wb_register
  { 882,	5,	1,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #882 = VLD1DUPd8
  { 883,	6,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #883 = VLD1DUPd8wb_fixed
  { 884,	7,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #884 = VLD1DUPd8wb_register
  { 885,	5,	1,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #885 = VLD1DUPq16
  { 886,	6,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #886 = VLD1DUPq16wb_fixed
  { 887,	7,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #887 = VLD1DUPq16wb_register
  { 888,	5,	1,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #888 = VLD1DUPq32
  { 889,	6,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #889 = VLD1DUPq32wb_fixed
  { 890,	7,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #890 = VLD1DUPq32wb_register
  { 891,	5,	1,	536,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #891 = VLD1DUPq8
  { 892,	6,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #892 = VLD1DUPq8wb_fixed
  { 893,	7,	2,	538,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #893 = VLD1DUPq8wb_register
  { 894,	7,	1,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #894 = VLD1LNd16
  { 895,	9,	2,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo164,0,0 },  // Inst #895 = VLD1LNd16_UPD
  { 896,	7,	1,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #896 = VLD1LNd32
  { 897,	9,	2,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo164,0,0 },  // Inst #897 = VLD1LNd32_UPD
  { 898,	7,	1,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo163,0,0 },  // Inst #898 = VLD1LNd8
  { 899,	9,	2,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo164,0,0 },  // Inst #899 = VLD1LNd8_UPD
  { 900,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #900 = VLD1LNdAsm_16
  { 901,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #901 = VLD1LNdAsm_32
  { 902,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #902 = VLD1LNdAsm_8
  { 903,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #903 = VLD1LNdWB_fixed_Asm_16
  { 904,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #904 = VLD1LNdWB_fixed_Asm_32
  { 905,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #905 = VLD1LNdWB_fixed_Asm_8
  { 906,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #906 = VLD1LNdWB_register_Asm_16
  { 907,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #907 = VLD1LNdWB_register_Asm_32
  { 908,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #908 = VLD1LNdWB_register_Asm_8
  { 909,	7,	1,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #909 = VLD1LNq16Pseudo
  { 910,	9,	2,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #910 = VLD1LNq16Pseudo_UPD
  { 911,	7,	1,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #911 = VLD1LNq32Pseudo
  { 912,	9,	2,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #912 = VLD1LNq32Pseudo_UPD
  { 913,	7,	1,	537,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #913 = VLD1LNq8Pseudo
  { 914,	9,	2,	539,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #914 = VLD1LNq8Pseudo_UPD
  { 915,	5,	1,	516,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #915 = VLD1d16
  { 916,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #916 = VLD1d16Q
  { 917,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #917 = VLD1d16Qwb_fixed
  { 918,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #918 = VLD1d16Qwb_register
  { 919,	5,	1,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #919 = VLD1d16T
  { 920,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #920 = VLD1d16Twb_fixed
  { 921,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #921 = VLD1d16Twb_register
  { 922,	6,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #922 = VLD1d16wb_fixed
  { 923,	7,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #923 = VLD1d16wb_register
  { 924,	5,	1,	516,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #924 = VLD1d32
  { 925,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #925 = VLD1d32Q
  { 926,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #926 = VLD1d32Qwb_fixed
  { 927,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #927 = VLD1d32Qwb_register
  { 928,	5,	1,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #928 = VLD1d32T
  { 929,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #929 = VLD1d32Twb_fixed
  { 930,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #930 = VLD1d32Twb_register
  { 931,	6,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #931 = VLD1d32wb_fixed
  { 932,	7,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #932 = VLD1d32wb_register
  { 933,	5,	1,	516,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #933 = VLD1d64
  { 934,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #934 = VLD1d64Q
  { 935,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #935 = VLD1d64QPseudo
  { 936,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #936 = VLD1d64Qwb_fixed
  { 937,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #937 = VLD1d64Qwb_register
  { 938,	5,	1,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #938 = VLD1d64T
  { 939,	5,	1,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #939 = VLD1d64TPseudo
  { 940,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #940 = VLD1d64Twb_fixed
  { 941,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #941 = VLD1d64Twb_register
  { 942,	6,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #942 = VLD1d64wb_fixed
  { 943,	7,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #943 = VLD1d64wb_register
  { 944,	5,	1,	516,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #944 = VLD1d8
  { 945,	5,	1,	522,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #945 = VLD1d8Q
  { 946,	6,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #946 = VLD1d8Qwb_fixed
  { 947,	7,	2,	523,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #947 = VLD1d8Qwb_register
  { 948,	5,	1,	520,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #948 = VLD1d8T
  { 949,	6,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #949 = VLD1d8Twb_fixed
  { 950,	7,	2,	521,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #950 = VLD1d8Twb_register
  { 951,	6,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #951 = VLD1d8wb_fixed
  { 952,	7,	2,	518,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #952 = VLD1d8wb_register
  { 953,	5,	1,	517,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #953 = VLD1q16
  { 954,	6,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #954 = VLD1q16wb_fixed
  { 955,	7,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #955 = VLD1q16wb_register
  { 956,	5,	1,	517,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #956 = VLD1q32
  { 957,	6,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #957 = VLD1q32wb_fixed
  { 958,	7,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #958 = VLD1q32wb_register
  { 959,	5,	1,	517,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #959 = VLD1q64
  { 960,	6,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #960 = VLD1q64wb_fixed
  { 961,	7,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #961 = VLD1q64wb_register
  { 962,	5,	1,	517,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #962 = VLD1q8
  { 963,	6,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #963 = VLD1q8wb_fixed
  { 964,	7,	2,	519,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #964 = VLD1q8wb_register
  { 965,	5,	1,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #965 = VLD2DUPd16
  { 966,	6,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #966 = VLD2DUPd16wb_fixed
  { 967,	7,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #967 = VLD2DUPd16wb_register
  { 968,	5,	1,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #968 = VLD2DUPd16x2
  { 969,	6,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #969 = VLD2DUPd16x2wb_fixed
  { 970,	7,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #970 = VLD2DUPd16x2wb_register
  { 971,	5,	1,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #971 = VLD2DUPd32
  { 972,	6,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #972 = VLD2DUPd32wb_fixed
  { 973,	7,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #973 = VLD2DUPd32wb_register
  { 974,	5,	1,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #974 = VLD2DUPd32x2
  { 975,	6,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #975 = VLD2DUPd32x2wb_fixed
  { 976,	7,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #976 = VLD2DUPd32x2wb_register
  { 977,	5,	1,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #977 = VLD2DUPd8
  { 978,	6,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #978 = VLD2DUPd8wb_fixed
  { 979,	7,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #979 = VLD2DUPd8wb_register
  { 980,	5,	1,	540,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #980 = VLD2DUPd8x2
  { 981,	6,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #981 = VLD2DUPd8x2wb_fixed
  { 982,	7,	2,	543,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #982 = VLD2DUPd8x2wb_register
  { 983,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #983 = VLD2LNd16
  { 984,	7,	1,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #984 = VLD2LNd16Pseudo
  { 985,	9,	2,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #985 = VLD2LNd16Pseudo_UPD
  { 986,	11,	3,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #986 = VLD2LNd16_UPD
  { 987,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #987 = VLD2LNd32
  { 988,	7,	1,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #988 = VLD2LNd32Pseudo
  { 989,	9,	2,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #989 = VLD2LNd32Pseudo_UPD
  { 990,	11,	3,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #990 = VLD2LNd32_UPD
  { 991,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #991 = VLD2LNd8
  { 992,	7,	1,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo167,0,0 },  // Inst #992 = VLD2LNd8Pseudo
  { 993,	9,	2,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo168,0,0 },  // Inst #993 = VLD2LNd8Pseudo_UPD
  { 994,	11,	3,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #994 = VLD2LNd8_UPD
  { 995,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #995 = VLD2LNdAsm_16
  { 996,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #996 = VLD2LNdAsm_32
  { 997,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #997 = VLD2LNdAsm_8
  { 998,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #998 = VLD2LNdWB_fixed_Asm_16
  { 999,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #999 = VLD2LNdWB_fixed_Asm_32
  { 1000,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1000 = VLD2LNdWB_fixed_Asm_8
  { 1001,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1001 = VLD2LNdWB_register_Asm_16
  { 1002,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1002 = VLD2LNdWB_register_Asm_32
  { 1003,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1003 = VLD2LNdWB_register_Asm_8
  { 1004,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1004 = VLD2LNq16
  { 1005,	7,	1,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1005 = VLD2LNq16Pseudo
  { 1006,	9,	2,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1006 = VLD2LNq16Pseudo_UPD
  { 1007,	11,	3,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #1007 = VLD2LNq16_UPD
  { 1008,	9,	2,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo170,0,0 },  // Inst #1008 = VLD2LNq32
  { 1009,	7,	1,	541,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1009 = VLD2LNq32Pseudo
  { 1010,	9,	2,	544,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1010 = VLD2LNq32Pseudo_UPD
  { 1011,	11,	3,	542,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo171,0,0 },  // Inst #1011 = VLD2LNq32_UPD
  { 1012,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1012 = VLD2LNqAsm_16
  { 1013,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1013 = VLD2LNqAsm_32
  { 1014,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1014 = VLD2LNqWB_fixed_Asm_16
  { 1015,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1015 = VLD2LNqWB_fixed_Asm_32
  { 1016,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1016 = VLD2LNqWB_register_Asm_16
  { 1017,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1017 = VLD2LNqWB_register_Asm_32
  { 1018,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1018 = VLD2b16
  { 1019,	6,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1019 = VLD2b16wb_fixed
  { 1020,	7,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1020 = VLD2b16wb_register
  { 1021,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1021 = VLD2b32
  { 1022,	6,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1022 = VLD2b32wb_fixed
  { 1023,	7,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1023 = VLD2b32wb_register
  { 1024,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1024 = VLD2b8
  { 1025,	6,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1025 = VLD2b8wb_fixed
  { 1026,	7,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1026 = VLD2b8wb_register
  { 1027,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1027 = VLD2d16
  { 1028,	6,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1028 = VLD2d16wb_fixed
  { 1029,	7,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1029 = VLD2d16wb_register
  { 1030,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1030 = VLD2d32
  { 1031,	6,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1031 = VLD2d32wb_fixed
  { 1032,	7,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1032 = VLD2d32wb_register
  { 1033,	5,	1,	524,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo160,0,0 },  // Inst #1033 = VLD2d8
  { 1034,	6,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo161,0,0 },  // Inst #1034 = VLD2d8wb_fixed
  { 1035,	7,	2,	526,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo162,0,0 },  // Inst #1035 = VLD2d8wb_register
  { 1036,	5,	1,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1036 = VLD2q16
  { 1037,	5,	1,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1037 = VLD2q16Pseudo
  { 1038,	6,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1038 = VLD2q16PseudoWB_fixed
  { 1039,	7,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo175,0,0 },  // Inst #1039 = VLD2q16PseudoWB_register
  { 1040,	6,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1040 = VLD2q16wb_fixed
  { 1041,	7,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #1041 = VLD2q16wb_register
  { 1042,	5,	1,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1042 = VLD2q32
  { 1043,	5,	1,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1043 = VLD2q32Pseudo
  { 1044,	6,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1044 = VLD2q32PseudoWB_fixed
  { 1045,	7,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo175,0,0 },  // Inst #1045 = VLD2q32PseudoWB_register
  { 1046,	6,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1046 = VLD2q32wb_fixed
  { 1047,	7,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #1047 = VLD2q32wb_register
  { 1048,	5,	1,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1048 = VLD2q8
  { 1049,	5,	1,	525,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1049 = VLD2q8Pseudo
  { 1050,	6,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo174,0,0 },  // Inst #1050 = VLD2q8PseudoWB_fixed
  { 1051,	7,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo175,0,0 },  // Inst #1051 = VLD2q8PseudoWB_register
  { 1052,	6,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo158,0,0 },  // Inst #1052 = VLD2q8wb_fixed
  { 1053,	7,	2,	527,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo159,0,0 },  // Inst #1053 = VLD2q8wb_register
  { 1054,	7,	3,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1054 = VLD3DUPd16
  { 1055,	5,	1,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1055 = VLD3DUPd16Pseudo
  { 1056,	7,	2,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1056 = VLD3DUPd16Pseudo_UPD
  { 1057,	9,	4,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1057 = VLD3DUPd16_UPD
  { 1058,	7,	3,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1058 = VLD3DUPd32
  { 1059,	5,	1,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1059 = VLD3DUPd32Pseudo
  { 1060,	7,	2,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1060 = VLD3DUPd32Pseudo_UPD
  { 1061,	9,	4,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1061 = VLD3DUPd32_UPD
  { 1062,	7,	3,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1062 = VLD3DUPd8
  { 1063,	5,	1,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1063 = VLD3DUPd8Pseudo
  { 1064,	7,	2,	549,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1064 = VLD3DUPd8Pseudo_UPD
  { 1065,	9,	4,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1065 = VLD3DUPd8_UPD
  { 1066,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1066 = VLD3DUPdAsm_16
  { 1067,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1067 = VLD3DUPdAsm_32
  { 1068,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1068 = VLD3DUPdAsm_8
  { 1069,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1069 = VLD3DUPdWB_fixed_Asm_16
  { 1070,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1070 = VLD3DUPdWB_fixed_Asm_32
  { 1071,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1071 = VLD3DUPdWB_fixed_Asm_8
  { 1072,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1072 = VLD3DUPdWB_register_Asm_16
  { 1073,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1073 = VLD3DUPdWB_register_Asm_32
  { 1074,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1074 = VLD3DUPdWB_register_Asm_8
  { 1075,	7,	3,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1075 = VLD3DUPq16
  { 1076,	9,	4,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1076 = VLD3DUPq16_UPD
  { 1077,	7,	3,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1077 = VLD3DUPq32
  { 1078,	9,	4,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1078 = VLD3DUPq32_UPD
  { 1079,	7,	3,	545,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1079 = VLD3DUPq8
  { 1080,	9,	4,	547,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1080 = VLD3DUPq8_UPD
  { 1081,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1081 = VLD3DUPqAsm_16
  { 1082,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1082 = VLD3DUPqAsm_32
  { 1083,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1083 = VLD3DUPqAsm_8
  { 1084,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1084 = VLD3DUPqWB_fixed_Asm_16
  { 1085,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1085 = VLD3DUPqWB_fixed_Asm_32
  { 1086,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1086 = VLD3DUPqWB_fixed_Asm_8
  { 1087,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1087 = VLD3DUPqWB_register_Asm_16
  { 1088,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1088 = VLD3DUPqWB_register_Asm_32
  { 1089,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1089 = VLD3DUPqWB_register_Asm_8
  { 1090,	11,	3,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1090 = VLD3LNd16
  { 1091,	7,	1,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1091 = VLD3LNd16Pseudo
  { 1092,	9,	2,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1092 = VLD3LNd16Pseudo_UPD
  { 1093,	13,	4,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1093 = VLD3LNd16_UPD
  { 1094,	11,	3,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1094 = VLD3LNd32
  { 1095,	7,	1,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1095 = VLD3LNd32Pseudo
  { 1096,	9,	2,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1096 = VLD3LNd32Pseudo_UPD
  { 1097,	13,	4,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1097 = VLD3LNd32_UPD
  { 1098,	11,	3,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1098 = VLD3LNd8
  { 1099,	7,	1,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1099 = VLD3LNd8Pseudo
  { 1100,	9,	2,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1100 = VLD3LNd8Pseudo_UPD
  { 1101,	13,	4,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1101 = VLD3LNd8_UPD
  { 1102,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1102 = VLD3LNdAsm_16
  { 1103,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1103 = VLD3LNdAsm_32
  { 1104,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1104 = VLD3LNdAsm_8
  { 1105,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1105 = VLD3LNdWB_fixed_Asm_16
  { 1106,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1106 = VLD3LNdWB_fixed_Asm_32
  { 1107,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1107 = VLD3LNdWB_fixed_Asm_8
  { 1108,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1108 = VLD3LNdWB_register_Asm_16
  { 1109,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1109 = VLD3LNdWB_register_Asm_32
  { 1110,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1110 = VLD3LNdWB_register_Asm_8
  { 1111,	11,	3,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1111 = VLD3LNq16
  { 1112,	7,	1,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1112 = VLD3LNq16Pseudo
  { 1113,	9,	2,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1113 = VLD3LNq16Pseudo_UPD
  { 1114,	13,	4,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1114 = VLD3LNq16_UPD
  { 1115,	11,	3,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo180,0,0 },  // Inst #1115 = VLD3LNq32
  { 1116,	7,	1,	546,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1116 = VLD3LNq32Pseudo
  { 1117,	9,	2,	550,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1117 = VLD3LNq32Pseudo_UPD
  { 1118,	13,	4,	548,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo181,0,0 },  // Inst #1118 = VLD3LNq32_UPD
  { 1119,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1119 = VLD3LNqAsm_16
  { 1120,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1120 = VLD3LNqAsm_32
  { 1121,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1121 = VLD3LNqWB_fixed_Asm_16
  { 1122,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1122 = VLD3LNqWB_fixed_Asm_32
  { 1123,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1123 = VLD3LNqWB_register_Asm_16
  { 1124,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1124 = VLD3LNqWB_register_Asm_32
  { 1125,	7,	3,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1125 = VLD3d16
  { 1126,	5,	1,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1126 = VLD3d16Pseudo
  { 1127,	7,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1127 = VLD3d16Pseudo_UPD
  { 1128,	9,	4,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1128 = VLD3d16_UPD
  { 1129,	7,	3,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1129 = VLD3d32
  { 1130,	5,	1,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1130 = VLD3d32Pseudo
  { 1131,	7,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1131 = VLD3d32Pseudo_UPD
  { 1132,	9,	4,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1132 = VLD3d32_UPD
  { 1133,	7,	3,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1133 = VLD3d8
  { 1134,	5,	1,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1134 = VLD3d8Pseudo
  { 1135,	7,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1135 = VLD3d8Pseudo_UPD
  { 1136,	9,	4,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1136 = VLD3d8_UPD
  { 1137,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1137 = VLD3dAsm_16
  { 1138,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1138 = VLD3dAsm_32
  { 1139,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1139 = VLD3dAsm_8
  { 1140,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1140 = VLD3dWB_fixed_Asm_16
  { 1141,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1141 = VLD3dWB_fixed_Asm_32
  { 1142,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1142 = VLD3dWB_fixed_Asm_8
  { 1143,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1143 = VLD3dWB_register_Asm_16
  { 1144,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1144 = VLD3dWB_register_Asm_32
  { 1145,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1145 = VLD3dWB_register_Asm_8
  { 1146,	7,	3,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1146 = VLD3q16
  { 1147,	8,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1147 = VLD3q16Pseudo_UPD
  { 1148,	9,	4,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1148 = VLD3q16_UPD
  { 1149,	6,	1,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1149 = VLD3q16oddPseudo
  { 1150,	8,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1150 = VLD3q16oddPseudo_UPD
  { 1151,	7,	3,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1151 = VLD3q32
  { 1152,	8,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1152 = VLD3q32Pseudo_UPD
  { 1153,	9,	4,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1153 = VLD3q32_UPD
  { 1154,	6,	1,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1154 = VLD3q32oddPseudo
  { 1155,	8,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1155 = VLD3q32oddPseudo_UPD
  { 1156,	7,	3,	528,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo176,0,0 },  // Inst #1156 = VLD3q8
  { 1157,	8,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1157 = VLD3q8Pseudo_UPD
  { 1158,	9,	4,	530,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo178,0,0 },  // Inst #1158 = VLD3q8_UPD
  { 1159,	6,	1,	529,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1159 = VLD3q8oddPseudo
  { 1160,	8,	2,	531,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1160 = VLD3q8oddPseudo_UPD
  { 1161,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1161 = VLD3qAsm_16
  { 1162,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1162 = VLD3qAsm_32
  { 1163,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1163 = VLD3qAsm_8
  { 1164,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1164 = VLD3qWB_fixed_Asm_16
  { 1165,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1165 = VLD3qWB_fixed_Asm_32
  { 1166,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1166 = VLD3qWB_fixed_Asm_8
  { 1167,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1167 = VLD3qWB_register_Asm_16
  { 1168,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1168 = VLD3qWB_register_Asm_32
  { 1169,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1169 = VLD3qWB_register_Asm_8
  { 1170,	8,	4,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1170 = VLD4DUPd16
  { 1171,	5,	1,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1171 = VLD4DUPd16Pseudo
  { 1172,	7,	2,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1172 = VLD4DUPd16Pseudo_UPD
  { 1173,	10,	5,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1173 = VLD4DUPd16_UPD
  { 1174,	8,	4,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1174 = VLD4DUPd32
  { 1175,	5,	1,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1175 = VLD4DUPd32Pseudo
  { 1176,	7,	2,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1176 = VLD4DUPd32Pseudo_UPD
  { 1177,	10,	5,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1177 = VLD4DUPd32_UPD
  { 1178,	8,	4,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1178 = VLD4DUPd8
  { 1179,	5,	1,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1179 = VLD4DUPd8Pseudo
  { 1180,	7,	2,	555,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1180 = VLD4DUPd8Pseudo_UPD
  { 1181,	10,	5,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1181 = VLD4DUPd8_UPD
  { 1182,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1182 = VLD4DUPdAsm_16
  { 1183,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1183 = VLD4DUPdAsm_32
  { 1184,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1184 = VLD4DUPdAsm_8
  { 1185,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1185 = VLD4DUPdWB_fixed_Asm_16
  { 1186,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1186 = VLD4DUPdWB_fixed_Asm_32
  { 1187,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1187 = VLD4DUPdWB_fixed_Asm_8
  { 1188,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1188 = VLD4DUPdWB_register_Asm_16
  { 1189,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1189 = VLD4DUPdWB_register_Asm_32
  { 1190,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1190 = VLD4DUPdWB_register_Asm_8
  { 1191,	8,	4,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1191 = VLD4DUPq16
  { 1192,	10,	5,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1192 = VLD4DUPq16_UPD
  { 1193,	8,	4,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1193 = VLD4DUPq32
  { 1194,	10,	5,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1194 = VLD4DUPq32_UPD
  { 1195,	8,	4,	551,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1195 = VLD4DUPq8
  { 1196,	10,	5,	553,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1196 = VLD4DUPq8_UPD
  { 1197,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1197 = VLD4DUPqAsm_16
  { 1198,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1198 = VLD4DUPqAsm_32
  { 1199,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1199 = VLD4DUPqAsm_8
  { 1200,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1200 = VLD4DUPqWB_fixed_Asm_16
  { 1201,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1201 = VLD4DUPqWB_fixed_Asm_32
  { 1202,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1202 = VLD4DUPqWB_fixed_Asm_8
  { 1203,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1203 = VLD4DUPqWB_register_Asm_16
  { 1204,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1204 = VLD4DUPqWB_register_Asm_32
  { 1205,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1205 = VLD4DUPqWB_register_Asm_8
  { 1206,	13,	4,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1206 = VLD4LNd16
  { 1207,	7,	1,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1207 = VLD4LNd16Pseudo
  { 1208,	9,	2,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1208 = VLD4LNd16Pseudo_UPD
  { 1209,	15,	5,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1209 = VLD4LNd16_UPD
  { 1210,	13,	4,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1210 = VLD4LNd32
  { 1211,	7,	1,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1211 = VLD4LNd32Pseudo
  { 1212,	9,	2,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1212 = VLD4LNd32Pseudo_UPD
  { 1213,	15,	5,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1213 = VLD4LNd32_UPD
  { 1214,	13,	4,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1214 = VLD4LNd8
  { 1215,	7,	1,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo172,0,0 },  // Inst #1215 = VLD4LNd8Pseudo
  { 1216,	9,	2,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo173,0,0 },  // Inst #1216 = VLD4LNd8Pseudo_UPD
  { 1217,	15,	5,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1217 = VLD4LNd8_UPD
  { 1218,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1218 = VLD4LNdAsm_16
  { 1219,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1219 = VLD4LNdAsm_32
  { 1220,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1220 = VLD4LNdAsm_8
  { 1221,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1221 = VLD4LNdWB_fixed_Asm_16
  { 1222,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1222 = VLD4LNdWB_fixed_Asm_32
  { 1223,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1223 = VLD4LNdWB_fixed_Asm_8
  { 1224,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1224 = VLD4LNdWB_register_Asm_16
  { 1225,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1225 = VLD4LNdWB_register_Asm_32
  { 1226,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1226 = VLD4LNdWB_register_Asm_8
  { 1227,	13,	4,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1227 = VLD4LNq16
  { 1228,	7,	1,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1228 = VLD4LNq16Pseudo
  { 1229,	9,	2,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1229 = VLD4LNq16Pseudo_UPD
  { 1230,	15,	5,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1230 = VLD4LNq16_UPD
  { 1231,	13,	4,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo188,0,0 },  // Inst #1231 = VLD4LNq32
  { 1232,	7,	1,	552,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo182,0,0 },  // Inst #1232 = VLD4LNq32Pseudo
  { 1233,	9,	2,	556,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo183,0,0 },  // Inst #1233 = VLD4LNq32Pseudo_UPD
  { 1234,	15,	5,	554,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo189,0,0 },  // Inst #1234 = VLD4LNq32_UPD
  { 1235,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1235 = VLD4LNqAsm_16
  { 1236,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1236 = VLD4LNqAsm_32
  { 1237,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1237 = VLD4LNqWB_fixed_Asm_16
  { 1238,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1238 = VLD4LNqWB_fixed_Asm_32
  { 1239,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1239 = VLD4LNqWB_register_Asm_16
  { 1240,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1240 = VLD4LNqWB_register_Asm_32
  { 1241,	8,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1241 = VLD4d16
  { 1242,	5,	1,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1242 = VLD4d16Pseudo
  { 1243,	7,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1243 = VLD4d16Pseudo_UPD
  { 1244,	10,	5,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1244 = VLD4d16_UPD
  { 1245,	8,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1245 = VLD4d32
  { 1246,	5,	1,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1246 = VLD4d32Pseudo
  { 1247,	7,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1247 = VLD4d32Pseudo_UPD
  { 1248,	10,	5,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1248 = VLD4d32_UPD
  { 1249,	8,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1249 = VLD4d8
  { 1250,	5,	1,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo169,0,0 },  // Inst #1250 = VLD4d8Pseudo
  { 1251,	7,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo177,0,0 },  // Inst #1251 = VLD4d8Pseudo_UPD
  { 1252,	10,	5,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1252 = VLD4d8_UPD
  { 1253,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1253 = VLD4dAsm_16
  { 1254,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1254 = VLD4dAsm_32
  { 1255,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1255 = VLD4dAsm_8
  { 1256,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1256 = VLD4dWB_fixed_Asm_16
  { 1257,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1257 = VLD4dWB_fixed_Asm_32
  { 1258,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1258 = VLD4dWB_fixed_Asm_8
  { 1259,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1259 = VLD4dWB_register_Asm_16
  { 1260,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1260 = VLD4dWB_register_Asm_32
  { 1261,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1261 = VLD4dWB_register_Asm_8
  { 1262,	8,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1262 = VLD4q16
  { 1263,	8,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1263 = VLD4q16Pseudo_UPD
  { 1264,	10,	5,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1264 = VLD4q16_UPD
  { 1265,	6,	1,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1265 = VLD4q16oddPseudo
  { 1266,	8,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1266 = VLD4q16oddPseudo_UPD
  { 1267,	8,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1267 = VLD4q32
  { 1268,	8,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1268 = VLD4q32Pseudo_UPD
  { 1269,	10,	5,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1269 = VLD4q32_UPD
  { 1270,	6,	1,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1270 = VLD4q32oddPseudo
  { 1271,	8,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1271 = VLD4q32oddPseudo_UPD
  { 1272,	8,	4,	532,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo186,0,0 },  // Inst #1272 = VLD4q8
  { 1273,	8,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1273 = VLD4q8Pseudo_UPD
  { 1274,	10,	5,	534,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo187,0,0 },  // Inst #1274 = VLD4q8_UPD
  { 1275,	6,	1,	533,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo185,0,0 },  // Inst #1275 = VLD4q8oddPseudo
  { 1276,	8,	2,	535,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo184,0,0 },  // Inst #1276 = VLD4q8oddPseudo_UPD
  { 1277,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1277 = VLD4qAsm_16
  { 1278,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1278 = VLD4qAsm_32
  { 1279,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1279 = VLD4qAsm_8
  { 1280,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1280 = VLD4qWB_fixed_Asm_16
  { 1281,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1281 = VLD4qWB_fixed_Asm_32
  { 1282,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #1282 = VLD4qWB_fixed_Asm_8
  { 1283,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1283 = VLD4qWB_register_Asm_16
  { 1284,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1284 = VLD4qWB_register_Asm_32
  { 1285,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #1285 = VLD4qWB_register_Asm_8
  { 1286,	5,	1,	513,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1286 = VLDMDDB_UPD
  { 1287,	4,	0,	512,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #1287 = VLDMDIA
  { 1288,	5,	1,	513,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1288 = VLDMDIA_UPD
  { 1289,	4,	1,	510,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0x18004ULL, NULL, NULL, OperandInfo190,0,0 },  // Inst #1289 = VLDMQIA
  { 1290,	5,	1,	513,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1290 = VLDMSDB_UPD
  { 1291,	4,	0,	512,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #1291 = VLDMSIA
  { 1292,	5,	1,	513,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #1292 = VLDMSIA_UPD
  { 1293,	5,	1,	506,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, NULL, NULL, OperandInfo191,0,0 },  // Inst #1293 = VLDRD
  { 1294,	5,	1,	507,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x18b05ULL, NULL, NULL, OperandInfo192,0,0 },  // Inst #1294 = VLDRS
  { 1295,	3,	1,	444,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo193,0,0 },  // Inst #1295 = VMAXNMD
  { 1296,	3,	1,	444,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo193,0,0 },  // Inst #1296 = VMAXNMND
  { 1297,	3,	1,	444,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo194,0,0 },  // Inst #1297 = VMAXNMNQ
  { 1298,	3,	1,	444,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo195,0,0 },  // Inst #1298 = VMAXNMS
  { 1299,	5,	1,	440,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1299 = VMAXfd
  { 1300,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1300 = VMAXfq
  { 1301,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1301 = VMAXsv16i8
  { 1302,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1302 = VMAXsv2i32
  { 1303,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1303 = VMAXsv4i16
  { 1304,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1304 = VMAXsv4i32
  { 1305,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1305 = VMAXsv8i16
  { 1306,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1306 = VMAXsv8i8
  { 1307,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1307 = VMAXuv16i8
  { 1308,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1308 = VMAXuv2i32
  { 1309,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1309 = VMAXuv4i16
  { 1310,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1310 = VMAXuv4i32
  { 1311,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1311 = VMAXuv8i16
  { 1312,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1312 = VMAXuv8i8
  { 1313,	3,	1,	444,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo193,0,0 },  // Inst #1313 = VMINNMD
  { 1314,	3,	1,	444,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo193,0,0 },  // Inst #1314 = VMINNMND
  { 1315,	3,	1,	444,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo194,0,0 },  // Inst #1315 = VMINNMNQ
  { 1316,	3,	1,	444,	4,	0, 0x8800ULL, NULL, NULL, OperandInfo195,0,0 },  // Inst #1316 = VMINNMS
  { 1317,	5,	1,	440,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1317 = VMINfd
  { 1318,	5,	1,	441,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1318 = VMINfq
  { 1319,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1319 = VMINsv16i8
  { 1320,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1320 = VMINsv2i32
  { 1321,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1321 = VMINsv4i16
  { 1322,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1322 = VMINsv4i32
  { 1323,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1323 = VMINsv8i16
  { 1324,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1324 = VMINsv8i8
  { 1325,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1325 = VMINuv16i8
  { 1326,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1326 = VMINuv2i32
  { 1327,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1327 = VMINuv4i16
  { 1328,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1328 = VMINuv4i32
  { 1329,	5,	1,	439,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1329 = VMINuv8i16
  { 1330,	5,	1,	442,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1330 = VMINuv8i8
  { 1331,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1331 = VMLAD
  { 1332,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1332 = VMLALslsv2i32
  { 1333,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1333 = VMLALslsv4i16
  { 1334,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1334 = VMLALsluv2i32
  { 1335,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1335 = VMLALsluv4i16
  { 1336,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1336 = VMLALsv2i64
  { 1337,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1337 = VMLALsv4i32
  { 1338,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1338 = VMLALsv8i16
  { 1339,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1339 = VMLALuv2i64
  { 1340,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1340 = VMLALuv4i32
  { 1341,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1341 = VMLALuv8i16
  { 1342,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #1342 = VMLAS
  { 1343,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1343 = VMLAfd
  { 1344,	6,	1,	467,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1344 = VMLAfq
  { 1345,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1345 = VMLAslfd
  { 1346,	7,	1,	467,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1346 = VMLAslfq
  { 1347,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1347 = VMLAslv2i32
  { 1348,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo200,0,0 },  // Inst #1348 = VMLAslv4i16
  { 1349,	7,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1349 = VMLAslv4i32
  { 1350,	7,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo201,0,0 },  // Inst #1350 = VMLAslv8i16
  { 1351,	6,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1351 = VMLAv16i8
  { 1352,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1352 = VMLAv2i32
  { 1353,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1353 = VMLAv4i16
  { 1354,	6,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1354 = VMLAv4i32
  { 1355,	6,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1355 = VMLAv8i16
  { 1356,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1356 = VMLAv8i8
  { 1357,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1357 = VMLSD
  { 1358,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1358 = VMLSLslsv2i32
  { 1359,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1359 = VMLSLslsv4i16
  { 1360,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1360 = VMLSLsluv2i32
  { 1361,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1361 = VMLSLsluv4i16
  { 1362,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1362 = VMLSLsv2i64
  { 1363,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1363 = VMLSLsv4i32
  { 1364,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1364 = VMLSLsv8i16
  { 1365,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1365 = VMLSLuv2i64
  { 1366,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1366 = VMLSLuv4i32
  { 1367,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1367 = VMLSLuv8i16
  { 1368,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #1368 = VMLSS
  { 1369,	6,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1369 = VMLSfd
  { 1370,	6,	1,	467,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1370 = VMLSfq
  { 1371,	7,	1,	466,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1371 = VMLSslfd
  { 1372,	7,	1,	467,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1372 = VMLSslfq
  { 1373,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo198,0,0 },  // Inst #1373 = VMLSslv2i32
  { 1374,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo200,0,0 },  // Inst #1374 = VMLSslv4i16
  { 1375,	7,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo199,0,0 },  // Inst #1375 = VMLSslv4i32
  { 1376,	7,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo201,0,0 },  // Inst #1376 = VMLSslv8i16
  { 1377,	6,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1377 = VMLSv16i8
  { 1378,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1378 = VMLSv2i32
  { 1379,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1379 = VMLSv4i16
  { 1380,	6,	1,	468,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1380 = VMLSv4i32
  { 1381,	6,	1,	469,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo125,0,0 },  // Inst #1381 = VMLSv8i16
  { 1382,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1382 = VMLSv8i8
  { 1383,	4,	1,	485,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1383 = VMOVD
  { 1384,	5,	1,	499,	4,	0|(1<<MCID_Predicable), 0x18a80ULL, NULL, NULL, OperandInfo202,0,0 },  // Inst #1384 = VMOVDRR
  { 1385,	5,	1,	485,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1385 = VMOVDcc
  { 1386,	4,	1,	489,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1386 = VMOVLsv2i64
  { 1387,	4,	1,	489,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1387 = VMOVLsv4i32
  { 1388,	4,	1,	489,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1388 = VMOVLsv8i16
  { 1389,	4,	1,	489,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1389 = VMOVLuv2i64
  { 1390,	4,	1,	489,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1390 = VMOVLuv4i32
  { 1391,	4,	1,	489,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo148,0,0 },  // Inst #1391 = VMOVLuv8i16
  { 1392,	4,	1,	490,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1392 = VMOVNv2i32
  { 1393,	4,	1,	490,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1393 = VMOVNv4i16
  { 1394,	4,	1,	490,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1394 = VMOVNv8i8
  { 1395,	5,	2,	498,	4,	0|(1<<MCID_Predicable), 0x18980ULL, NULL, NULL, OperandInfo204,0,0 },  // Inst #1395 = VMOVRRD
  { 1396,	6,	2,	498,	4,	0|(1<<MCID_Predicable), 0x18980ULL, NULL, NULL, OperandInfo205,0,0 },  // Inst #1396 = VMOVRRS
  { 1397,	4,	1,	495,	4,	0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18900ULL, NULL, NULL, OperandInfo206,0,0 },  // Inst #1397 = VMOVRS
  { 1398,	4,	1,	486,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1398 = VMOVS
  { 1399,	4,	1,	496,	4,	0|(1<<MCID_Bitcast)|(1<<MCID_Predicable), 0x18a00ULL, NULL, NULL, OperandInfo207,0,0 },  // Inst #1399 = VMOVSR
  { 1400,	6,	2,	500,	4,	0|(1<<MCID_Predicable), 0x18a80ULL, NULL, NULL, OperandInfo208,0,0 },  // Inst #1400 = VMOVSRR
  { 1401,	5,	1,	486,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo209,0,0 },  // Inst #1401 = VMOVScc
  { 1402,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1402 = VMOVv16i8
  { 1403,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1403 = VMOVv1i64
  { 1404,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1404 = VMOVv2f32
  { 1405,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1405 = VMOVv2i32
  { 1406,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1406 = VMOVv2i64
  { 1407,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1407 = VMOVv4f32
  { 1408,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1408 = VMOVv4i16
  { 1409,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1409 = VMOVv4i32
  { 1410,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1410 = VMOVv8i16
  { 1411,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1411 = VMOVv8i8
  { 1412,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1412 = VMRS
  { 1413,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1413 = VMRS_FPEXC
  { 1414,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1414 = VMRS_FPINST
  { 1415,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1415 = VMRS_FPINST2
  { 1416,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1416 = VMRS_FPSID
  { 1417,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1417 = VMRS_MVFR0
  { 1418,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1418 = VMRS_MVFR1
  { 1419,	3,	1,	503,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, ImplicitList9, NULL, OperandInfo36,0,0 },  // Inst #1419 = VMRS_MVFR2
  { 1420,	3,	0,	504,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1420 = VMSR
  { 1421,	3,	0,	504,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1421 = VMSR_FPEXC
  { 1422,	3,	0,	504,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1422 = VMSR_FPINST
  { 1423,	3,	0,	504,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1423 = VMSR_FPINST2
  { 1424,	3,	0,	504,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8c00ULL, NULL, ImplicitList9, OperandInfo36,0,0 },  // Inst #1424 = VMSR_FPSID
  { 1425,	5,	1,	459,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1425 = VMULD
  { 1426,	3,	1,	449,	4,	0, 0x11280ULL, NULL, NULL, OperandInfo211,0,0 },  // Inst #1426 = VMULLp64
  { 1427,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1427 = VMULLp8
  { 1428,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo212,0,0 },  // Inst #1428 = VMULLslsv2i32
  { 1429,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo213,0,0 },  // Inst #1429 = VMULLslsv4i16
  { 1430,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo212,0,0 },  // Inst #1430 = VMULLsluv2i32
  { 1431,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo213,0,0 },  // Inst #1431 = VMULLsluv4i16
  { 1432,	5,	1,	451,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1432 = VMULLsv2i64
  { 1433,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1433 = VMULLsv4i32
  { 1434,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1434 = VMULLsv8i16
  { 1435,	5,	1,	451,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1435 = VMULLuv2i64
  { 1436,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1436 = VMULLuv4i32
  { 1437,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1437 = VMULLuv8i16
  { 1438,	5,	1,	452,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1438 = VMULS
  { 1439,	5,	1,	453,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1439 = VMULfd
  { 1440,	5,	1,	454,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1440 = VMULfq
  { 1441,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1441 = VMULpd
  { 1442,	5,	1,	455,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1442 = VMULpq
  { 1443,	6,	1,	456,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo214,0,0 },  // Inst #1443 = VMULslfd
  { 1444,	6,	1,	457,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1444 = VMULslfq
  { 1445,	6,	1,	451,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo214,0,0 },  // Inst #1445 = VMULslv2i32
  { 1446,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo216,0,0 },  // Inst #1446 = VMULslv4i16
  { 1447,	6,	1,	458,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1447 = VMULslv4i32
  { 1448,	6,	1,	455,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo217,0,0 },  // Inst #1448 = VMULslv8i16
  { 1449,	5,	1,	455,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1449 = VMULv16i8
  { 1450,	5,	1,	451,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1450 = VMULv2i32
  { 1451,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1451 = VMULv4i16
  { 1452,	5,	1,	458,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1452 = VMULv4i32
  { 1453,	5,	1,	455,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1453 = VMULv8i16
  { 1454,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1454 = VMULv8i8
  { 1455,	4,	1,	488,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1455 = VMVNd
  { 1456,	4,	1,	488,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1456 = VMVNq
  { 1457,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1457 = VMVNv2i32
  { 1458,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo51,0,0 },  // Inst #1458 = VMVNv4i16
  { 1459,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1459 = VMVNv4i32
  { 1460,	4,	1,	487,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x10f80ULL, NULL, NULL, OperandInfo210,0,0 },  // Inst #1460 = VMVNv8i16
  { 1461,	4,	1,	435,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1461 = VNEGD
  { 1462,	4,	1,	436,	4,	0|(1<<MCID_Predicable), 0x28780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1462 = VNEGS
  { 1463,	4,	1,	388,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1463 = VNEGf32q
  { 1464,	4,	1,	389,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1464 = VNEGfd
  { 1465,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1465 = VNEGs16d
  { 1466,	4,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1466 = VNEGs16q
  { 1467,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1467 = VNEGs32d
  { 1468,	4,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1468 = VNEGs32q
  { 1469,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1469 = VNEGs8d
  { 1470,	4,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1470 = VNEGs8q
  { 1471,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1471 = VNMLAD
  { 1472,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #1472 = VNMLAS
  { 1473,	6,	1,	462,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo126,0,0 },  // Inst #1473 = VNMLSD
  { 1474,	6,	1,	465,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo155,0,0 },  // Inst #1474 = VNMLSS
  { 1475,	5,	1,	459,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1475 = VNMULD
  { 1476,	5,	1,	452,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #1476 = VNMULS
  { 1477,	5,	1,	380,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1477 = VORNd
  { 1478,	5,	1,	379,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1478 = VORNq
  { 1479,	5,	1,	380,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1479 = VORRd
  { 1480,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #1480 = VORRiv2i32
  { 1481,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo136,0,0 },  // Inst #1481 = VORRiv4i16
  { 1482,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #1482 = VORRiv4i32
  { 1483,	5,	1,	381,	4,	0|(1<<MCID_Predicable), 0x10f80ULL, NULL, NULL, OperandInfo137,0,0 },  // Inst #1483 = VORRiv8i16
  { 1484,	5,	1,	379,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1484 = VORRq
  { 1485,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1485 = VPADALsv16i8
  { 1486,	5,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1486 = VPADALsv2i32
  { 1487,	5,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1487 = VPADALsv4i16
  { 1488,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1488 = VPADALsv4i32
  { 1489,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1489 = VPADALsv8i16
  { 1490,	5,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1490 = VPADALsv8i8
  { 1491,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1491 = VPADALuv16i8
  { 1492,	5,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1492 = VPADALuv2i32
  { 1493,	5,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1493 = VPADALuv4i16
  { 1494,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1494 = VPADALuv4i32
  { 1495,	5,	1,	409,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo218,0,0 },  // Inst #1495 = VPADALuv8i16
  { 1496,	5,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo203,0,0 },  // Inst #1496 = VPADALuv8i8
  { 1497,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1497 = VPADDLsv16i8
  { 1498,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1498 = VPADDLsv2i32
  { 1499,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1499 = VPADDLsv4i16
  { 1500,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1500 = VPADDLsv4i32
  { 1501,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1501 = VPADDLsv8i16
  { 1502,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1502 = VPADDLsv8i8
  { 1503,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1503 = VPADDLuv16i8
  { 1504,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1504 = VPADDLuv2i32
  { 1505,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1505 = VPADDLuv4i16
  { 1506,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1506 = VPADDLuv4i32
  { 1507,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1507 = VPADDLuv8i16
  { 1508,	4,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1508 = VPADDLuv8i8
  { 1509,	5,	1,	445,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1509 = VPADDf
  { 1510,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1510 = VPADDi16
  { 1511,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1511 = VPADDi32
  { 1512,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1512 = VPADDi8
  { 1513,	5,	1,	445,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1513 = VPMAXf
  { 1514,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1514 = VPMAXs16
  { 1515,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1515 = VPMAXs32
  { 1516,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1516 = VPMAXs8
  { 1517,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1517 = VPMAXu16
  { 1518,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1518 = VPMAXu32
  { 1519,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1519 = VPMAXu8
  { 1520,	5,	1,	445,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1520 = VPMINf
  { 1521,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1521 = VPMINs16
  { 1522,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1522 = VPMINs32
  { 1523,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1523 = VPMINs8
  { 1524,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1524 = VPMINu16
  { 1525,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1525 = VPMINu32
  { 1526,	5,	1,	442,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1526 = VPMINu8
  { 1527,	4,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1527 = VQABSv16i8
  { 1528,	4,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1528 = VQABSv2i32
  { 1529,	4,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1529 = VQABSv4i16
  { 1530,	4,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1530 = VQABSv4i32
  { 1531,	4,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1531 = VQABSv8i16
  { 1532,	4,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1532 = VQABSv8i8
  { 1533,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1533 = VQADDsv16i8
  { 1534,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1534 = VQADDsv1i64
  { 1535,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1535 = VQADDsv2i32
  { 1536,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1536 = VQADDsv2i64
  { 1537,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1537 = VQADDsv4i16
  { 1538,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1538 = VQADDsv4i32
  { 1539,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1539 = VQADDsv8i16
  { 1540,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1540 = VQADDsv8i8
  { 1541,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1541 = VQADDuv16i8
  { 1542,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1542 = VQADDuv1i64
  { 1543,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1543 = VQADDuv2i32
  { 1544,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1544 = VQADDuv2i64
  { 1545,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1545 = VQADDuv4i16
  { 1546,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1546 = VQADDuv4i32
  { 1547,	5,	1,	413,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1547 = VQADDuv8i16
  { 1548,	5,	1,	414,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1548 = VQADDuv8i8
  { 1549,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1549 = VQDMLALslv2i32
  { 1550,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1550 = VQDMLALslv4i16
  { 1551,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1551 = VQDMLALv2i64
  { 1552,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1552 = VQDMLALv4i32
  { 1553,	7,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo196,0,0 },  // Inst #1553 = VQDMLSLslv2i32
  { 1554,	7,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo197,0,0 },  // Inst #1554 = VQDMLSLslv4i16
  { 1555,	6,	1,	463,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1555 = VQDMLSLv2i64
  { 1556,	6,	1,	464,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo124,0,0 },  // Inst #1556 = VQDMLSLv4i32
  { 1557,	6,	1,	451,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo214,0,0 },  // Inst #1557 = VQDMULHslv2i32
  { 1558,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo216,0,0 },  // Inst #1558 = VQDMULHslv4i16
  { 1559,	6,	1,	458,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1559 = VQDMULHslv4i32
  { 1560,	6,	1,	455,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo217,0,0 },  // Inst #1560 = VQDMULHslv8i16
  { 1561,	5,	1,	451,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1561 = VQDMULHv2i32
  { 1562,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1562 = VQDMULHv4i16
  { 1563,	5,	1,	458,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1563 = VQDMULHv4i32
  { 1564,	5,	1,	455,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1564 = VQDMULHv8i16
  { 1565,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo212,0,0 },  // Inst #1565 = VQDMULLslv2i32
  { 1566,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo213,0,0 },  // Inst #1566 = VQDMULLslv4i16
  { 1567,	5,	1,	451,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1567 = VQDMULLv2i64
  { 1568,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #1568 = VQDMULLv4i32
  { 1569,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1569 = VQMOVNsuv2i32
  { 1570,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1570 = VQMOVNsuv4i16
  { 1571,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1571 = VQMOVNsuv8i8
  { 1572,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1572 = VQMOVNsv2i32
  { 1573,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1573 = VQMOVNsv4i16
  { 1574,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1574 = VQMOVNsv8i8
  { 1575,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1575 = VQMOVNuv2i32
  { 1576,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1576 = VQMOVNuv4i16
  { 1577,	4,	1,	491,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo145,0,0 },  // Inst #1577 = VQMOVNuv8i8
  { 1578,	4,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1578 = VQNEGv16i8
  { 1579,	4,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1579 = VQNEGv2i32
  { 1580,	4,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1580 = VQNEGv4i16
  { 1581,	4,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1581 = VQNEGv4i32
  { 1582,	4,	1,	411,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1582 = VQNEGv8i16
  { 1583,	4,	1,	412,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1583 = VQNEGv8i8
  { 1584,	6,	1,	451,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo214,0,0 },  // Inst #1584 = VQRDMULHslv2i32
  { 1585,	6,	1,	450,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo216,0,0 },  // Inst #1585 = VQRDMULHslv4i16
  { 1586,	6,	1,	458,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo215,0,0 },  // Inst #1586 = VQRDMULHslv4i32
  { 1587,	6,	1,	455,	4,	0|(1<<MCID_Predicable), 0x11400ULL, NULL, NULL, OperandInfo217,0,0 },  // Inst #1587 = VQRDMULHslv8i16
  { 1588,	5,	1,	451,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1588 = VQRDMULHv2i32
  { 1589,	5,	1,	450,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1589 = VQRDMULHv4i16
  { 1590,	5,	1,	458,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1590 = VQRDMULHv4i32
  { 1591,	5,	1,	455,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1591 = VQRDMULHv8i16
  { 1592,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1592 = VQRSHLsv16i8
  { 1593,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1593 = VQRSHLsv1i64
  { 1594,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1594 = VQRSHLsv2i32
  { 1595,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1595 = VQRSHLsv2i64
  { 1596,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1596 = VQRSHLsv4i16
  { 1597,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1597 = VQRSHLsv4i32
  { 1598,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1598 = VQRSHLsv8i16
  { 1599,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1599 = VQRSHLsv8i8
  { 1600,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1600 = VQRSHLuv16i8
  { 1601,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1601 = VQRSHLuv1i64
  { 1602,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1602 = VQRSHLuv2i32
  { 1603,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1603 = VQRSHLuv2i64
  { 1604,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1604 = VQRSHLuv4i16
  { 1605,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1605 = VQRSHLuv4i32
  { 1606,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1606 = VQRSHLuv8i16
  { 1607,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1607 = VQRSHLuv8i8
  { 1608,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1608 = VQRSHRNsv2i32
  { 1609,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1609 = VQRSHRNsv4i16
  { 1610,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1610 = VQRSHRNsv8i8
  { 1611,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1611 = VQRSHRNuv2i32
  { 1612,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1612 = VQRSHRNuv4i16
  { 1613,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1613 = VQRSHRNuv8i8
  { 1614,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1614 = VQRSHRUNv2i32
  { 1615,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1615 = VQRSHRUNv4i16
  { 1616,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1616 = VQRSHRUNv8i8
  { 1617,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1617 = VQSHLsiv16i8
  { 1618,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1618 = VQSHLsiv1i64
  { 1619,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1619 = VQSHLsiv2i32
  { 1620,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1620 = VQSHLsiv2i64
  { 1621,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1621 = VQSHLsiv4i16
  { 1622,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1622 = VQSHLsiv4i32
  { 1623,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1623 = VQSHLsiv8i16
  { 1624,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1624 = VQSHLsiv8i8
  { 1625,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1625 = VQSHLsuv16i8
  { 1626,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1626 = VQSHLsuv1i64
  { 1627,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1627 = VQSHLsuv2i32
  { 1628,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1628 = VQSHLsuv2i64
  { 1629,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1629 = VQSHLsuv4i16
  { 1630,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1630 = VQSHLsuv4i32
  { 1631,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1631 = VQSHLsuv8i16
  { 1632,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1632 = VQSHLsuv8i8
  { 1633,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1633 = VQSHLsv16i8
  { 1634,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1634 = VQSHLsv1i64
  { 1635,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1635 = VQSHLsv2i32
  { 1636,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1636 = VQSHLsv2i64
  { 1637,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1637 = VQSHLsv4i16
  { 1638,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1638 = VQSHLsv4i32
  { 1639,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1639 = VQSHLsv8i16
  { 1640,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1640 = VQSHLsv8i8
  { 1641,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1641 = VQSHLuiv16i8
  { 1642,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1642 = VQSHLuiv1i64
  { 1643,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1643 = VQSHLuiv2i32
  { 1644,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1644 = VQSHLuiv2i64
  { 1645,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1645 = VQSHLuiv4i16
  { 1646,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1646 = VQSHLuiv4i32
  { 1647,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1647 = VQSHLuiv8i16
  { 1648,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1648 = VQSHLuiv8i8
  { 1649,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1649 = VQSHLuv16i8
  { 1650,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1650 = VQSHLuv1i64
  { 1651,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1651 = VQSHLuv2i32
  { 1652,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1652 = VQSHLuv2i64
  { 1653,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1653 = VQSHLuv4i16
  { 1654,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1654 = VQSHLuv4i32
  { 1655,	5,	1,	392,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1655 = VQSHLuv8i16
  { 1656,	5,	1,	391,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1656 = VQSHLuv8i8
  { 1657,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1657 = VQSHRNsv2i32
  { 1658,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1658 = VQSHRNsv4i16
  { 1659,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1659 = VQSHRNsv8i8
  { 1660,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1660 = VQSHRNuv2i32
  { 1661,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1661 = VQSHRNuv4i16
  { 1662,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1662 = VQSHRNuv8i8
  { 1663,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1663 = VQSHRUNv2i32
  { 1664,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1664 = VQSHRUNv4i16
  { 1665,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1665 = VQSHRUNv8i8
  { 1666,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1666 = VQSUBsv16i8
  { 1667,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1667 = VQSUBsv1i64
  { 1668,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1668 = VQSUBsv2i32
  { 1669,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1669 = VQSUBsv2i64
  { 1670,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1670 = VQSUBsv4i16
  { 1671,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1671 = VQSUBsv4i32
  { 1672,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1672 = VQSUBsv8i16
  { 1673,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1673 = VQSUBsv8i8
  { 1674,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1674 = VQSUBuv16i8
  { 1675,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1675 = VQSUBuv1i64
  { 1676,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1676 = VQSUBuv2i32
  { 1677,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1677 = VQSUBuv2i64
  { 1678,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1678 = VQSUBuv4i16
  { 1679,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1679 = VQSUBuv4i32
  { 1680,	5,	1,	406,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1680 = VQSUBuv8i16
  { 1681,	5,	1,	407,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1681 = VQSUBuv8i8
  { 1682,	5,	1,	422,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1682 = VRADDHNv2i32
  { 1683,	5,	1,	422,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1683 = VRADDHNv4i16
  { 1684,	5,	1,	422,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1684 = VRADDHNv8i8
  { 1685,	4,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1685 = VRECPEd
  { 1686,	4,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1686 = VRECPEfd
  { 1687,	4,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1687 = VRECPEfq
  { 1688,	4,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1688 = VRECPEq
  { 1689,	5,	1,	447,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1689 = VRECPSfd
  { 1690,	5,	1,	448,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1690 = VRECPSfq
  { 1691,	4,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1691 = VREV16d8
  { 1692,	4,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1692 = VREV16q8
  { 1693,	4,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1693 = VREV32d16
  { 1694,	4,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1694 = VREV32d8
  { 1695,	4,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1695 = VREV32q16
  { 1696,	4,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1696 = VREV32q8
  { 1697,	4,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1697 = VREV64d16
  { 1698,	4,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1698 = VREV64d32
  { 1699,	4,	1,	396,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1699 = VREV64d8
  { 1700,	4,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1700 = VREV64q16
  { 1701,	4,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1701 = VREV64q32
  { 1702,	4,	1,	397,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1702 = VREV64q8
  { 1703,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1703 = VRHADDsv16i8
  { 1704,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1704 = VRHADDsv2i32
  { 1705,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1705 = VRHADDsv4i16
  { 1706,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1706 = VRHADDsv4i32
  { 1707,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1707 = VRHADDsv8i16
  { 1708,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1708 = VRHADDsv8i8
  { 1709,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1709 = VRHADDuv16i8
  { 1710,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1710 = VRHADDuv2i32
  { 1711,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1711 = VRHADDuv4i16
  { 1712,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1712 = VRHADDuv4i32
  { 1713,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1713 = VRHADDuv8i16
  { 1714,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1714 = VRHADDuv8i8
  { 1715,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1715 = VRINTAD
  { 1716,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1716 = VRINTAND
  { 1717,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1717 = VRINTANQ
  { 1718,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #1718 = VRINTAS
  { 1719,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1719 = VRINTMD
  { 1720,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1720 = VRINTMND
  { 1721,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1721 = VRINTMNQ
  { 1722,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #1722 = VRINTMS
  { 1723,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1723 = VRINTND
  { 1724,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1724 = VRINTNND
  { 1725,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1725 = VRINTNNQ
  { 1726,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #1726 = VRINTNS
  { 1727,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1727 = VRINTPD
  { 1728,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1728 = VRINTPND
  { 1729,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1729 = VRINTPNQ
  { 1730,	2,	1,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo142,0,0 },  // Inst #1730 = VRINTPS
  { 1731,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1731 = VRINTRD
  { 1732,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1732 = VRINTRS
  { 1733,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1733 = VRINTXD
  { 1734,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1734 = VRINTXND
  { 1735,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1735 = VRINTXNQ
  { 1736,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1736 = VRINTXS
  { 1737,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1737 = VRINTZD
  { 1738,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo140,0,0 },  // Inst #1738 = VRINTZND
  { 1739,	2,	1,	0,	4,	0, 0x11000ULL, NULL, NULL, OperandInfo24,0,0 },  // Inst #1739 = VRINTZNQ
  { 1740,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1740 = VRINTZS
  { 1741,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1741 = VRSHLsv16i8
  { 1742,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1742 = VRSHLsv1i64
  { 1743,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1743 = VRSHLsv2i32
  { 1744,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1744 = VRSHLsv2i64
  { 1745,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1745 = VRSHLsv4i16
  { 1746,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1746 = VRSHLsv4i32
  { 1747,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1747 = VRSHLsv8i16
  { 1748,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1748 = VRSHLsv8i8
  { 1749,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1749 = VRSHLuv16i8
  { 1750,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1750 = VRSHLuv1i64
  { 1751,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1751 = VRSHLuv2i32
  { 1752,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1752 = VRSHLuv2i64
  { 1753,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1753 = VRSHLuv4i16
  { 1754,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1754 = VRSHLuv4i32
  { 1755,	5,	1,	415,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1755 = VRSHLuv8i16
  { 1756,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1756 = VRSHLuv8i8
  { 1757,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1757 = VRSHRNv2i32
  { 1758,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1758 = VRSHRNv4i16
  { 1759,	5,	1,	421,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1759 = VRSHRNv8i8
  { 1760,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1760 = VRSHRsv16i8
  { 1761,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1761 = VRSHRsv1i64
  { 1762,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1762 = VRSHRsv2i32
  { 1763,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1763 = VRSHRsv2i64
  { 1764,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1764 = VRSHRsv4i16
  { 1765,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1765 = VRSHRsv4i32
  { 1766,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1766 = VRSHRsv8i16
  { 1767,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1767 = VRSHRsv8i8
  { 1768,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1768 = VRSHRuv16i8
  { 1769,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1769 = VRSHRuv1i64
  { 1770,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1770 = VRSHRuv2i32
  { 1771,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1771 = VRSHRuv2i64
  { 1772,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1772 = VRSHRuv4i16
  { 1773,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1773 = VRSHRuv4i32
  { 1774,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1774 = VRSHRuv8i16
  { 1775,	5,	1,	416,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1775 = VRSHRuv8i8
  { 1776,	4,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1776 = VRSQRTEd
  { 1777,	4,	1,	417,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1777 = VRSQRTEfd
  { 1778,	4,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1778 = VRSQRTEfq
  { 1779,	4,	1,	418,	4,	0|(1<<MCID_Predicable), 0x11000ULL, NULL, NULL, OperandInfo132,0,0 },  // Inst #1779 = VRSQRTEq
  { 1780,	5,	1,	447,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1780 = VRSQRTSfd
  { 1781,	5,	1,	448,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1781 = VRSQRTSfq
  { 1782,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1782 = VRSRAsv16i8
  { 1783,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1783 = VRSRAsv1i64
  { 1784,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1784 = VRSRAsv2i32
  { 1785,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1785 = VRSRAsv2i64
  { 1786,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1786 = VRSRAsv4i16
  { 1787,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1787 = VRSRAsv4i32
  { 1788,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1788 = VRSRAsv8i16
  { 1789,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1789 = VRSRAsv8i8
  { 1790,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1790 = VRSRAuv16i8
  { 1791,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1791 = VRSRAuv1i64
  { 1792,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1792 = VRSRAuv2i32
  { 1793,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1793 = VRSRAuv2i64
  { 1794,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1794 = VRSRAuv4i16
  { 1795,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1795 = VRSRAuv4i32
  { 1796,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1796 = VRSRAuv8i16
  { 1797,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1797 = VRSRAuv8i8
  { 1798,	5,	1,	422,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1798 = VRSUBHNv2i32
  { 1799,	5,	1,	422,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1799 = VRSUBHNv4i16
  { 1800,	5,	1,	422,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #1800 = VRSUBHNv8i8
  { 1801,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo193,0,0 },  // Inst #1801 = VSELEQD
  { 1802,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo195,0,0 },  // Inst #1802 = VSELEQS
  { 1803,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo193,0,0 },  // Inst #1803 = VSELGED
  { 1804,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo195,0,0 },  // Inst #1804 = VSELGES
  { 1805,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo193,0,0 },  // Inst #1805 = VSELGTD
  { 1806,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo195,0,0 },  // Inst #1806 = VSELGTS
  { 1807,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo193,0,0 },  // Inst #1807 = VSELVSD
  { 1808,	3,	1,	0,	4,	0, 0x8800ULL, ImplicitList1, NULL, OperandInfo195,0,0 },  // Inst #1808 = VSELVSS
  { 1809,	6,	1,	497,	4,	0|(1<<MCID_Predicable), 0x10e00ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1809 = VSETLNi16
  { 1810,	6,	1,	497,	4,	0|(1<<MCID_Predicable), 0x10e00ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1810 = VSETLNi32
  { 1811,	6,	1,	497,	4,	0|(1<<MCID_Predicable), 0x10e00ULL, NULL, NULL, OperandInfo224,0,0 },  // Inst #1811 = VSETLNi8
  { 1812,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1812 = VSHLLi16
  { 1813,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1813 = VSHLLi32
  { 1814,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1814 = VSHLLi8
  { 1815,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1815 = VSHLLsv2i64
  { 1816,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1816 = VSHLLsv4i32
  { 1817,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1817 = VSHLLsv8i16
  { 1818,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1818 = VSHLLuv2i64
  { 1819,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1819 = VSHLLuv4i32
  { 1820,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo151,0,0 },  // Inst #1820 = VSHLLuv8i16
  { 1821,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1821 = VSHLiv16i8
  { 1822,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1822 = VSHLiv1i64
  { 1823,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1823 = VSHLiv2i32
  { 1824,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1824 = VSHLiv2i64
  { 1825,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1825 = VSHLiv4i16
  { 1826,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1826 = VSHLiv4i32
  { 1827,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo220,0,0 },  // Inst #1827 = VSHLiv8i16
  { 1828,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo221,0,0 },  // Inst #1828 = VSHLiv8i8
  { 1829,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1829 = VSHLsv16i8
  { 1830,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1830 = VSHLsv1i64
  { 1831,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1831 = VSHLsv2i32
  { 1832,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1832 = VSHLsv2i64
  { 1833,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1833 = VSHLsv4i16
  { 1834,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1834 = VSHLsv4i32
  { 1835,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1835 = VSHLsv8i16
  { 1836,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1836 = VSHLsv8i8
  { 1837,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1837 = VSHLuv16i8
  { 1838,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1838 = VSHLuv1i64
  { 1839,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1839 = VSHLuv2i32
  { 1840,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1840 = VSHLuv2i64
  { 1841,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1841 = VSHLuv4i16
  { 1842,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1842 = VSHLuv4i32
  { 1843,	5,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #1843 = VSHLuv8i16
  { 1844,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11300ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #1844 = VSHLuv8i8
  { 1845,	5,	1,	420,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1845 = VSHRNv2i32
  { 1846,	5,	1,	420,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1846 = VSHRNv4i16
  { 1847,	5,	1,	420,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo219,0,0 },  // Inst #1847 = VSHRNv8i8
  { 1848,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1848 = VSHRsv16i8
  { 1849,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1849 = VSHRsv1i64
  { 1850,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1850 = VSHRsv2i32
  { 1851,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1851 = VSHRsv2i64
  { 1852,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1852 = VSHRsv4i16
  { 1853,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1853 = VSHRsv4i32
  { 1854,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1854 = VSHRsv8i16
  { 1855,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1855 = VSHRsv8i8
  { 1856,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1856 = VSHRuv16i8
  { 1857,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1857 = VSHRuv1i64
  { 1858,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1858 = VSHRuv2i32
  { 1859,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1859 = VSHRuv2i64
  { 1860,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1860 = VSHRuv4i16
  { 1861,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1861 = VSHRuv4i32
  { 1862,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo147,0,0 },  // Inst #1862 = VSHRuv8i16
  { 1863,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo146,0,0 },  // Inst #1863 = VSHRuv8i8
  { 1864,	5,	1,	187,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #1864 = VSHTOD
  { 1865,	5,	1,	188,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #1865 = VSHTOS
  { 1866,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #1866 = VSITOD
  { 1867,	4,	1,	480,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1867 = VSITOS
  { 1868,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #1868 = VSLIv16i8
  { 1869,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1869 = VSLIv1i64
  { 1870,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1870 = VSLIv2i32
  { 1871,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #1871 = VSLIv2i64
  { 1872,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1872 = VSLIv4i16
  { 1873,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #1873 = VSLIv4i32
  { 1874,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo227,0,0 },  // Inst #1874 = VSLIv8i16
  { 1875,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11180ULL, NULL, NULL, OperandInfo228,0,0 },  // Inst #1875 = VSLIv8i8
  { 1876,	5,	1,	187,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #1876 = VSLTOD
  { 1877,	5,	1,	188,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #1877 = VSLTOS
  { 1878,	4,	1,	587,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo130,0,0 },  // Inst #1878 = VSQRTD
  { 1879,	4,	1,	585,	4,	0|(1<<MCID_Predicable), 0x8780ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #1879 = VSQRTS
  { 1880,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1880 = VSRAsv16i8
  { 1881,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1881 = VSRAsv1i64
  { 1882,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1882 = VSRAsv2i32
  { 1883,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1883 = VSRAsv2i64
  { 1884,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1884 = VSRAsv4i16
  { 1885,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1885 = VSRAsv4i32
  { 1886,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1886 = VSRAsv8i16
  { 1887,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1887 = VSRAsv8i8
  { 1888,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1888 = VSRAuv16i8
  { 1889,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1889 = VSRAuv1i64
  { 1890,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1890 = VSRAuv2i32
  { 1891,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1891 = VSRAuv2i64
  { 1892,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1892 = VSRAuv4i16
  { 1893,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1893 = VSRAuv4i32
  { 1894,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1894 = VSRAuv8i16
  { 1895,	6,	1,	410,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1895 = VSRAuv8i8
  { 1896,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1896 = VSRIv16i8
  { 1897,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1897 = VSRIv1i64
  { 1898,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1898 = VSRIv2i32
  { 1899,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1899 = VSRIv2i64
  { 1900,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1900 = VSRIv4i16
  { 1901,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1901 = VSRIv4i32
  { 1902,	6,	1,	390,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo222,0,0 },  // Inst #1902 = VSRIv8i16
  { 1903,	6,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11200ULL, NULL, NULL, OperandInfo223,0,0 },  // Inst #1903 = VSRIv8i8
  { 1904,	6,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo229,0,0 },  // Inst #1904 = VST1LNd16
  { 1905,	8,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo230,0,0 },  // Inst #1905 = VST1LNd16_UPD
  { 1906,	6,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo229,0,0 },  // Inst #1906 = VST1LNd32
  { 1907,	8,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo230,0,0 },  // Inst #1907 = VST1LNd32_UPD
  { 1908,	6,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo229,0,0 },  // Inst #1908 = VST1LNd8
  { 1909,	8,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10f06ULL, NULL, NULL, OperandInfo230,0,0 },  // Inst #1909 = VST1LNd8_UPD
  { 1910,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1910 = VST1LNdAsm_16
  { 1911,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1911 = VST1LNdAsm_32
  { 1912,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1912 = VST1LNdAsm_8
  { 1913,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1913 = VST1LNdWB_fixed_Asm_16
  { 1914,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1914 = VST1LNdWB_fixed_Asm_32
  { 1915,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1915 = VST1LNdWB_fixed_Asm_8
  { 1916,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1916 = VST1LNdWB_register_Asm_16
  { 1917,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1917 = VST1LNdWB_register_Asm_32
  { 1918,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1918 = VST1LNdWB_register_Asm_8
  { 1919,	6,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1919 = VST1LNq16Pseudo
  { 1920,	8,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1920 = VST1LNq16Pseudo_UPD
  { 1921,	6,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1921 = VST1LNq32Pseudo
  { 1922,	8,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1922 = VST1LNq32Pseudo_UPD
  { 1923,	6,	0,	576,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1923 = VST1LNq8Pseudo
  { 1924,	8,	1,	577,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1924 = VST1LNq8Pseudo_UPD
  { 1925,	5,	0,	557,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1925 = VST1d16
  { 1926,	5,	0,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1926 = VST1d16Q
  { 1927,	6,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1927 = VST1d16Qwb_fixed
  { 1928,	7,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1928 = VST1d16Qwb_register
  { 1929,	5,	0,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1929 = VST1d16T
  { 1930,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1930 = VST1d16Twb_fixed
  { 1931,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1931 = VST1d16Twb_register
  { 1932,	6,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1932 = VST1d16wb_fixed
  { 1933,	7,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1933 = VST1d16wb_register
  { 1934,	5,	0,	557,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1934 = VST1d32
  { 1935,	5,	0,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1935 = VST1d32Q
  { 1936,	6,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1936 = VST1d32Qwb_fixed
  { 1937,	7,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1937 = VST1d32Qwb_register
  { 1938,	5,	0,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1938 = VST1d32T
  { 1939,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1939 = VST1d32Twb_fixed
  { 1940,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1940 = VST1d32Twb_register
  { 1941,	6,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1941 = VST1d32wb_fixed
  { 1942,	7,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1942 = VST1d32wb_register
  { 1943,	5,	0,	557,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1943 = VST1d64
  { 1944,	5,	0,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1944 = VST1d64Q
  { 1945,	5,	0,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1945 = VST1d64QPseudo
  { 1946,	7,	1,	566,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #1946 = VST1d64QPseudoWB_fixed
  { 1947,	7,	1,	566,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #1947 = VST1d64QPseudoWB_register
  { 1948,	6,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1948 = VST1d64Qwb_fixed
  { 1949,	7,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1949 = VST1d64Qwb_register
  { 1950,	5,	0,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1950 = VST1d64T
  { 1951,	5,	0,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #1951 = VST1d64TPseudo
  { 1952,	7,	1,	563,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #1952 = VST1d64TPseudoWB_fixed
  { 1953,	7,	1,	563,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #1953 = VST1d64TPseudoWB_register
  { 1954,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1954 = VST1d64Twb_fixed
  { 1955,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1955 = VST1d64Twb_register
  { 1956,	6,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1956 = VST1d64wb_fixed
  { 1957,	7,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1957 = VST1d64wb_register
  { 1958,	5,	0,	557,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1958 = VST1d8
  { 1959,	5,	0,	564,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1959 = VST1d8Q
  { 1960,	6,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1960 = VST1d8Qwb_fixed
  { 1961,	7,	1,	565,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1961 = VST1d8Qwb_register
  { 1962,	5,	0,	561,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #1962 = VST1d8T
  { 1963,	6,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1963 = VST1d8Twb_fixed
  { 1964,	7,	1,	562,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1964 = VST1d8Twb_register
  { 1965,	6,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #1965 = VST1d8wb_fixed
  { 1966,	7,	1,	559,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #1966 = VST1d8wb_register
  { 1967,	5,	0,	558,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1967 = VST1q16
  { 1968,	6,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1968 = VST1q16wb_fixed
  { 1969,	7,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1969 = VST1q16wb_register
  { 1970,	5,	0,	558,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1970 = VST1q32
  { 1971,	6,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1971 = VST1q32wb_fixed
  { 1972,	7,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1972 = VST1q32wb_register
  { 1973,	5,	0,	558,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1973 = VST1q64
  { 1974,	6,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1974 = VST1q64wb_fixed
  { 1975,	7,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1975 = VST1q64wb_register
  { 1976,	5,	0,	558,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #1976 = VST1q8
  { 1977,	6,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #1977 = VST1q8wb_fixed
  { 1978,	7,	1,	560,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #1978 = VST1q8wb_register
  { 1979,	7,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #1979 = VST2LNd16
  { 1980,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1980 = VST2LNd16Pseudo
  { 1981,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1981 = VST2LNd16Pseudo_UPD
  { 1982,	9,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #1982 = VST2LNd16_UPD
  { 1983,	7,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #1983 = VST2LNd32
  { 1984,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1984 = VST2LNd32Pseudo
  { 1985,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1985 = VST2LNd32Pseudo_UPD
  { 1986,	9,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #1986 = VST2LNd32_UPD
  { 1987,	7,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #1987 = VST2LNd8
  { 1988,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo231,0,0 },  // Inst #1988 = VST2LNd8Pseudo
  { 1989,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo232,0,0 },  // Inst #1989 = VST2LNd8Pseudo_UPD
  { 1990,	9,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #1990 = VST2LNd8_UPD
  { 1991,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1991 = VST2LNdAsm_16
  { 1992,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1992 = VST2LNdAsm_32
  { 1993,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1993 = VST2LNdAsm_8
  { 1994,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1994 = VST2LNdWB_fixed_Asm_16
  { 1995,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1995 = VST2LNdWB_fixed_Asm_32
  { 1996,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #1996 = VST2LNdWB_fixed_Asm_8
  { 1997,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1997 = VST2LNdWB_register_Asm_16
  { 1998,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1998 = VST2LNdWB_register_Asm_32
  { 1999,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #1999 = VST2LNdWB_register_Asm_8
  { 2000,	7,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2000 = VST2LNq16
  { 2001,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2001 = VST2LNq16Pseudo
  { 2002,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2002 = VST2LNq16Pseudo_UPD
  { 2003,	9,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #2003 = VST2LNq16_UPD
  { 2004,	7,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo241,0,0 },  // Inst #2004 = VST2LNq32
  { 2005,	6,	0,	578,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2005 = VST2LNq32Pseudo
  { 2006,	8,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2006 = VST2LNq32Pseudo_UPD
  { 2007,	9,	1,	579,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo242,0,0 },  // Inst #2007 = VST2LNq32_UPD
  { 2008,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2008 = VST2LNqAsm_16
  { 2009,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2009 = VST2LNqAsm_32
  { 2010,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2010 = VST2LNqWB_fixed_Asm_16
  { 2011,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2011 = VST2LNqWB_fixed_Asm_32
  { 2012,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2012 = VST2LNqWB_register_Asm_16
  { 2013,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2013 = VST2LNqWB_register_Asm_32
  { 2014,	5,	0,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2014 = VST2b16
  { 2015,	6,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2015 = VST2b16wb_fixed
  { 2016,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2016 = VST2b16wb_register
  { 2017,	5,	0,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2017 = VST2b32
  { 2018,	6,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2018 = VST2b32wb_fixed
  { 2019,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2019 = VST2b32wb_register
  { 2020,	5,	0,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2020 = VST2b8
  { 2021,	6,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2021 = VST2b8wb_fixed
  { 2022,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2022 = VST2b8wb_register
  { 2023,	5,	0,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2023 = VST2d16
  { 2024,	6,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2024 = VST2d16wb_fixed
  { 2025,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2025 = VST2d16wb_register
  { 2026,	5,	0,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2026 = VST2d32
  { 2027,	6,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2027 = VST2d32wb_fixed
  { 2028,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2028 = VST2d32wb_register
  { 2029,	5,	0,	567,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo238,0,0 },  // Inst #2029 = VST2d8
  { 2030,	6,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo239,0,0 },  // Inst #2030 = VST2d8wb_fixed
  { 2031,	7,	1,	568,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo240,0,0 },  // Inst #2031 = VST2d8wb_register
  { 2032,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #2032 = VST2q16
  { 2033,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2033 = VST2q16Pseudo
  { 2034,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2034 = VST2q16PseudoWB_fixed
  { 2035,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo246,0,0 },  // Inst #2035 = VST2q16PseudoWB_register
  { 2036,	6,	1,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #2036 = VST2q16wb_fixed
  { 2037,	7,	1,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #2037 = VST2q16wb_register
  { 2038,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #2038 = VST2q32
  { 2039,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2039 = VST2q32Pseudo
  { 2040,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2040 = VST2q32PseudoWB_fixed
  { 2041,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo246,0,0 },  // Inst #2041 = VST2q32PseudoWB_register
  { 2042,	6,	1,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #2042 = VST2q32wb_fixed
  { 2043,	7,	1,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #2043 = VST2q32wb_register
  { 2044,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo233,0,0 },  // Inst #2044 = VST2q8
  { 2045,	5,	0,	569,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2045 = VST2q8Pseudo
  { 2046,	6,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo245,0,0 },  // Inst #2046 = VST2q8PseudoWB_fixed
  { 2047,	7,	1,	570,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo246,0,0 },  // Inst #2047 = VST2q8PseudoWB_register
  { 2048,	6,	1,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo234,0,0 },  // Inst #2048 = VST2q8wb_fixed
  { 2049,	7,	1,	571,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo235,0,0 },  // Inst #2049 = VST2q8wb_register
  { 2050,	8,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2050 = VST3LNd16
  { 2051,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2051 = VST3LNd16Pseudo
  { 2052,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2052 = VST3LNd16Pseudo_UPD
  { 2053,	10,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2053 = VST3LNd16_UPD
  { 2054,	8,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2054 = VST3LNd32
  { 2055,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2055 = VST3LNd32Pseudo
  { 2056,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2056 = VST3LNd32Pseudo_UPD
  { 2057,	10,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2057 = VST3LNd32_UPD
  { 2058,	8,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2058 = VST3LNd8
  { 2059,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2059 = VST3LNd8Pseudo
  { 2060,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2060 = VST3LNd8Pseudo_UPD
  { 2061,	10,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2061 = VST3LNd8_UPD
  { 2062,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2062 = VST3LNdAsm_16
  { 2063,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2063 = VST3LNdAsm_32
  { 2064,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2064 = VST3LNdAsm_8
  { 2065,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2065 = VST3LNdWB_fixed_Asm_16
  { 2066,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2066 = VST3LNdWB_fixed_Asm_32
  { 2067,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2067 = VST3LNdWB_fixed_Asm_8
  { 2068,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2068 = VST3LNdWB_register_Asm_16
  { 2069,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2069 = VST3LNdWB_register_Asm_32
  { 2070,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2070 = VST3LNdWB_register_Asm_8
  { 2071,	8,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2071 = VST3LNq16
  { 2072,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2072 = VST3LNq16Pseudo
  { 2073,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2073 = VST3LNq16Pseudo_UPD
  { 2074,	10,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2074 = VST3LNq16_UPD
  { 2075,	8,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo247,0,0 },  // Inst #2075 = VST3LNq32
  { 2076,	6,	0,	580,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2076 = VST3LNq32Pseudo
  { 2077,	8,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2077 = VST3LNq32Pseudo_UPD
  { 2078,	10,	1,	581,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo248,0,0 },  // Inst #2078 = VST3LNq32_UPD
  { 2079,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2079 = VST3LNqAsm_16
  { 2080,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2080 = VST3LNqAsm_32
  { 2081,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2081 = VST3LNqWB_fixed_Asm_16
  { 2082,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2082 = VST3LNqWB_fixed_Asm_32
  { 2083,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2083 = VST3LNqWB_register_Asm_16
  { 2084,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2084 = VST3LNqWB_register_Asm_32
  { 2085,	7,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2085 = VST3d16
  { 2086,	5,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2086 = VST3d16Pseudo
  { 2087,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2087 = VST3d16Pseudo_UPD
  { 2088,	9,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2088 = VST3d16_UPD
  { 2089,	7,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2089 = VST3d32
  { 2090,	5,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2090 = VST3d32Pseudo
  { 2091,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2091 = VST3d32Pseudo_UPD
  { 2092,	9,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2092 = VST3d32_UPD
  { 2093,	7,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2093 = VST3d8
  { 2094,	5,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2094 = VST3d8Pseudo
  { 2095,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2095 = VST3d8Pseudo_UPD
  { 2096,	9,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2096 = VST3d8_UPD
  { 2097,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2097 = VST3dAsm_16
  { 2098,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2098 = VST3dAsm_32
  { 2099,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2099 = VST3dAsm_8
  { 2100,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2100 = VST3dWB_fixed_Asm_16
  { 2101,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2101 = VST3dWB_fixed_Asm_32
  { 2102,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2102 = VST3dWB_fixed_Asm_8
  { 2103,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2103 = VST3dWB_register_Asm_16
  { 2104,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2104 = VST3dWB_register_Asm_32
  { 2105,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2105 = VST3dWB_register_Asm_8
  { 2106,	7,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2106 = VST3q16
  { 2107,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2107 = VST3q16Pseudo_UPD
  { 2108,	9,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2108 = VST3q16_UPD
  { 2109,	5,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2109 = VST3q16oddPseudo
  { 2110,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2110 = VST3q16oddPseudo_UPD
  { 2111,	7,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2111 = VST3q32
  { 2112,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2112 = VST3q32Pseudo_UPD
  { 2113,	9,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2113 = VST3q32_UPD
  { 2114,	5,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2114 = VST3q32oddPseudo
  { 2115,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2115 = VST3q32oddPseudo_UPD
  { 2116,	7,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo251,0,0 },  // Inst #2116 = VST3q8
  { 2117,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2117 = VST3q8Pseudo_UPD
  { 2118,	9,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo252,0,0 },  // Inst #2118 = VST3q8_UPD
  { 2119,	5,	0,	572,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2119 = VST3q8oddPseudo
  { 2120,	7,	1,	573,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2120 = VST3q8oddPseudo_UPD
  { 2121,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2121 = VST3qAsm_16
  { 2122,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2122 = VST3qAsm_32
  { 2123,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2123 = VST3qAsm_8
  { 2124,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2124 = VST3qWB_fixed_Asm_16
  { 2125,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2125 = VST3qWB_fixed_Asm_32
  { 2126,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2126 = VST3qWB_fixed_Asm_8
  { 2127,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2127 = VST3qWB_register_Asm_16
  { 2128,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2128 = VST3qWB_register_Asm_32
  { 2129,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2129 = VST3qWB_register_Asm_8
  { 2130,	9,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2130 = VST4LNd16
  { 2131,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2131 = VST4LNd16Pseudo
  { 2132,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2132 = VST4LNd16Pseudo_UPD
  { 2133,	11,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2133 = VST4LNd16_UPD
  { 2134,	9,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2134 = VST4LNd32
  { 2135,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2135 = VST4LNd32Pseudo
  { 2136,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2136 = VST4LNd32Pseudo_UPD
  { 2137,	11,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2137 = VST4LNd32_UPD
  { 2138,	9,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2138 = VST4LNd8
  { 2139,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo243,0,0 },  // Inst #2139 = VST4LNd8Pseudo
  { 2140,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo244,0,0 },  // Inst #2140 = VST4LNd8Pseudo_UPD
  { 2141,	11,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2141 = VST4LNd8_UPD
  { 2142,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2142 = VST4LNdAsm_16
  { 2143,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2143 = VST4LNdAsm_32
  { 2144,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2144 = VST4LNdAsm_8
  { 2145,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2145 = VST4LNdWB_fixed_Asm_16
  { 2146,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2146 = VST4LNdWB_fixed_Asm_32
  { 2147,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2147 = VST4LNdWB_fixed_Asm_8
  { 2148,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2148 = VST4LNdWB_register_Asm_16
  { 2149,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2149 = VST4LNdWB_register_Asm_32
  { 2150,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2150 = VST4LNdWB_register_Asm_8
  { 2151,	9,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2151 = VST4LNq16
  { 2152,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2152 = VST4LNq16Pseudo
  { 2153,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2153 = VST4LNq16Pseudo_UPD
  { 2154,	11,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2154 = VST4LNq16_UPD
  { 2155,	9,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo255,0,0 },  // Inst #2155 = VST4LNq32
  { 2156,	6,	0,	582,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo249,0,0 },  // Inst #2156 = VST4LNq32Pseudo
  { 2157,	8,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo250,0,0 },  // Inst #2157 = VST4LNq32Pseudo_UPD
  { 2158,	11,	1,	583,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo256,0,0 },  // Inst #2158 = VST4LNq32_UPD
  { 2159,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2159 = VST4LNqAsm_16
  { 2160,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2160 = VST4LNqAsm_32
  { 2161,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2161 = VST4LNqWB_fixed_Asm_16
  { 2162,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo165,0,0 },  // Inst #2162 = VST4LNqWB_fixed_Asm_32
  { 2163,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2163 = VST4LNqWB_register_Asm_16
  { 2164,	7,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo166,0,0 },  // Inst #2164 = VST4LNqWB_register_Asm_32
  { 2165,	8,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2165 = VST4d16
  { 2166,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2166 = VST4d16Pseudo
  { 2167,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2167 = VST4d16Pseudo_UPD
  { 2168,	10,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2168 = VST4d16_UPD
  { 2169,	8,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2169 = VST4d32
  { 2170,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2170 = VST4d32Pseudo
  { 2171,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2171 = VST4d32Pseudo_UPD
  { 2172,	10,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2172 = VST4d32_UPD
  { 2173,	8,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2173 = VST4d8
  { 2174,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo236,0,0 },  // Inst #2174 = VST4d8Pseudo
  { 2175,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo237,0,0 },  // Inst #2175 = VST4d8Pseudo_UPD
  { 2176,	10,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2176 = VST4d8_UPD
  { 2177,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2177 = VST4dAsm_16
  { 2178,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2178 = VST4dAsm_32
  { 2179,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2179 = VST4dAsm_8
  { 2180,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2180 = VST4dWB_fixed_Asm_16
  { 2181,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2181 = VST4dWB_fixed_Asm_32
  { 2182,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2182 = VST4dWB_fixed_Asm_8
  { 2183,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2183 = VST4dWB_register_Asm_16
  { 2184,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2184 = VST4dWB_register_Asm_32
  { 2185,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2185 = VST4dWB_register_Asm_8
  { 2186,	8,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2186 = VST4q16
  { 2187,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2187 = VST4q16Pseudo_UPD
  { 2188,	10,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2188 = VST4q16_UPD
  { 2189,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2189 = VST4q16oddPseudo
  { 2190,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2190 = VST4q16oddPseudo_UPD
  { 2191,	8,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2191 = VST4q32
  { 2192,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2192 = VST4q32Pseudo_UPD
  { 2193,	10,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2193 = VST4q32_UPD
  { 2194,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2194 = VST4q32oddPseudo
  { 2195,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2195 = VST4q32oddPseudo_UPD
  { 2196,	8,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo257,0,0 },  // Inst #2196 = VST4q8
  { 2197,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2197 = VST4q8Pseudo_UPD
  { 2198,	10,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10f06ULL, NULL, NULL, OperandInfo258,0,0 },  // Inst #2198 = VST4q8_UPD
  { 2199,	5,	0,	574,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo254,0,0 },  // Inst #2199 = VST4q8oddPseudo
  { 2200,	7,	1,	575,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0x10006ULL, NULL, NULL, OperandInfo253,0,0 },  // Inst #2200 = VST4q8oddPseudo_UPD
  { 2201,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2201 = VST4qAsm_16
  { 2202,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2202 = VST4qAsm_32
  { 2203,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2203 = VST4qAsm_8
  { 2204,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2204 = VST4qWB_fixed_Asm_16
  { 2205,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2205 = VST4qWB_fixed_Asm_32
  { 2206,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo157,0,0 },  // Inst #2206 = VST4qWB_fixed_Asm_8
  { 2207,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2207 = VST4qWB_register_Asm_16
  { 2208,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2208 = VST4qWB_register_Asm_32
  { 2209,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo179,0,0 },  // Inst #2209 = VST4qWB_register_Asm_8
  { 2210,	5,	1,	515,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2210 = VSTMDDB_UPD
  { 2211,	4,	0,	514,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2211 = VSTMDIA
  { 2212,	5,	1,	515,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x8be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2212 = VSTMDIA_UPD
  { 2213,	4,	0,	511,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18004ULL, NULL, NULL, OperandInfo190,0,0 },  // Inst #2213 = VSTMQIA
  { 2214,	5,	1,	515,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2214 = VSTMSDB_UPD
  { 2215,	4,	0,	514,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18b84ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2215 = VSTMSIA
  { 2216,	5,	1,	515,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0x18be4ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2216 = VSTMSIA_UPD
  { 2217,	5,	0,	508,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, NULL, NULL, OperandInfo191,0,0 },  // Inst #2217 = VSTRD
  { 2218,	5,	0,	509,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0x18b05ULL, NULL, NULL, OperandInfo192,0,0 },  // Inst #2218 = VSTRS
  { 2219,	5,	1,	446,	4,	0|(1<<MCID_Predicable), 0x8800ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2219 = VSUBD
  { 2220,	5,	1,	419,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #2220 = VSUBHNv2i32
  { 2221,	5,	1,	419,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #2221 = VSUBHNv4i16
  { 2222,	5,	1,	419,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo133,0,0 },  // Inst #2222 = VSUBHNv8i8
  { 2223,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #2223 = VSUBLsv2i64
  { 2224,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #2224 = VSUBLsv4i32
  { 2225,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #2225 = VSUBLsv8i16
  { 2226,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #2226 = VSUBLuv2i64
  { 2227,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #2227 = VSUBLuv4i32
  { 2228,	5,	1,	377,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo127,0,0 },  // Inst #2228 = VSUBLuv8i16
  { 2229,	5,	1,	443,	4,	0|(1<<MCID_Predicable), 0x28800ULL, NULL, NULL, OperandInfo134,0,0 },  // Inst #2229 = VSUBS
  { 2230,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #2230 = VSUBWsv2i64
  { 2231,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #2231 = VSUBWsv4i32
  { 2232,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #2232 = VSUBWsv8i16
  { 2233,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #2233 = VSUBWuv2i64
  { 2234,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #2234 = VSUBWuv4i32
  { 2235,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo135,0,0 },  // Inst #2235 = VSUBWuv8i16
  { 2236,	5,	1,	440,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2236 = VSUBfd
  { 2237,	5,	1,	441,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2237 = VSUBfq
  { 2238,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2238 = VSUBv16i8
  { 2239,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2239 = VSUBv1i64
  { 2240,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2240 = VSUBv2i32
  { 2241,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2241 = VSUBv2i64
  { 2242,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2242 = VSUBv4i16
  { 2243,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2243 = VSUBv4i32
  { 2244,	5,	1,	393,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2244 = VSUBv8i16
  { 2245,	5,	1,	378,	4,	0|(1<<MCID_Predicable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2245 = VSUBv8i8
  { 2246,	6,	2,	431,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2246 = VSWPd
  { 2247,	6,	2,	431,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2247 = VSWPq
  { 2248,	5,	1,	423,	4,	0|(1<<MCID_Predicable), 0x11480ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2248 = VTBL1
  { 2249,	5,	1,	425,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo262,0,0 },  // Inst #2249 = VTBL2
  { 2250,	5,	1,	427,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2250 = VTBL3
  { 2251,	5,	1,	427,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo263,0,0 },  // Inst #2251 = VTBL3Pseudo
  { 2252,	5,	1,	429,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo261,0,0 },  // Inst #2252 = VTBL4
  { 2253,	5,	1,	429,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo263,0,0 },  // Inst #2253 = VTBL4Pseudo
  { 2254,	6,	1,	424,	4,	0|(1<<MCID_Predicable), 0x11480ULL, NULL, NULL, OperandInfo264,0,0 },  // Inst #2254 = VTBX1
  { 2255,	6,	1,	426,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo265,0,0 },  // Inst #2255 = VTBX2
  { 2256,	6,	1,	428,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo264,0,0 },  // Inst #2256 = VTBX3
  { 2257,	6,	1,	428,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo266,0,0 },  // Inst #2257 = VTBX3Pseudo
  { 2258,	6,	1,	430,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x11480ULL, NULL, NULL, OperandInfo264,0,0 },  // Inst #2258 = VTBX4
  { 2259,	6,	1,	430,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x10000ULL, NULL, NULL, OperandInfo266,0,0 },  // Inst #2259 = VTBX4Pseudo
  { 2260,	5,	1,	481,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #2260 = VTOSHD
  { 2261,	5,	1,	482,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2261 = VTOSHS
  { 2262,	4,	1,	483,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo143,0,0 },  // Inst #2262 = VTOSIRD
  { 2263,	4,	1,	484,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo131,0,0 },  // Inst #2263 = VTOSIRS
  { 2264,	4,	1,	483,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #2264 = VTOSIZD
  { 2265,	4,	1,	484,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #2265 = VTOSIZS
  { 2266,	5,	1,	481,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #2266 = VTOSLD
  { 2267,	5,	1,	482,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2267 = VTOSLS
  { 2268,	5,	1,	481,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #2268 = VTOUHD
  { 2269,	5,	1,	482,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2269 = VTOUHS
  { 2270,	4,	1,	483,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo143,0,0 },  // Inst #2270 = VTOUIRD
  { 2271,	4,	1,	484,	4,	0|(1<<MCID_Predicable), 0x8880ULL, ImplicitList9, NULL, OperandInfo131,0,0 },  // Inst #2271 = VTOUIRS
  { 2272,	4,	1,	483,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo143,0,0 },  // Inst #2272 = VTOUIZD
  { 2273,	4,	1,	484,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #2273 = VTOUIZS
  { 2274,	5,	1,	481,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #2274 = VTOULD
  { 2275,	5,	1,	482,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2275 = VTOULS
  { 2276,	6,	2,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2276 = VTRNd16
  { 2277,	6,	2,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2277 = VTRNd32
  { 2278,	6,	2,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2278 = VTRNd8
  { 2279,	6,	2,	433,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2279 = VTRNq16
  { 2280,	6,	2,	433,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2280 = VTRNq32
  { 2281,	6,	2,	433,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2281 = VTRNq8
  { 2282,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2282 = VTSTv16i8
  { 2283,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2283 = VTSTv2i32
  { 2284,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2284 = VTSTv4i16
  { 2285,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2285 = VTSTv4i32
  { 2286,	5,	1,	384,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo129,0,0 },  // Inst #2286 = VTSTv8i16
  { 2287,	5,	1,	385,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x11280ULL, NULL, NULL, OperandInfo128,0,0 },  // Inst #2287 = VTSTv8i8
  { 2288,	5,	1,	187,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #2288 = VUHTOD
  { 2289,	5,	1,	188,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2289 = VUHTOS
  { 2290,	4,	1,	479,	4,	0|(1<<MCID_Predicable), 0x8880ULL, NULL, NULL, OperandInfo144,0,0 },  // Inst #2290 = VUITOD
  { 2291,	4,	1,	480,	4,	0|(1<<MCID_Predicable), 0x28880ULL, NULL, NULL, OperandInfo131,0,0 },  // Inst #2291 = VUITOS
  { 2292,	5,	1,	187,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x8880ULL, NULL, NULL, OperandInfo225,0,0 },  // Inst #2292 = VULTOD
  { 2293,	5,	1,	188,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x28880ULL, NULL, NULL, OperandInfo226,0,0 },  // Inst #2293 = VULTOS
  { 2294,	6,	2,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2294 = VUZPd16
  { 2295,	6,	2,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2295 = VUZPd8
  { 2296,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2296 = VUZPq16
  { 2297,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2297 = VUZPq32
  { 2298,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2298 = VUZPq8
  { 2299,	6,	2,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2299 = VZIPd16
  { 2300,	6,	2,	432,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo259,0,0 },  // Inst #2300 = VZIPd8
  { 2301,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2301 = VZIPq16
  { 2302,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2302 = VZIPq32
  { 2303,	6,	2,	434,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x11000ULL, NULL, NULL, OperandInfo260,0,0 },  // Inst #2303 = VZIPq8
  { 2304,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2304 = sysLDMDA
  { 2305,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2305 = sysLDMDA_UPD
  { 2306,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2306 = sysLDMDB
  { 2307,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2307 = sysLDMDB_UPD
  { 2308,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2308 = sysLDMIA
  { 2309,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2309 = sysLDMIA_UPD
  { 2310,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2310 = sysLDMIB
  { 2311,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2311 = sysLDMIB_UPD
  { 2312,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2312 = sysSTMDA
  { 2313,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2313 = sysSTMDA_UPD
  { 2314,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2314 = sysSTMDB
  { 2315,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2315 = sysSTMDB_UPD
  { 2316,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2316 = sysSTMIA
  { 2317,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2317 = sysSTMIA_UPD
  { 2318,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x504ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2318 = sysSTMIB
  { 2319,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0x564ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2319 = sysSTMIB_UPD
  { 2320,	2,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList1, OperandInfo267,0,0 },  // Inst #2320 = t2ABS
  { 2321,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,0 },  // Inst #2321 = t2ADCri
  { 2322,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,0 },  // Inst #2322 = t2ADCrr
  { 2323,	7,	1,	56,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,0 },  // Inst #2323 = t2ADCrs
  { 2324,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo271,0,0 },  // Inst #2324 = t2ADDSri
  { 2325,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo272,0,0 },  // Inst #2325 = t2ADDSrr
  { 2326,	6,	1,	235,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo273,0,0 },  // Inst #2326 = t2ADDSrs
  { 2327,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo274,0,0 },  // Inst #2327 = t2ADDri
  { 2328,	5,	1,	1,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo275,0,0 },  // Inst #2328 = t2ADDri12
  { 2329,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo276,0,0 },  // Inst #2329 = t2ADDrr
  { 2330,	7,	1,	56,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo277,0,0 },  // Inst #2330 = t2ADDrs
  { 2331,	4,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo278,0,0 },  // Inst #2331 = t2ADR
  { 2332,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2332 = t2ANDri
  { 2333,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2333 = t2ANDrr
  { 2334,	7,	1,	57,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2334 = t2ANDrs
  { 2335,	6,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2335 = t2ASRri
  { 2336,	6,	1,	47,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2336 = t2ASRrr
  { 2337,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2337 = t2B
  { 2338,	5,	1,	296,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2338 = t2BFC
  { 2339,	6,	1,	297,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo280,0,0 },  // Inst #2339 = t2BFI
  { 2340,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2340 = t2BICri
  { 2341,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2341 = t2BICrr
  { 2342,	7,	1,	57,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2342 = t2BICrs
  { 2343,	4,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable), 0x0ULL, NULL, NULL, OperandInfo39,0,0 },  // Inst #2343 = t2BR_JT
  { 2344,	3,	0,	15,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo281,0,0 },  // Inst #2344 = t2BXJ
  { 2345,	3,	0,	10,	4,	0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2345 = t2Bcc
  { 2346,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo43,0,0 },  // Inst #2346 = t2CDP
  { 2347,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo43,0,0 },  // Inst #2347 = t2CDP2
  { 2348,	2,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2348 = t2CLREX
  { 2349,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo282,0,0 },  // Inst #2349 = t2CLZ
  { 2350,	4,	0,	17,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo283,0,0 },  // Inst #2350 = t2CMNri
  { 2351,	4,	0,	18,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2351 = t2CMNzrr
  { 2352,	5,	0,	237,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2352 = t2CMNzrs
  { 2353,	4,	0,	238,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo283,0,0 },  // Inst #2353 = t2CMPri
  { 2354,	4,	0,	239,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2354 = t2CMPrr
  { 2355,	5,	0,	240,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2355 = t2CMPrs
  { 2356,	1,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #2356 = t2CPS1p
  { 2357,	2,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #2357 = t2CPS2p
  { 2358,	3,	0,	0,	4,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo3,0,0 },  // Inst #2358 = t2CPS3p
  { 2359,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo286,0,0 },  // Inst #2359 = t2CRC32B
  { 2360,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo286,0,0 },  // Inst #2360 = t2CRC32CB
  { 2361,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo286,0,0 },  // Inst #2361 = t2CRC32CH
  { 2362,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo286,0,0 },  // Inst #2362 = t2CRC32CW
  { 2363,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo286,0,0 },  // Inst #2363 = t2CRC32H
  { 2364,	3,	1,	0,	4,	0, 0xc80ULL, NULL, NULL, OperandInfo286,0,0 },  // Inst #2364 = t2CRC32W
  { 2365,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2365 = t2DBG
  { 2366,	2,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2366 = t2DCPS1
  { 2367,	2,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2367 = t2DCPS2
  { 2368,	2,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2368 = t2DCPS3
  { 2369,	3,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2369 = t2DMB
  { 2370,	3,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2370 = t2DSB
  { 2371,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2371 = t2EORri
  { 2372,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2372 = t2EORrr
  { 2373,	7,	1,	57,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2373 = t2EORrs
  { 2374,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2374 = t2HINT
  { 2375,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2375 = t2ISB
  { 2376,	2,	0,	376,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList10, OperandInfo7,0,0 },  // Inst #2376 = t2IT
  { 2377,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList11, OperandInfo287,0,0 },  // Inst #2377 = t2Int_eh_sjlj_setjmp
  { 2378,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList7, OperandInfo287,0,0 },  // Inst #2378 = t2Int_eh_sjlj_setjmp_nofp
  { 2379,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2379 = t2LDA
  { 2380,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2380 = t2LDAB
  { 2381,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2381 = t2LDAEX
  { 2382,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2382 = t2LDAEXB
  { 2383,	5,	2,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2383 = t2LDAEXD
  { 2384,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2384 = t2LDAEXH
  { 2385,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2385 = t2LDAH
  { 2386,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2386 = t2LDC2L_OFFSET
  { 2387,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2387 = t2LDC2L_OPTION
  { 2388,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2388 = t2LDC2L_POST
  { 2389,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2389 = t2LDC2L_PRE
  { 2390,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2390 = t2LDC2_OFFSET
  { 2391,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2391 = t2LDC2_OPTION
  { 2392,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2392 = t2LDC2_POST
  { 2393,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2393 = t2LDC2_PRE
  { 2394,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2394 = t2LDCL_OFFSET
  { 2395,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2395 = t2LDCL_OPTION
  { 2396,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2396 = t2LDCL_POST
  { 2397,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2397 = t2LDCL_PRE
  { 2398,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2398 = t2LDC_OFFSET
  { 2399,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2399 = t2LDC_OPTION
  { 2400,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2400 = t2LDC_POST
  { 2401,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2401 = t2LDC_PRE
  { 2402,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2402 = t2LDMDB
  { 2403,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2403 = t2LDMDB_UPD
  { 2404,	4,	0,	352,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2404 = t2LDMIA
  { 2405,	5,	1,	354,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2405 = t2LDMIA_RET
  { 2406,	5,	1,	353,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2406 = t2LDMIA_UPD
  { 2407,	5,	1,	345,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2407 = t2LDRBT
  { 2408,	6,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2408 = t2LDRB_POST
  { 2409,	6,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2409 = t2LDRB_PRE
  { 2410,	5,	1,	328,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2410 = t2LDRBi12
  { 2411,	5,	1,	328,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2411 = t2LDRBi8
  { 2412,	4,	1,	328,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2412 = t2LDRBpci
  { 2413,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2413 = t2LDRBpcrel
  { 2414,	6,	1,	325,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2414 = t2LDRBs
  { 2415,	7,	3,	351,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2415 = t2LDRD_POST
  { 2416,	7,	3,	351,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo292,0,0 },  // Inst #2416 = t2LDRD_PRE
  { 2417,	6,	2,	350,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_ExtraDefRegAllocReq), 0xc8fULL, NULL, NULL, OperandInfo293,0,0 },  // Inst #2417 = t2LDRDi8
  { 2418,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo294,0,0 },  // Inst #2418 = t2LDREX
  { 2419,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2419 = t2LDREXB
  { 2420,	5,	2,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo289,0,0 },  // Inst #2420 = t2LDREXD
  { 2421,	4,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2421 = t2LDREXH
  { 2422,	5,	1,	345,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2422 = t2LDRHT
  { 2423,	6,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2423 = t2LDRH_POST
  { 2424,	6,	2,	341,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2424 = t2LDRH_PRE
  { 2425,	5,	1,	328,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2425 = t2LDRHi12
  { 2426,	5,	1,	328,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2426 = t2LDRHi8
  { 2427,	4,	1,	328,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2427 = t2LDRHpci
  { 2428,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2428 = t2LDRHpcrel
  { 2429,	6,	1,	325,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2429 = t2LDRHs
  { 2430,	5,	1,	347,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2430 = t2LDRSBT
  { 2431,	6,	2,	348,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2431 = t2LDRSB_POST
  { 2432,	6,	2,	348,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2432 = t2LDRSB_PRE
  { 2433,	5,	1,	336,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2433 = t2LDRSBi12
  { 2434,	5,	1,	336,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2434 = t2LDRSBi8
  { 2435,	4,	1,	336,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2435 = t2LDRSBpci
  { 2436,	4,	0,	337,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2436 = t2LDRSBpcrel
  { 2437,	6,	1,	338,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2437 = t2LDRSBs
  { 2438,	5,	1,	347,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2438 = t2LDRSHT
  { 2439,	6,	2,	348,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2439 = t2LDRSH_POST
  { 2440,	6,	2,	348,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2440 = t2LDRSH_PRE
  { 2441,	5,	1,	336,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2441 = t2LDRSHi12
  { 2442,	5,	1,	336,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2442 = t2LDRSHi8
  { 2443,	4,	1,	336,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2443 = t2LDRSHpci
  { 2444,	4,	0,	337,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo283,0,0 },  // Inst #2444 = t2LDRSHpcrel
  { 2445,	6,	1,	338,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2445 = t2LDRSHs
  { 2446,	5,	1,	346,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2446 = t2LDRT
  { 2447,	6,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2447 = t2LDR_POST
  { 2448,	6,	2,	344,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo60,0,0 },  // Inst #2448 = t2LDR_PRE
  { 2449,	5,	1,	329,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2449 = t2LDRi12
  { 2450,	5,	1,	329,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2450 = t2LDRi8
  { 2451,	4,	1,	329,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8eULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2451 = t2LDRpci
  { 2452,	3,	1,	330,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo295,0,0 },  // Inst #2452 = t2LDRpci_pic
  { 2453,	4,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo22,0,0 },  // Inst #2453 = t2LDRpcrel
  { 2454,	6,	1,	331,	4,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8dULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2454 = t2LDRs
  { 2455,	4,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo296,0,0 },  // Inst #2455 = t2LEApcrel
  { 2456,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo297,0,0 },  // Inst #2456 = t2LEApcrelJT
  { 2457,	6,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2457 = t2LSLri
  { 2458,	6,	1,	47,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2458 = t2LSLrr
  { 2459,	6,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2459 = t2LSRri
  { 2460,	6,	1,	47,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2460 = t2LSRrr
  { 2461,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo71,0,0 },  // Inst #2461 = t2MCR
  { 2462,	8,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo71,0,0 },  // Inst #2462 = t2MCR2
  { 2463,	7,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo298,0,0 },  // Inst #2463 = t2MCRR
  { 2464,	7,	0,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo298,0,0 },  // Inst #2464 = t2MCRR2
  { 2465,	6,	1,	312,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2465 = t2MLA
  { 2466,	6,	1,	312,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2466 = t2MLS
  { 2467,	6,	1,	246,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2467 = t2MOVCCasr
  { 2468,	5,	1,	38,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2468 = t2MOVCCi
  { 2469,	5,	1,	38,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2469 = t2MOVCCi16
  { 2470,	5,	1,	291,	8,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo301,0,0 },  // Inst #2470 = t2MOVCCi32imm
  { 2471,	6,	1,	246,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2471 = t2MOVCClsl
  { 2472,	6,	1,	246,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2472 = t2MOVCClsr
  { 2473,	5,	1,	41,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Select)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0x0ULL, NULL, NULL, OperandInfo302,0,0 },  // Inst #2473 = t2MOVCCr
  { 2474,	6,	1,	246,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo300,0,0 },  // Inst #2474 = t2MOVCCror
  { 2475,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo303,0,0 },  // Inst #2475 = t2MOVSsi
  { 2476,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo304,0,0 },  // Inst #2476 = t2MOVSsr
  { 2477,	5,	1,	39,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2477 = t2MOVTi16
  { 2478,	4,	1,	39,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo305,0,0 },  // Inst #2478 = t2MOVTi16_ga_pcrel
  { 2479,	2,	1,	293,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo306,0,0 },  // Inst #2479 = t2MOV_ga_pcrel
  { 2480,	5,	1,	39,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, NULL, NULL, OperandInfo307,0,0 },  // Inst #2480 = t2MOVi
  { 2481,	4,	1,	39,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_CheapAsAMove), 0xc80ULL, NULL, NULL, OperandInfo278,0,0 },  // Inst #2481 = t2MOVi16
  { 2482,	3,	1,	294,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo295,0,0 },  // Inst #2482 = t2MOVi16_ga_pcrel
  { 2483,	2,	1,	292,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo306,0,0 },  // Inst #2483 = t2MOVi32imm
  { 2484,	5,	1,	46,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo308,0,0 },  // Inst #2484 = t2MOVr
  { 2485,	5,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo303,0,0 },  // Inst #2485 = t2MOVsi
  { 2486,	6,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo304,0,0 },  // Inst #2486 = t2MOVsr
  { 2487,	4,	1,	48,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo282,0,0 },  // Inst #2487 = t2MOVsra_flag
  { 2488,	4,	1,	48,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo282,0,0 },  // Inst #2488 = t2MOVsrl_flag
  { 2489,	8,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo91,0,0 },  // Inst #2489 = t2MRC
  { 2490,	8,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo91,0,0 },  // Inst #2490 = t2MRC2
  { 2491,	7,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo298,0,0 },  // Inst #2491 = t2MRRC
  { 2492,	7,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo298,0,0 },  // Inst #2492 = t2MRRC2
  { 2493,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2493 = t2MRS_AR
  { 2494,	4,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo278,0,0 },  // Inst #2494 = t2MRS_M
  { 2495,	3,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2495 = t2MRSsys_AR
  { 2496,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo309,0,0 },  // Inst #2496 = t2MSR_AR
  { 2497,	4,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo309,0,0 },  // Inst #2497 = t2MSR_M
  { 2498,	5,	1,	309,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2498 = t2MUL
  { 2499,	5,	1,	38,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MoveImm)|(1<<MCID_Predicable), 0x0ULL, NULL, NULL, OperandInfo279,0,0 },  // Inst #2499 = t2MVNCCi
  { 2500,	5,	1,	50,	4,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef)|(1<<MCID_CheapAsAMove), 0xc80ULL, NULL, NULL, OperandInfo307,0,0 },  // Inst #2500 = t2MVNi
  { 2501,	5,	1,	51,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo311,0,0 },  // Inst #2501 = t2MVNr
  { 2502,	6,	1,	248,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo312,0,0 },  // Inst #2502 = t2MVNs
  { 2503,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2503 = t2ORNri
  { 2504,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2504 = t2ORNrr
  { 2505,	7,	1,	57,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2505 = t2ORNrs
  { 2506,	6,	1,	6,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2506 = t2ORRri
  { 2507,	6,	1,	7,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2507 = t2ORRrr
  { 2508,	7,	1,	57,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2508 = t2ORRrs
  { 2509,	6,	1,	57,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2509 = t2PKHBT
  { 2510,	6,	1,	57,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2510 = t2PKHTB
  { 2511,	4,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2511 = t2PLDWi12
  { 2512,	4,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2512 = t2PLDWi8
  { 2513,	5,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2513 = t2PLDWs
  { 2514,	4,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2514 = t2PLDi12
  { 2515,	4,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2515 = t2PLDi8
  { 2516,	3,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2516 = t2PLDpci
  { 2517,	5,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2517 = t2PLDs
  { 2518,	4,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2518 = t2PLIi12
  { 2519,	4,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo314,0,0 },  // Inst #2519 = t2PLIi8
  { 2520,	3,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2520 = t2PLIpci
  { 2521,	5,	0,	58,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo315,0,0 },  // Inst #2521 = t2PLIs
  { 2522,	5,	1,	299,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2522 = t2QADD
  { 2523,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2523 = t2QADD16
  { 2524,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2524 = t2QADD8
  { 2525,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2525 = t2QASX
  { 2526,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2526 = t2QDADD
  { 2527,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2527 = t2QDSUB
  { 2528,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2528 = t2QSAX
  { 2529,	5,	1,	299,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2529 = t2QSUB
  { 2530,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2530 = t2QSUB16
  { 2531,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2531 = t2QSUB8
  { 2532,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo282,0,0 },  // Inst #2532 = t2RBIT
  { 2533,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo282,0,0 },  // Inst #2533 = t2REV
  { 2534,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo282,0,0 },  // Inst #2534 = t2REV16
  { 2535,	4,	1,	16,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo282,0,0 },  // Inst #2535 = t2REVSH
  { 2536,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2536 = t2RFEDB
  { 2537,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2537 = t2RFEDBW
  { 2538,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2538 = t2RFEIA
  { 2539,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2539 = t2RFEIAW
  { 2540,	6,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2540 = t2RORri
  { 2541,	6,	1,	47,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2541 = t2RORrr
  { 2542,	5,	1,	48,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, ImplicitList1, NULL, OperandInfo311,0,0 },  // Inst #2542 = t2RRX
  { 2543,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo316,0,0 },  // Inst #2543 = t2RSBSri
  { 2544,	6,	1,	56,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo317,0,0 },  // Inst #2544 = t2RSBSrs
  { 2545,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo268,0,0 },  // Inst #2545 = t2RSBri
  { 2546,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo269,0,0 },  // Inst #2546 = t2RSBrr
  { 2547,	7,	1,	249,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo270,0,0 },  // Inst #2547 = t2RSBrs
  { 2548,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2548 = t2SADD16
  { 2549,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2549 = t2SADD8
  { 2550,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2550 = t2SASX
  { 2551,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo268,0,0 },  // Inst #2551 = t2SBCri
  { 2552,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo269,0,0 },  // Inst #2552 = t2SBCrr
  { 2553,	7,	1,	56,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef)|(1<<MCID_HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo270,0,0 },  // Inst #2553 = t2SBCrs
  { 2554,	6,	1,	296,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo318,0,0 },  // Inst #2554 = t2SBFX
  { 2555,	5,	1,	323,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2555 = t2SDIV
  { 2556,	5,	1,	295,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo16,0,0 },  // Inst #2556 = t2SEL
  { 2557,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2557 = t2SHADD16
  { 2558,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2558 = t2SHADD8
  { 2559,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2559 = t2SHASX
  { 2560,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2560 = t2SHSAX
  { 2561,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2561 = t2SHSUB16
  { 2562,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2562 = t2SHSUB8
  { 2563,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2563 = t2SMC
  { 2564,	6,	1,	316,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2564 = t2SMLABB
  { 2565,	6,	1,	316,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2565 = t2SMLABT
  { 2566,	6,	1,	319,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2566 = t2SMLAD
  { 2567,	6,	1,	319,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2567 = t2SMLADX
  { 2568,	8,	2,	322,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo319,0,0 },  // Inst #2568 = t2SMLAL
  { 2569,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2569 = t2SMLALBB
  { 2570,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2570 = t2SMLALBT
  { 2571,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2571 = t2SMLALD
  { 2572,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2572 = t2SMLALDX
  { 2573,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2573 = t2SMLALTB
  { 2574,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2574 = t2SMLALTT
  { 2575,	6,	1,	316,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2575 = t2SMLATB
  { 2576,	6,	1,	316,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2576 = t2SMLATT
  { 2577,	6,	1,	316,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2577 = t2SMLAWB
  { 2578,	6,	1,	316,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2578 = t2SMLAWT
  { 2579,	6,	1,	317,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2579 = t2SMLSD
  { 2580,	6,	1,	317,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2580 = t2SMLSDX
  { 2581,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2581 = t2SMLSLD
  { 2582,	6,	2,	322,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2582 = t2SMLSLDX
  { 2583,	6,	1,	312,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2583 = t2SMMLA
  { 2584,	6,	1,	312,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2584 = t2SMMLAR
  { 2585,	6,	1,	312,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2585 = t2SMMLS
  { 2586,	6,	1,	312,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2586 = t2SMMLSR
  { 2587,	5,	1,	309,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2587 = t2SMMUL
  { 2588,	5,	1,	309,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2588 = t2SMMULR
  { 2589,	5,	1,	314,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2589 = t2SMUAD
  { 2590,	5,	1,	314,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2590 = t2SMUADX
  { 2591,	5,	1,	310,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2591 = t2SMULBB
  { 2592,	5,	1,	310,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2592 = t2SMULBT
  { 2593,	6,	2,	321,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2593 = t2SMULL
  { 2594,	5,	1,	310,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2594 = t2SMULTB
  { 2595,	5,	1,	310,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2595 = t2SMULTT
  { 2596,	5,	1,	310,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2596 = t2SMULWB
  { 2597,	5,	1,	310,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2597 = t2SMULWT
  { 2598,	5,	1,	311,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2598 = t2SMUSD
  { 2599,	5,	1,	311,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2599 = t2SMUSDX
  { 2600,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2600 = t2SRSDB
  { 2601,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2601 = t2SRSDB_UPD
  { 2602,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2602 = t2SRSIA
  { 2603,	3,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2603 = t2SRSIA_UPD
  { 2604,	6,	1,	299,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo320,0,0 },  // Inst #2604 = t2SSAT
  { 2605,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo321,0,0 },  // Inst #2605 = t2SSAT16
  { 2606,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2606 = t2SSAX
  { 2607,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2607 = t2SSUB16
  { 2608,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2608 = t2SSUB8
  { 2609,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2609 = t2STC2L_OFFSET
  { 2610,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2610 = t2STC2L_OPTION
  { 2611,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2611 = t2STC2L_POST
  { 2612,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2612 = t2STC2L_PRE
  { 2613,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2613 = t2STC2_OFFSET
  { 2614,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2614 = t2STC2_OPTION
  { 2615,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2615 = t2STC2_POST
  { 2616,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2616 = t2STC2_PRE
  { 2617,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2617 = t2STCL_OFFSET
  { 2618,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2618 = t2STCL_OPTION
  { 2619,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2619 = t2STCL_POST
  { 2620,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2620 = t2STCL_PRE
  { 2621,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2621 = t2STC_OFFSET
  { 2622,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2622 = t2STC_OPTION
  { 2623,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2623 = t2STC_POST
  { 2624,	6,	0,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo58,0,0 },  // Inst #2624 = t2STC_PRE
  { 2625,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2625 = t2STL
  { 2626,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2626 = t2STLB
  { 2627,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo322,0,0 },  // Inst #2627 = t2STLEX
  { 2628,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo322,0,0 },  // Inst #2628 = t2STLEXB
  { 2629,	6,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo323,0,0 },  // Inst #2629 = t2STLEXD
  { 2630,	5,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo322,0,0 },  // Inst #2630 = t2STLEXH
  { 2631,	4,	0,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo288,0,0 },  // Inst #2631 = t2STLH
  { 2632,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2632 = t2STMDB
  { 2633,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2633 = t2STMDB_UPD
  { 2634,	4,	0,	372,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo54,0,0 },  // Inst #2634 = t2STMIA
  { 2635,	5,	1,	373,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2635 = t2STMIA_UPD
  { 2636,	5,	1,	368,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2636 = t2STRBT
  { 2637,	6,	1,	365,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo324,0,0 },  // Inst #2637 = t2STRB_POST
  { 2638,	6,	1,	365,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo324,0,0 },  // Inst #2638 = t2STRB_PRE
  { 2639,	6,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo325,0,0 },  // Inst #2639 = t2STRB_preidx
  { 2640,	5,	0,	362,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2640 = t2STRBi12
  { 2641,	5,	0,	362,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2641 = t2STRBi8
  { 2642,	6,	0,	359,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo326,0,0 },  // Inst #2642 = t2STRBs
  { 2643,	7,	1,	371,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo327,0,0 },  // Inst #2643 = t2STRD_POST
  { 2644,	7,	1,	371,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8fULL, NULL, NULL, OperandInfo327,0,0 },  // Inst #2644 = t2STRD_PRE
  { 2645,	6,	0,	370,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_ExtraSrcRegAllocReq), 0xc8fULL, NULL, NULL, OperandInfo17,0,0 },  // Inst #2645 = t2STRDi8
  { 2646,	6,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo328,0,0 },  // Inst #2646 = t2STREX
  { 2647,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo322,0,0 },  // Inst #2647 = t2STREXB
  { 2648,	6,	1,	0,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo323,0,0 },  // Inst #2648 = t2STREXD
  { 2649,	5,	1,	0,	4,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo322,0,0 },  // Inst #2649 = t2STREXH
  { 2650,	5,	1,	368,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2650 = t2STRHT
  { 2651,	6,	1,	365,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo324,0,0 },  // Inst #2651 = t2STRH_POST
  { 2652,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo324,0,0 },  // Inst #2652 = t2STRH_PRE
  { 2653,	6,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo325,0,0 },  // Inst #2653 = t2STRH_preidx
  { 2654,	5,	0,	362,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2654 = t2STRHi12
  { 2655,	5,	0,	362,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2655 = t2STRHi8
  { 2656,	6,	0,	359,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo326,0,0 },  // Inst #2656 = t2STRHs
  { 2657,	5,	1,	369,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc8cULL, NULL, NULL, OperandInfo290,0,0 },  // Inst #2657 = t2STRT
  { 2658,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcccULL, NULL, NULL, OperandInfo329,0,0 },  // Inst #2658 = t2STR_POST
  { 2659,	6,	1,	367,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xcacULL, NULL, NULL, OperandInfo329,0,0 },  // Inst #2659 = t2STR_PRE
  { 2660,	6,	1,	366,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo325,0,0 },  // Inst #2660 = t2STR_preidx
  { 2661,	5,	0,	363,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8bULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2661 = t2STRi12
  { 2662,	5,	0,	363,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8cULL, NULL, NULL, OperandInfo46,0,0 },  // Inst #2662 = t2STRi8
  { 2663,	6,	0,	361,	4,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8dULL, NULL, NULL, OperandInfo291,0,0 },  // Inst #2663 = t2STRs
  { 2664,	3,	0,	0,	4,	0|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, NULL, ImplicitList12, OperandInfo50,0,0 },  // Inst #2664 = t2SUBS_PC_LR
  { 2665,	5,	1,	1,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo271,0,0 },  // Inst #2665 = t2SUBSri
  { 2666,	5,	1,	2,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo272,0,0 },  // Inst #2666 = t2SUBSrr
  { 2667,	6,	1,	235,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_HasPostISelHook), 0x0ULL, NULL, ImplicitList1, OperandInfo273,0,0 },  // Inst #2667 = t2SUBSrs
  { 2668,	6,	1,	1,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Rematerializable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo274,0,0 },  // Inst #2668 = t2SUBri
  { 2669,	5,	1,	1,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo275,0,0 },  // Inst #2669 = t2SUBri12
  { 2670,	6,	1,	2,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo276,0,0 },  // Inst #2670 = t2SUBrr
  { 2671,	7,	1,	56,	4,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0xc80ULL, NULL, NULL, OperandInfo277,0,0 },  // Inst #2671 = t2SUBrs
  { 2672,	6,	1,	305,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2672 = t2SXTAB
  { 2673,	6,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2673 = t2SXTAB16
  { 2674,	6,	1,	305,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2674 = t2SXTAH
  { 2675,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2675 = t2SXTB
  { 2676,	5,	1,	290,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2676 = t2SXTB16
  { 2677,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2677 = t2SXTH
  { 2678,	4,	0,	14,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo330,0,0 },  // Inst #2678 = t2TBB
  { 2679,	3,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo41,0,0 },  // Inst #2679 = t2TBB_JT
  { 2680,	4,	0,	14,	4,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo330,0,0 },  // Inst #2680 = t2TBH
  { 2681,	3,	0,	10,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_NotDuplicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo41,0,0 },  // Inst #2681 = t2TBH_JT
  { 2682,	4,	0,	254,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo283,0,0 },  // Inst #2682 = t2TEQri
  { 2683,	4,	0,	255,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2683 = t2TEQrr
  { 2684,	5,	0,	256,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2684 = t2TEQrs
  { 2685,	4,	0,	254,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo283,0,0 },  // Inst #2685 = t2TSTri
  { 2686,	4,	0,	255,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo284,0,0 },  // Inst #2686 = t2TSTrr
  { 2687,	5,	0,	256,	4,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo285,0,0 },  // Inst #2687 = t2TSTrs
  { 2688,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2688 = t2UADD16
  { 2689,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2689 = t2UADD8
  { 2690,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2690 = t2UASX
  { 2691,	6,	1,	296,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo318,0,0 },  // Inst #2691 = t2UBFX
  { 2692,	5,	1,	323,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2692 = t2UDIV
  { 2693,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2693 = t2UHADD16
  { 2694,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2694 = t2UHADD8
  { 2695,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2695 = t2UHASX
  { 2696,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2696 = t2UHSAX
  { 2697,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2697 = t2UHSUB16
  { 2698,	5,	1,	304,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2698 = t2UHSUB8
  { 2699,	6,	2,	322,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2699 = t2UMAAL
  { 2700,	8,	2,	322,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo319,0,0 },  // Inst #2700 = t2UMLAL
  { 2701,	6,	2,	321,	4,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2701 = t2UMULL
  { 2702,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2702 = t2UQADD16
  { 2703,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2703 = t2UQADD8
  { 2704,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2704 = t2UQASX
  { 2705,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2705 = t2UQSAX
  { 2706,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2706 = t2UQSUB16
  { 2707,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2707 = t2UQSUB8
  { 2708,	5,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2708 = t2USAD8
  { 2709,	6,	1,	0,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo299,0,0 },  // Inst #2709 = t2USADA8
  { 2710,	6,	1,	299,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo320,0,0 },  // Inst #2710 = t2USAT
  { 2711,	5,	1,	299,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo321,0,0 },  // Inst #2711 = t2USAT16
  { 2712,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2712 = t2USAX
  { 2713,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2713 = t2USUB16
  { 2714,	5,	1,	301,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo310,0,0 },  // Inst #2714 = t2USUB8
  { 2715,	6,	1,	305,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2715 = t2UXTAB
  { 2716,	6,	1,	305,	4,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2716 = t2UXTAB16
  { 2717,	6,	1,	305,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo313,0,0 },  // Inst #2717 = t2UXTAH
  { 2718,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2718 = t2UXTB
  { 2719,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2719 = t2UXTB16
  { 2720,	5,	1,	290,	4,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo316,0,0 },  // Inst #2720 = t2UXTH
  { 2721,	6,	2,	257,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, NULL, OperandInfo331,0,0 },  // Inst #2721 = tADC
  { 2722,	5,	1,	257,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo79,0,0 },  // Inst #2722 = tADDhirr
  { 2723,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2723 = tADDi3
  { 2724,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo333,0,0 },  // Inst #2724 = tADDi8
  { 2725,	5,	1,	257,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo334,0,0 },  // Inst #2725 = tADDrSP
  { 2726,	5,	1,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo335,0,0 },  // Inst #2726 = tADDrSPi
  { 2727,	6,	2,	257,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo336,0,0 },  // Inst #2727 = tADDrr
  { 2728,	5,	1,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo337,0,0 },  // Inst #2728 = tADDspi
  { 2729,	5,	1,	257,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo338,0,0 },  // Inst #2729 = tADDspr
  { 2730,	1,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo2,0,0 },  // Inst #2730 = tADJCALLSTACKDOWN
  { 2731,	2,	0,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, ImplicitList2, OperandInfo8,0,0 },  // Inst #2731 = tADJCALLSTACKUP
  { 2732,	4,	1,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo339,0,0 },  // Inst #2732 = tADR
  { 2733,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2733 = tAND
  { 2734,	6,	2,	48,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2734 = tASRri
  { 2735,	6,	2,	47,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2735 = tASRrr
  { 2736,	3,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2736 = tB
  { 2737,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2737 = tBIC
  { 2738,	1,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #2738 = tBKPT
  { 2739,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo340,0,0 },  // Inst #2739 = tBL
  { 2740,	3,	0,	12,	4,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo340,0,0 },  // Inst #2740 = tBLXi
  { 2741,	3,	0,	12,	2,	0|(1<<MCID_Call)|(1<<MCID_Predicable), 0xc80ULL, ImplicitList2, ImplicitList3, OperandInfo341,0,0 },  // Inst #2741 = tBLXr
  { 2742,	3,	0,	10,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2742 = tBRIND
  { 2743,	3,	0,	14,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo342,0,0 },  // Inst #2743 = tBR_JTr
  { 2744,	3,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_IndirectBranch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo36,0,0 },  // Inst #2744 = tBX
  { 2745,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList3, OperandInfo38,0,0 },  // Inst #2745 = tBX_CALL
  { 2746,	2,	0,	10,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator), 0x0ULL, NULL, NULL, OperandInfo42,0,0 },  // Inst #2746 = tBX_RET
  { 2747,	3,	0,	10,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo343,0,0 },  // Inst #2747 = tBX_RET_vararg
  { 2748,	3,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo37,0,0 },  // Inst #2748 = tBcc
  { 2749,	3,	0,	14,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Branch)|(1<<MCID_Barrier)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList3, OperandInfo37,0,0 },  // Inst #2749 = tBfar
  { 2750,	2,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo344,0,0 },  // Inst #2750 = tCBNZ
  { 2751,	2,	0,	10,	2,	0|(1<<MCID_Branch)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo344,0,0 },  // Inst #2751 = tCBZ
  { 2752,	4,	0,	239,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo345,0,0 },  // Inst #2752 = tCMNz
  { 2753,	4,	0,	239,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList1, OperandInfo45,0,0 },  // Inst #2753 = tCMPhir
  { 2754,	4,	0,	238,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo346,0,0 },  // Inst #2754 = tCMPi8
  { 2755,	4,	0,	239,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable), 0xc80ULL, NULL, ImplicitList1, OperandInfo345,0,0 },  // Inst #2755 = tCMPr
  { 2756,	2,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo7,0,0 },  // Inst #2756 = tCPS
  { 2757,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2757 = tEOR
  { 2758,	3,	0,	0,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo50,0,0 },  // Inst #2758 = tHINT
  { 2759,	1,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,0,0 },  // Inst #2759 = tHLT
  { 2760,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, ImplicitList5, OperandInfo10,0,0 },  // Inst #2760 = tInt_eh_sjlj_longjmp
  { 2761,	2,	0,	0,	0,	0|(1<<MCID_Barrier)|(1<<MCID_UsesCustomInserter)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, ImplicitList13, OperandInfo287,0,0 },  // Inst #2761 = tInt_eh_sjlj_setjmp
  { 2762,	4,	0,	352,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo347,0,0 },  // Inst #2762 = tLDMIA
  { 2763,	5,	1,	353,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Variadic), 0x0ULL, NULL, NULL, OperandInfo53,0,0 },  // Inst #2763 = tLDMIA_UPD
  { 2764,	5,	1,	328,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, NULL, NULL, OperandInfo348,0,0 },  // Inst #2764 = tLDRBi
  { 2765,	5,	1,	332,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc87ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2765 = tLDRBr
  { 2766,	5,	1,	328,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, NULL, NULL, OperandInfo348,0,0 },  // Inst #2766 = tLDRHi
  { 2767,	5,	1,	332,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc88ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2767 = tLDRHr
  { 2768,	5,	1,	339,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc87ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2768 = tLDRSB
  { 2769,	5,	1,	339,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc88ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2769 = tLDRSH
  { 2770,	5,	1,	329,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, NULL, NULL, OperandInfo348,0,0 },  // Inst #2770 = tLDRi
  { 2771,	4,	1,	329,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc8aULL, NULL, NULL, OperandInfo339,0,0 },  // Inst #2771 = tLDRpci
  { 2772,	3,	1,	326,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_MayLoad)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo86,0,0 },  // Inst #2772 = tLDRpci_pic
  { 2773,	5,	1,	333,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0xc89ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2773 = tLDRr
  { 2774,	5,	1,	329,	2,	0|(1<<MCID_FoldableAsLoad)|(1<<MCID_MayLoad)|(1<<MCID_Predicable), 0xc8aULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2774 = tLDRspi
  { 2775,	4,	1,	258,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_Rematerializable), 0x0ULL, NULL, NULL, OperandInfo351,0,0 },  // Inst #2775 = tLEApcrel
  { 2776,	5,	1,	258,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, NULL, NULL, OperandInfo352,0,0 },  // Inst #2776 = tLEApcrelJT
  { 2777,	6,	2,	48,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2777 = tLSLri
  { 2778,	6,	2,	47,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2778 = tLSLrr
  { 2779,	6,	2,	48,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2779 = tLSRri
  { 2780,	6,	2,	47,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2780 = tLSRrr
  { 2781,	5,	1,	0,	0,	0|(1<<MCID_Pseudo)|(1<<MCID_Predicable)|(1<<MCID_UsesCustomInserter), 0x0ULL, NULL, NULL, OperandInfo353,0,0 },  // Inst #2781 = tMOVCCr_pseudo
  { 2782,	2,	1,	46,	2,	0, 0xc80ULL, NULL, ImplicitList1, OperandInfo287,0,0 },  // Inst #2782 = tMOVSr
  { 2783,	5,	2,	39,	2,	0|(1<<MCID_MoveImm)|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo354,0,0 },  // Inst #2783 = tMOVi8
  { 2784,	4,	1,	46,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo45,0,0 },  // Inst #2784 = tMOVr
  { 2785,	6,	2,	49,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo355,0,0 },  // Inst #2785 = tMUL
  { 2786,	5,	2,	51,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo356,0,0 },  // Inst #2786 = tMVN
  { 2787,	6,	2,	259,	2,	0|(1<<MCID_Predicable)|(1<<MCID_Commutable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2787 = tORR
  { 2788,	3,	1,	257,	2,	0|(1<<MCID_NotDuplicable), 0xc80ULL, NULL, NULL, OperandInfo357,0,0 },  // Inst #2788 = tPICADD
  { 2789,	3,	0,	355,	2,	0|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo358,0,0 },  // Inst #2789 = tPOP
  { 2790,	3,	0,	356,	2,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_MayLoad)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraDefRegAllocReq), 0x0ULL, NULL, NULL, OperandInfo358,0,0 },  // Inst #2790 = tPOP_RET
  { 2791,	3,	0,	374,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_UnmodeledSideEffects)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, ImplicitList2, ImplicitList2, OperandInfo358,0,0 },  // Inst #2791 = tPUSH
  { 2792,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2792 = tREV
  { 2793,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2793 = tREV16
  { 2794,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2794 = tREVSH
  { 2795,	6,	2,	47,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo331,0,0 },  // Inst #2795 = tROR
  { 2796,	5,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo356,0,0 },  // Inst #2796 = tRSB
  { 2797,	6,	2,	257,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, ImplicitList1, NULL, OperandInfo331,0,0 },  // Inst #2797 = tSBC
  { 2798,	1,	0,	0,	2,	0|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo5,ARM_HasV8Ops,0 },  // Inst #2798 = tSETEND
  { 2799,	5,	1,	373,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable)|(1<<MCID_Variadic)|(1<<MCID_ExtraSrcRegAllocReq), 0xc80ULL, NULL, NULL, OperandInfo359,0,0 },  // Inst #2799 = tSTMIA_UPD
  { 2800,	5,	0,	362,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, NULL, NULL, OperandInfo348,0,0 },  // Inst #2800 = tSTRBi
  { 2801,	5,	0,	358,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc87ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2801 = tSTRBr
  { 2802,	5,	0,	362,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, NULL, NULL, OperandInfo348,0,0 },  // Inst #2802 = tSTRHi
  { 2803,	5,	0,	358,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc88ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2803 = tSTRHr
  { 2804,	5,	0,	363,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, NULL, NULL, OperandInfo348,0,0 },  // Inst #2804 = tSTRi
  { 2805,	5,	0,	357,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc89ULL, NULL, NULL, OperandInfo349,0,0 },  // Inst #2805 = tSTRr
  { 2806,	5,	0,	363,	2,	0|(1<<MCID_MayStore)|(1<<MCID_Predicable), 0xc8aULL, NULL, NULL, OperandInfo350,0,0 },  // Inst #2806 = tSTRspi
  { 2807,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo332,0,0 },  // Inst #2807 = tSUBi3
  { 2808,	6,	2,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo333,0,0 },  // Inst #2808 = tSUBi8
  { 2809,	6,	2,	257,	2,	0|(1<<MCID_Predicable)|(1<<MCID_HasOptionalDef), 0x40c80ULL, NULL, NULL, OperandInfo336,0,0 },  // Inst #2809 = tSUBrr
  { 2810,	5,	1,	258,	2,	0|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, OperandInfo337,0,0 },  // Inst #2810 = tSUBspi
  { 2811,	3,	0,	10,	2,	0|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, ImplicitList2, NULL, OperandInfo50,0,0 },  // Inst #2811 = tSVC
  { 2812,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2812 = tSXTB
  { 2813,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2813 = tSXTH
  { 2814,	3,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo37,0,0 },  // Inst #2814 = tTAILJMPd
  { 2815,	3,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Predicable)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo37,0,0 },  // Inst #2815 = tTAILJMPdND
  { 2816,	1,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Return)|(1<<MCID_Barrier)|(1<<MCID_Call)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0x0ULL, ImplicitList2, NULL, OperandInfo121,0,0 },  // Inst #2816 = tTAILJMPr
  { 2817,	0,	0,	10,	4,	0|(1<<MCID_Pseudo)|(1<<MCID_Call), 0x0ULL, ImplicitList2, ImplicitList8, 0,0,0 },  // Inst #2817 = tTPsoft
  { 2818,	0,	0,	10,	2,	0|(1<<MCID_Barrier)|(1<<MCID_Terminator)|(1<<MCID_UnmodeledSideEffects), 0xc80ULL, NULL, NULL, 0,0,0 },  // Inst #2818 = tTRAP
  { 2819,	4,	0,	262,	2,	0|(1<<MCID_Compare)|(1<<MCID_Predicable)|(1<<MCID_Commutable), 0xc80ULL, NULL, ImplicitList1, OperandInfo345,0,0 },  // Inst #2819 = tTST
  { 2820,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2820 = tUXTB
  { 2821,	4,	1,	16,	2,	0|(1<<MCID_Predicable), 0xc80ULL, NULL, NULL, OperandInfo345,0,0 },  // Inst #2821 = tUXTH
};

#endif // GET_INSTRINFO_MC_DESC
