2017-05-16 19:15:02 +08:00
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#!/usr/bin/python
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# Test tool to disassemble MC files. By Nguyen Anh Quynh, 2017
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import array, os.path, sys
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from capstone import *
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# convert all hex numbers to decimal numbers in a text
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def normalize_hex(a):
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while(True):
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i = a.find('0x')
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if i == -1: # no more hex number
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break
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hexnum = '0x'
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for c in a[i + 2:]:
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if c in '0123456789abcdefABCDEF':
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hexnum += c
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else:
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break
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num = int(hexnum, 16)
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a = a.replace(hexnum, str(num))
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return a
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def test_file(fname):
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print("Test %s" %fname);
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f = open(fname)
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lines = f.readlines()
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f.close()
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if not lines[0].startswith('# '):
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print("ERROR: decoding information is missing")
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return
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# skip '# ' at the front, then split line to get out hexcode
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# Note: option can be '', or 'None'
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#print lines[0]
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#print lines[0][2:].split(', ')
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(arch, mode, option) = lines[0][2:].split(', ')
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mode = mode.replace(' ', '')
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option = option.strip()
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archs = {
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"CS_ARCH_ARM": CS_ARCH_ARM,
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"CS_ARCH_ARM64": CS_ARCH_ARM64,
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"CS_ARCH_MIPS": CS_ARCH_MIPS,
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"CS_ARCH_PPC": CS_ARCH_PPC,
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"CS_ARCH_SPARC": CS_ARCH_SPARC,
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"CS_ARCH_SYSZ": CS_ARCH_SYSZ,
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"CS_ARCH_X86": CS_ARCH_X86,
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"CS_ARCH_XCORE": CS_ARCH_XCORE,
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"CS_ARCH_M68K": CS_ARCH_M68K,
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RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 08:41:12 +08:00
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"CS_ARCH_RISCV": CS_ARCH_RISCV,
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2017-05-16 19:15:02 +08:00
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}
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modes = {
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"CS_MODE_16": CS_MODE_16,
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"CS_MODE_32": CS_MODE_32,
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"CS_MODE_64": CS_MODE_64,
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"CS_MODE_MIPS32": CS_MODE_MIPS32,
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"CS_MODE_MIPS64": CS_MODE_MIPS64,
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"0": CS_MODE_ARM,
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"CS_MODE_ARM": CS_MODE_ARM,
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"CS_MODE_THUMB": CS_MODE_THUMB,
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"CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8,
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"CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8,
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"CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS,
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"CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
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"CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN,
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"CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO,
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"CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
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"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
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"CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9,
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"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN,
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"CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN,
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"CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN,
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RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 08:41:12 +08:00
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"CS_MODE_RISCV32": CS_MODE_RISCV32,
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"CS_MODE_RISCV64": CS_MODE_RISCV64,
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2017-05-16 19:15:02 +08:00
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}
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options = {
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"CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT,
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"CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME,
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}
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mc_modes = {
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("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'],
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("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'],
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("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'],
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("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'],
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("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'],
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("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'],
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("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'],
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("CS_ARCH_ARM64", "0"): ['-triple=aarch64'],
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'],
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'],
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("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'],
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("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'],
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("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'],
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'],
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("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'],
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("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'],
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('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'],
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('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'],
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('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'],
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RISCV support ISRV32/ISRV64 (#1401)
* Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h
* Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction
* Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h
* Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter
* Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h
* Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b
* All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly.
* Add refactored cs.c for RISCV
* Testing all I instructions in test_riscv.c
* Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture
* Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c
* fixed bug related to incorrect initialization of memory after malloc
* fix compile bug
* Fix compile errors.
* move riscv.h to include/capstone
* fix indentation issues
* fix coding style issues
* Fix indentation issues
* fix coding style
* Move variable declaration to the top of the block
* Fix coding indentation
* Move some stuff into RISCVMappingInsn.inc
* Fix code sytle
* remove cs_mode support for RISCV
* update asmwriter-inc to LLVM upstream
* update the .inc files to riscv upstream
* update riscv disassembler function for suport 16bit instructions
* update printer & tablegen inc files which have fixed arguments mismatch
* update headers and mapping source
* add riscv architecture specific test code
* fix all RISCV tons of compiler errors
* pass final tests
* add riscv tablegen patchs
* merge with upstream/next
* fix cstool missing riscv file
* fix root Makefile
* add new TableGen patchs for riscv
* fix cmakefile.txt of missing one riscv file
* fix declaration conflict
* fix incompatible declaration type
* change riscvc from arch to mode
* fix test_riscv warnning
* fix code style and add riscv part of test_basic
* add RISCV64 mode
* add suite for riscv
* crack fuzz test
* fix getfeaturebits test add riscvc
* fix test missing const qualifier warnning
* fix testcase type mismatch
* fix return value missing
* change getfeaturebits test
* add test cs files
* using a winder type contain the decode string
* fix a copy typo
* remove useless mode for riscv
* change cs file blank type
* add repo for update_riscv & fix cstool missing riscv mode
* fix typo
* add riscv for cstool useage
* add TableGen patch for riscv asmwriter
* clean ctags file
* remove black comment line
* fix fuzz related something
* fix missing RISCV string of fuzz
* update readme, etc..
* add riscv *.s.cs file
* add riscv *.s.cs file & clear ctags
* clear useless array declarations at capstone_test
* update to 5e4069f
* update readme change name more formal
* change position of riscv after bpf and modify copyright more uniform
* clear useless ctags file
* change blank with tab in riscv.h
* add riscv python bindings
* add riscv in __init__.py
* fix riscv define value for python binding
* fix test_riscv.py typo
* add missing riscvc in __init__.py of python bindings
* fix alias-insn printer bug, remove useless newline
* change inst print delimter from tab to bankspace for travis
* add riscv tablegen patch
* fix inst output more consistency
* add TableGen patch which fix inst output formal
* crack the effective address output for detail and change register print function
* fix not detail crash bug
* change item declaration position at cs_riscv
* update riscv.py
* change function name more meaningfull
* update python binding makefile
* fix register enum sequence according to riscvgenreginfo.inc
* test function name
* add enum s0/fp in riscv.h & update riscv_const.py
* add register name enum
2019-03-09 08:41:12 +08:00
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('CS_ARCH_RISCV', 'CS_MODE_RISCV32'): ['-triple=riscv32'],
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('CS_ARCH_RISCV', 'CS_MODE_RISCV64'): ['-triple=riscv64'],
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2017-05-16 19:15:02 +08:00
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}
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#if not option in ('', 'None'):
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# print archs[arch], modes[mode], options[option]
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#print(arch, mode, option)
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md = Cs(archs[arch], modes[mode])
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if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' :
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md.syntax = CS_OPT_SYNTAX_NOREGNAME
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if fname.endswith('3DNow.s.cs'):
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md.syntax = CS_OPT_SYNTAX_ATT
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for line in lines[1:]:
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# ignore all the input lines having # in front.
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if line.startswith('#'):
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continue
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#print("Check %s" %line)
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code = line.split(' = ')[0]
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asm = ''.join(line.split(' = ')[1:])
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hex_code = code.replace('0x', '')
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hex_code = hex_code.replace(',', '')
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hex_data = hex_code.decode('hex')
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#hex_bytes = array.array('B', hex_data)
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x = list(md.disasm(hex_data, 0))
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if len(x) > 0:
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if x[0].op_str != '':
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cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str)
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else:
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cs_output = x[0].mnemonic
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else:
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cs_output = 'FAILED to disassemble'
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cs_output2 = normalize_hex(cs_output)
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cs_output2 = cs_output2.replace(' ', '')
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if arch == 'CS_ARCH_MIPS':
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# normalize register alias names
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cs_output2 = cs_output2.replace('$at', '$1')
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cs_output2 = cs_output2.replace('$v0', '$2')
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cs_output2 = cs_output2.replace('$v1', '$3')
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cs_output2 = cs_output2.replace('$a0', '$4')
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cs_output2 = cs_output2.replace('$a1', '$5')
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cs_output2 = cs_output2.replace('$a2', '$6')
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cs_output2 = cs_output2.replace('$a3', '$7')
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cs_output2 = cs_output2.replace('$t0', '$8')
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cs_output2 = cs_output2.replace('$t1', '$9')
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cs_output2 = cs_output2.replace('$t2', '$10')
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cs_output2 = cs_output2.replace('$t3', '$11')
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cs_output2 = cs_output2.replace('$t4', '$12')
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cs_output2 = cs_output2.replace('$t5', '$13')
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cs_output2 = cs_output2.replace('$t6', '$14')
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cs_output2 = cs_output2.replace('$t7', '$15')
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cs_output2 = cs_output2.replace('$t8', '$24')
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cs_output2 = cs_output2.replace('$t9', '$25')
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cs_output2 = cs_output2.replace('$s0', '$16')
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cs_output2 = cs_output2.replace('$s1', '$17')
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cs_output2 = cs_output2.replace('$s2', '$18')
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cs_output2 = cs_output2.replace('$s3', '$19')
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cs_output2 = cs_output2.replace('$s4', '$20')
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cs_output2 = cs_output2.replace('$s5', '$21')
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cs_output2 = cs_output2.replace('$s6', '$22')
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cs_output2 = cs_output2.replace('$s7', '$23')
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cs_output2 = cs_output2.replace('$k0', '$26')
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cs_output2 = cs_output2.replace('$k1', '$27')
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print("\t%s = %s" %(hex_code, cs_output))
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if __name__ == '__main__':
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if len(sys.argv) == 1:
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fnames = sys.stdin.readlines()
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for fname in fnames:
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test_file(fname.strip())
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else:
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#print("Usage: ./test_mc.py <input-file.s.cs>")
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test_file(sys.argv[1])
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