capstone/suite/capstone_get_setup.c

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/*
Retrieve architectures compiled in Capstone.
By Nguyen Anh Quynh, 2019.
Compile this code with:
$ cc -o capstone_get_setup capstone_get_setup.c -lcapstone
On default Capstone build, this code prints out the below output:
$ capstone_get_setup
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x86=1 arm=1 arm64=1 mips=1 ppc=1 sparc=1 sysz=1 xcore=1 m68k=1 tms320c64x=1 m680x=1 evm=1 wasm=1 mos65xx=1 bpf=1
*/
#include <stdio.h>
#include <capstone/capstone.h>
int main()
{
if (cs_support(CS_ARCH_X86)) {
printf("x86=1 ");
}
if (cs_support(CS_ARCH_ARM)) {
printf("arm=1 ");
}
if (cs_support(CS_ARCH_ARM64)) {
printf("arm64=1 ");
}
if (cs_support(CS_ARCH_MIPS)) {
printf("mips=1 ");
}
if (cs_support(CS_ARCH_PPC)) {
printf("ppc=1 ");
}
if (cs_support(CS_ARCH_SPARC)) {
printf("sparc=1 ");
}
if (cs_support(CS_ARCH_SYSZ)) {
printf("sysz=1 ");
}
if (cs_support(CS_ARCH_XCORE)) {
printf("xcore=1 ");
}
if (cs_support(CS_ARCH_M68K)) {
printf("m68k=1 ");
}
if (cs_support(CS_ARCH_TMS320C64X)) {
printf("tms320c64x=1 ");
}
if (cs_support(CS_ARCH_M680X)) {
printf("m680x=1 ");
}
if (cs_support(CS_ARCH_EVM)) {
printf("evm=1 ");
}
if (cs_support(CS_ARCH_WASM)) {
printf("wasm=1 ");
}
if (cs_support(CS_ARCH_MOS65XX)) {
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printf("mos65xx=1 ");
}
if (cs_support(CS_ARCH_BPF)) {
printf("bpf=1 ");
}
RISCV support ISRV32/ISRV64 (#1401) * Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h * Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction * Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h * Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter * Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h * Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b * All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly. * Add refactored cs.c for RISCV * Testing all I instructions in test_riscv.c * Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture * Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c * fixed bug related to incorrect initialization of memory after malloc * fix compile bug * Fix compile errors. * move riscv.h to include/capstone * fix indentation issues * fix coding style issues * Fix indentation issues * fix coding style * Move variable declaration to the top of the block * Fix coding indentation * Move some stuff into RISCVMappingInsn.inc * Fix code sytle * remove cs_mode support for RISCV * update asmwriter-inc to LLVM upstream * update the .inc files to riscv upstream * update riscv disassembler function for suport 16bit instructions * update printer & tablegen inc files which have fixed arguments mismatch * update headers and mapping source * add riscv architecture specific test code * fix all RISCV tons of compiler errors * pass final tests * add riscv tablegen patchs * merge with upstream/next * fix cstool missing riscv file * fix root Makefile * add new TableGen patchs for riscv * fix cmakefile.txt of missing one riscv file * fix declaration conflict * fix incompatible declaration type * change riscvc from arch to mode * fix test_riscv warnning * fix code style and add riscv part of test_basic * add RISCV64 mode * add suite for riscv * crack fuzz test * fix getfeaturebits test add riscvc * fix test missing const qualifier warnning * fix testcase type mismatch * fix return value missing * change getfeaturebits test * add test cs files * using a winder type contain the decode string * fix a copy typo * remove useless mode for riscv * change cs file blank type * add repo for update_riscv & fix cstool missing riscv mode * fix typo * add riscv for cstool useage * add TableGen patch for riscv asmwriter * clean ctags file * remove black comment line * fix fuzz related something * fix missing RISCV string of fuzz * update readme, etc.. * add riscv *.s.cs file * add riscv *.s.cs file & clear ctags * clear useless array declarations at capstone_test * update to 5e4069f * update readme change name more formal * change position of riscv after bpf and modify copyright more uniform * clear useless ctags file * change blank with tab in riscv.h * add riscv python bindings * add riscv in __init__.py * fix riscv define value for python binding * fix test_riscv.py typo * add missing riscvc in __init__.py of python bindings * fix alias-insn printer bug, remove useless newline * change inst print delimter from tab to bankspace for travis * add riscv tablegen patch * fix inst output more consistency * add TableGen patch which fix inst output formal * crack the effective address output for detail and change register print function * fix not detail crash bug * change item declaration position at cs_riscv * update riscv.py * change function name more meaningfull * update python binding makefile * fix register enum sequence according to riscvgenreginfo.inc * test function name * add enum s0/fp in riscv.h & update riscv_const.py * add register name enum
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if (cs_support(CS_ARCH_RISCV)) {
printf("riscv=1 ");
}
if (cs_support(CS_SUPPORT_DIET)) {
printf("diet=1 ");
}
if (cs_support(CS_SUPPORT_X86_REDUCE)) {
printf("x86_reduce=1 ");
}
if (cs_support(CS_ARCH_TRICORE)) {
printf("tricore=1 ");
}
printf("\n");
return 0;
}