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capstone/suite/MC/AArch64/fullfp16-neon-neg.txt.cs

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Architecture updater (auto-sync) - Updating AArch64 (#2026) * Update sysop inc file * Fix missing braces warning * Handle new system operands * Fix build errors by renaming. * Fix segfault * Fix segfault * Add custom MCOperand valiadtors * Add AArch64 case for getFeatureBits * Fix infinite loop * Fix braces warning. * Implement loopuo by name for sys operands * Fix incorrect translation which remove else if statements. * Fix several segfaults * Rename GetRegFromClass patch * Fix segfaults and asserts * Fix segfault * Move MRI setting to Mapping * Remove unused code * Add add_op_X functinos for AArch64. * Add fill detail functins * Handle RegWithShiftExtend operands * Handle TypedVectorList operands. * Handle ComplexRoatation operands * Handle MemExtend operands * Handle ImmRangeScale operands * Handle ExactFPImm operands * Handle GPRSeqPairsClass operands * Handle Imm8OptLsl operands * Handle ImmScale operands * Handle LogicalImm operands * Handle Matrix operands * Handle SME Matrix tiles and vectors. * Handle normal operands. * Fix segfault. * Handle PostInc operands. * Reorder VecLayout enum to have no duplicate enum value. * Handle PredicateAsCounter operands * Handle ZPRasFPR operands * Handle VectorIndex operands * Handle UImm12Offset operands. * Move reg suffix to enum val to single function. * Handle SVERegOp operands * Handle SVELogicalImm operands * Handle SImm operand * Handle PrefetchOp operands * Handle Imm and ImmHex operands * Handle GPR64as32 and GPR64x8 operands * Add missing break * Handle FPImm operand * Handle ExtendedRegister opreand * Handle CondCode operands * Handle BTIHintOp operands * Handle BarrierOption operands * Handle BarrierXSOption * Add not implemeted case again * Handle ArithExtend operands * Handle AdrpLabel and AlignedLabel operands * Handle AMNoIndex operands * Handle AddSubImm operands * Handle MSRSystemRegisters and MRSSystemRegister operands * Handle PSBHntOp and RPRFMOperand operands * Remove unused variables * Handle InverseCondCode operands * Handle ImplicityTypedVectorList operands * Handle ShiftedRegister operands * Handle Shifter operands * Handle SIMDType10Operand operands * Handle SVCROp operands * Handle SVEPattern operands * Handle SVEVecLenSpecifier operands * Handle SysCROperands * Handle SysXzrPair operands * Handle PState operands * Handle VRegOperands * Primt SME oeprands. * Fix cs_operand.h include * Rename arm64 -> aarch64 in python bindings. * Add Python bindings for SH * Fix ARM Python bindings (#2127) * Restructure auto-sync update scripts. * Move Helper functions to Updater dir * Move requirements.txt * Add basic ASUpdater.py * Run black. * Add inc file generater to updater * Add option to select certain inc files fore generation. * Enable clean build and implement patcher for inc files. * Format config * Patch main header files after inc generation. * Implement clang-format function (unused yet, because it takes forever.) * Copy generated inc files to arch dir * Invert clean option (noramlly we need to clean the build dir.) * Clearify arg doc * Rename SystemRegister file for AArch64 * Centralize handling of path variables. * Check if SystemOperands had to be generated before renaming on of its files. * Replace class parameters by calling get_path * Remove updater config which only contained paths. * Add refactor option. * Remove more path handling in the Configurator. * Add translation step to updater. * Fix includes after CppTranslator was moved into the Updater * Remove updater config * Fix several issue in the Configurator * Fix file operations * Remove addition argument from translator. * Add Differ step to updater. * Add path variable for arch_config * Add diff step. * Fix typo * Introduce .clang-format path variable. * Remove duplicate functions * Add option to select update steps to execute. * Check in write functions for write flag. * Rename PatchMainHeader -> HeaderPatcher * Move .gitignore * Add README to vendor dir. * Add all system operands to cstool output * Update cstest with aarch64 changes * Remove wb flag of aarch64 detail struct * Set updates_flag after decoding * Set writeback after decoding. * Rename ARM64 -> AArch64 * Update printer and op mapping * Exit normally * Add AArch64 alias * Fix some tmeplate function calls * Fix flag check after rebase. * Fix build by commentig unnused code. * Add memory operand flag * Handle memory operands printed via generic printOperand function. * Handle UImm memory offsets * Introduce MEM_REG and MEM_IMM op types * Handle scaled memory immediates * Check for op_count before checking for mem op at -1 index. * Update memory operand flags. * Pass imm/reg memory ops in set_imm/reg to set_mem. * Add missing set_sme_operand call and fix assert. * Remove CS_OP_MEM flag before entering switch. * Preidcates are registers. * Add shift info always to the previous operand * Check for generic system regs * Handle NumLanes = 0 LaneKind = q case * Replace printImm call with normal print logic. Otherwise ops get added twice to detail. * Handle FP operands in printOperand. * Add access information to float operands. * Rewrite SME matrix handling. * Set correct SME layouts and allow for immediate range sme offsets. * Handle cases of unknown system alias by setting their raw values * Update cstool and header file with new SME offset handling * Handle SME Tile lists. * Fix build error in cstest * Update MC tests for AArch64 * Handle TLBI operands and fix printing bug. * Fix: Print signed value as signed. * Add more system alias to detail. * Remove duplicate hex prefix * Set correct values for the register info * Replace tabs with white spaces * Move string append logic to own function. * Set DecodeComplete = true before decoding (as originally in the LLVM code). * Change type of feature argument, since only LLVM features are passed, not CS groups. * Imitate lower_bound for the index table binary search. * Remove trailing comments from test files. * Print shift amount in decimal * Save detail of shift alias instructions. * Add extension details fot ext instruction alias * Print LSB and width in decimal * Fix LLVM bug. The feature check for V8_2a doesn't check if all features are enabled. * Fix lower_bounds check. For m == 0 we wrap around 0 of cause. * Fix feature check. Add check for FeatureAll since it includes XS * Operate on temporary MCInst when trying decoding. * Add lower_bound behavior to IndexTypeStr binsearch. * Fix MC tests which were incorrect because of missing FeatureAll check * Add Alias handling for AArch64 * Update system operands with SYSIMM types and add additional sysop category. * Add macros for meta programming (ARM64 <-> AArch64 selection). * Fix union/struct confusion and add raw_value member to uninions. * Allow to set Syntax and mode options for AArch64 * Fix build warning by using correct type * Print shift value in decimal * Add missing call to add_cs_detail. * Update name map files with normalized names. * Remove unused function * Add check if detail should be filled. * Fill detail for real instructions if only real detail is requested. * Add always the extension. * Make dir creation log message debug level * Implement ADR immediate operand printer. See: https://github.com/capstone-engine/llvm-capstone/commit/c3484b1fdc03b479beaf5897eca8ea294d3df909 * Check for flag registers beeing written and update flag. * Move multiple CondCode helpers to aarch64.h because they are so freaking useful. + Print CC if it is EQ * Fix incorrectly initialized CC and VectorLayout. * Add LSL shift type for extensions. * Fix case when shift amount is 0 * Fix post-index memory instructions. * Pass raw immediate through getShiftValue to extract actual shift amount * Setup AArch64 detail ops. * Add flag for operands part of a list. * Set vector indices for all relevant registers. * Add missing call to add_cs_detail for postIncOperands * Add ugly yet reliable way to determine post-index addressing mode * Add support for old Capstone register alias. * Remove leading space before some alias mnemonics. * add AARCH64 to `cmake.sh` * add HAS_AARCH64 to `cs.c` * should probably just reference `cs_operand.h` in `aarch64.h` * hint compiler at `AArch64_SYSREG` enum type for casting purposes * update `Makefile` for AARCH64 leaves `CAPSTONE_HAS_ARM64` supported * `testFeatureBits` platform function check `testFeatureBits` should check if the platform function is visible first * update tests to use AARCH64 convention * hack: avoid enum casts for `MCInst` Values Apple compiler really hates typecasting a enum, even if bounded from a unsigned. Lets set the raw_value directly is a hack and needs proper review * Check for present detail before accessing it. * Add CS only groups * Use general map ins_op type * Fix build warning about str size computation. * Disable warning about unitialized value for GCC 11. Imm is initialized and the warning does not appear in later versions. * Use correct include guard for PPC * Add missing requirements * Update SystemOperand enums. * Fix overlapping comparison warning * Fix reachable assert where OpNum is not of type IMM * Handle 0.0 operand for fcmp * Fix incorrect variable passed. * Fix for MacOS which doesn't know the warning and throws another one. * Make getExtendEncoding static to fix build warning on MSVC. * Fix build error: 'missing binary operator before token' by checking __GNUC__ * Add string search to add vector layout info. * Add missing mem disponents of several ldr and str instructions. * Add 0 immediates to several instructions. * Rename v regs to q and d variant. The cs_regname API can not pass the variant name of the register requested. So we simply emit the default variant name. * Fix incorrect enum value. * Fix tests for system operands. * Fix syntax issues in tests. * Rename Arm64 -> AArch64 Python bindings. * Fix Python bindings C structs. * Fix generation of constants (ARMCC skipped because it starts with ARM) * Update const files * Remove -Wmaybe-uninitialized warning since it fails fuzz build * Add missing comma * Fix case * Fix AArch64 Python bindings: - Do not generate constants automatically (dscript is way too buggy). - Update printing of details. * Rename ARM64 -> AArch64 in test_corpus.py * Rename test_arm64 -> test_aarch64 * Rename ARM-64 -> AArch64 * Fix diff CI test by disassembling AArch64 at former ARM64 place * Fix several wrong types and remove unnecessary memebers from Python binding * Fix: Same printing format of detail for cstool, test_ and test_*.py * Fix: pass correct op index for mov alias with op[1] == reg wzr. * Set prfm op manuall in case of unnown sysop. set_imm would add it to an memory operand wihtout base. * Fix: If barrier ops are not set an assert is reached. We fix it here by simply getting the immediate as the printing code does. --------- Co-authored-by: Peace-Maker <peace-maker@wcfan.de> Co-authored-by: Dayton <5340801+watbulb@users.noreply.github.com>
2023-11-15 12:12:14 +08:00
# CS_ARCH_AARCH64, 0, None
0x00,0xf8,0xf8,0x0e = fabs v0.4h, v0.4h
0x00,0xf8,0xf8,0x2e = fneg v0.4h, v0.4h
0x00,0xd8,0xf9,0x0e = frecpe v0.4h, v0.4h
0x00,0x88,0x79,0x2e = frinta v0.4h, v0.4h
0x00,0x98,0x79,0x2e = frintx v0.4h, v0.4h
0x00,0x98,0xf9,0x2e = frinti v0.4h, v0.4h
0x00,0x98,0x79,0x0e = frintm v0.4h, v0.4h
0x00,0x88,0x79,0x0e = frintn v0.4h, v0.4h
0x00,0x88,0xf9,0x0e = frintp v0.4h, v0.4h
0x00,0x98,0xf9,0x0e = frintz v0.4h, v0.4h
0x00,0xd8,0xf9,0x2e = frsqrte v0.4h, v0.4h
0x00,0xf8,0xf9,0x2e = fsqrt v0.4h, v0.4h
0x00,0xf8,0xf8,0x4e = fabs v0.8h, v0.8h
0x00,0xf8,0xf8,0x6e = fneg v0.8h, v0.8h
0x00,0xd8,0xf9,0x4e = frecpe v0.8h, v0.8h
0x00,0x88,0x79,0x6e = frinta v0.8h, v0.8h
0x00,0x98,0x79,0x6e = frintx v0.8h, v0.8h
0x00,0x98,0xf9,0x6e = frinti v0.8h, v0.8h
0x00,0x98,0x79,0x4e = frintm v0.8h, v0.8h
0x00,0x88,0x79,0x4e = frintn v0.8h, v0.8h
0x00,0x88,0xf9,0x4e = frintp v0.8h, v0.8h
0x00,0x98,0xf9,0x4e = frintz v0.8h, v0.8h
0x00,0xd8,0xf9,0x6e = frsqrte v0.8h, v0.8h
0x00,0xf8,0xf9,0x6e = fsqrt v0.8h, v0.8h
0x20,0x10,0x22,0x0f = fmla v0.4h, v1.4h, v2.h[2]
0x03,0x11,0x12,0x4f = fmla v3.8h, v8.8h, v2.h[1]
0x20,0x50,0x22,0x0f = fmls v0.4h, v1.4h, v2.h[2]
0x03,0x51,0x12,0x4f = fmls v3.8h, v8.8h, v2.h[1]
0x20,0x90,0x22,0x0f = fmul v0.4h, v1.4h, v2.h[2]
0x20,0x90,0x22,0x4f = fmul v0.8h, v1.8h, v2.h[2]
0x20,0x90,0x22,0x2f = fmulx v0.4h, v1.4h, v2.h[2]
0x20,0x90,0x22,0x6f = fmulx v0.8h, v1.8h, v2.h[2]
0x20,0x14,0xc2,0x2e = fabd v0.4h, v1.4h, v2.4h
0x20,0xc8,0x30,0x4e = fmaxnmv h0, v1.8h
0x20,0xc8,0xb0,0x4e = fminnmv h0, v1.8h
0x20,0xf8,0x30,0x4e = fmaxv h0, v1.8h
0x20,0xf8,0xb0,0x4e = fminv h0, v1.8h
0x20,0x14,0x42,0x2e = faddp v0.4h, v1.4h, v2.4h
0x20,0x14,0x42,0x6e = faddp v0.8h, v1.8h, v2.8h
0x20,0x14,0x42,0x0e = fadd v0.4h, v1.4h, v2.4h
0x20,0x14,0x42,0x4e = fadd v0.8h, v1.8h, v2.8h
0x20,0x14,0xc2,0x0e = fsub v0.4h, v1.4h, v2.4h
0x20,0x14,0xc2,0x4e = fsub v0.8h, v1.8h, v2.8h
0xe0,0x27,0x50,0x0e = fcmeq v0.4h, v31.4h, v16.4h
0xe4,0x24,0x4f,0x4e = fcmeq v4.8h, v7.8h, v15.8h
0x03,0x25,0x4c,0x2e = fcmge v3.4h, v8.4h, v12.4h
0xbf,0x27,0x5c,0x6e = fcmge v31.8h, v29.8h, v28.8h
0x03,0x25,0x4c,0x2e = fcmge v3.4h, v8.4h, v12.4h
0xbf,0x27,0x5c,0x6e = fcmge v31.8h, v29.8h, v28.8h
0xe0,0x27,0xd0,0x2e = fcmgt v0.4h, v31.4h, v16.4h
0xe4,0x24,0xcf,0x6e = fcmgt v4.8h, v7.8h, v15.8h
0xe0,0x27,0xd0,0x2e = fcmgt v0.4h, v31.4h, v16.4h
0xe4,0x24,0xcf,0x6e = fcmgt v4.8h, v7.8h, v15.8h
0xe0,0xdb,0xf8,0x0e = fcmeq v0.4h, v31.4h, #0.0
0xe4,0xd8,0xf8,0x4e = fcmeq v4.8h, v7.8h, #0.0
0xe0,0xdb,0xf8,0x0e = fcmeq v0.4h, v31.4h, #0.0
0xe4,0xd8,0xf8,0x4e = fcmeq v4.8h, v7.8h, #0.0
0x03,0xc9,0xf8,0x2e = fcmge v3.4h, v8.4h, #0.0
0xbf,0xcb,0xf8,0x6e = fcmge v31.8h, v29.8h, #0.0
0x03,0xc9,0xf8,0x2e = fcmge v3.4h, v8.4h, #0.0
0xbf,0xcb,0xf8,0x6e = fcmge v31.8h, v29.8h, #0.0
0xe0,0xcb,0xf8,0x0e = fcmgt v0.4h, v31.4h, #0.0
0xe4,0xc8,0xf8,0x4e = fcmgt v4.8h, v7.8h, #0.0
0xe0,0xcb,0xf8,0x0e = fcmgt v0.4h, v31.4h, #0.0
0xe4,0xc8,0xf8,0x4e = fcmgt v4.8h, v7.8h, #0.0
0x83,0xda,0xf8,0x2e = fcmle v3.4h, v20.4h, #0.0
0x01,0xd9,0xf8,0x6e = fcmle v1.8h, v8.8h, #0.0
0x83,0xda,0xf8,0x2e = fcmle v3.4h, v20.4h, #0.0
0x01,0xd9,0xf8,0x6e = fcmle v1.8h, v8.8h, #0.0
0x50,0xe8,0xf8,0x0e = fcmlt v16.4h, v2.4h, #0.0
0x8f,0xe8,0xf8,0x4e = fcmlt v15.8h, v4.8h, #0.0
0x50,0xe8,0xf8,0x0e = fcmlt v16.4h, v2.4h, #0.0
0x8f,0xe8,0xf8,0x4e = fcmlt v15.8h, v4.8h, #0.0
0xe0,0x2f,0x50,0x2e = facge v0.4h, v31.4h, v16.4h
0xe4,0x2c,0x4f,0x6e = facge v4.8h, v7.8h, v15.8h
0xe0,0x2f,0x50,0x2e = facge v0.4h, v31.4h, v16.4h
0xe4,0x2c,0x4f,0x6e = facge v4.8h, v7.8h, v15.8h
0x03,0x2d,0xcc,0x2e = facgt v3.4h, v8.4h, v12.4h
0xbf,0x2f,0xdc,0x6e = facgt v31.8h, v29.8h, v28.8h
0x03,0x2d,0xcc,0x2e = facgt v3.4h, v8.4h, v12.4h
0xbf,0x2f,0xdc,0x6e = facgt v31.8h, v29.8h, v28.8h
0xe0,0x3f,0xd0,0x0e = frsqrts v0.4h, v31.4h, v16.4h
0xe4,0x3c,0xcf,0x4e = frsqrts v4.8h, v7.8h, v15.8h
0x03,0x3d,0x4c,0x0e = frecps v3.4h, v8.4h, v12.4h
0xbf,0x3f,0x5c,0x4e = frecps v31.8h, v29.8h, v28.8h
0x20,0x34,0x42,0x2e = fmaxp v0.4h, v1.4h, v2.4h
0xff,0x35,0x50,0x6e = fmaxp v31.8h, v15.8h, v16.8h
0xea,0x35,0xd6,0x2e = fminp v10.4h, v15.4h, v22.4h
0xa3,0x34,0xc6,0x6e = fminp v3.8h, v5.8h, v6.8h
0x20,0x04,0x42,0x2e = fmaxnmp v0.4h, v1.4h, v2.4h
0xff,0x05,0x50,0x6e = fmaxnmp v31.8h, v15.8h, v16.8h
0xea,0x05,0xd6,0x2e = fminnmp v10.4h, v15.4h, v22.4h
0xa3,0x04,0xc6,0x6e = fminnmp v3.8h, v5.8h, v6.8h
0x20,0x34,0x42,0x0e = fmax v0.4h, v1.4h, v2.4h
0x20,0x34,0x42,0x4e = fmax v0.8h, v1.8h, v2.8h
0xea,0x35,0xd6,0x0e = fmin v10.4h, v15.4h, v22.4h
0xea,0x35,0xd6,0x4e = fmin v10.8h, v15.8h, v22.8h
0x20,0x04,0x42,0x0e = fmaxnm v0.4h, v1.4h, v2.4h
0x20,0x04,0x42,0x4e = fmaxnm v0.8h, v1.8h, v2.8h
0xea,0x05,0xd6,0x0e = fminnm v10.4h, v15.4h, v22.4h
0xea,0x05,0xd6,0x4e = fminnm v10.8h, v15.8h, v22.8h
0x20,0x0c,0x42,0x0e = fmla v0.4h, v1.4h, v2.4h
0x20,0x0c,0x42,0x4e = fmla v0.8h, v1.8h, v2.8h
0x20,0x0c,0xc2,0x0e = fmls v0.4h, v1.4h, v2.4h
0x20,0x0c,0xc2,0x4e = fmls v0.8h, v1.8h, v2.8h
0x1d,0x17,0xd4,0x7e = fabd h29, h24, h20
0x20,0x18,0x11,0x5f = fmla h0, h1, v1.h[5]
0x62,0x58,0x14,0x5f = fmls h2, h3, v4.h[5]
0x20,0x98,0x11,0x5f = fmul h0, h1, v1.h[5]
0x46,0x98,0x18,0x7f = fmulx h6, h2, v8.h[5]
0x95,0xfd,0x1f,0x5f = fcvtzs h21, h12, #1
0x95,0xfd,0x1f,0x7f = fcvtzu h21, h12, #1
0xac,0xc9,0x79,0x5e = fcvtas h12, h13
0xac,0xc9,0x79,0x7e = fcvtau h12, h13
0xb6,0xb9,0x79,0x5e = fcvtms h22, h13
0xac,0xb9,0x79,0x7e = fcvtmu h12, h13
0xb6,0xa9,0x79,0x5e = fcvtns h22, h13
0xac,0xa9,0x79,0x7e = fcvtnu h12, h13
0xb6,0xa9,0xf9,0x5e = fcvtps h22, h13
0xac,0xa9,0xf9,0x7e = fcvtpu h12, h13
0xac,0xb9,0xf9,0x5e = fcvtzs h12, h13
0xac,0xb9,0xf9,0x7e = fcvtzu h12, h13
0x6a,0x25,0x4c,0x5e = fcmeq h10, h11, h12
0x6a,0xd9,0xf8,0x5e = fcmeq h10, h11, #0.0
0x6a,0xd9,0xf8,0x5e = fcmeq h10, h11, #0.0
0x6a,0x25,0x4c,0x7e = fcmge h10, h11, h12
0x6a,0xc9,0xf8,0x7e = fcmge h10, h11, #0.0
0x6a,0xc9,0xf8,0x7e = fcmge h10, h11, #0.0
0x6a,0x25,0xcc,0x7e = fcmgt h10, h11, h12
0x6a,0xc9,0xf8,0x5e = fcmgt h10, h11, #0.0
0x6a,0xc9,0xf8,0x5e = fcmgt h10, h11, #0.0
0x6a,0xd9,0xf8,0x7e = fcmle h10, h11, #0.0
0x6a,0xd9,0xf8,0x7e = fcmle h10, h11, #0.0
0x6a,0xe9,0xf8,0x5e = fcmlt h10, h11, #0.0
0x6a,0xe9,0xf8,0x5e = fcmlt h10, h11, #0.0
0x6a,0x2d,0x4c,0x7e = facge h10, h11, h12
0x6a,0x2d,0xcc,0x7e = facgt h10, h11, h12
0xd4,0x1e,0x4f,0x5e = fmulx h20, h22, h15
0x15,0x3e,0x4d,0x5e = frecps h21, h16, h13
0xb5,0x3c,0xcc,0x5e = frsqrts h21, h5, h12
0xd3,0xd9,0xf9,0x5e = frecpe h19, h14
0x52,0xf9,0xf9,0x5e = frecpx h18, h10
0xb6,0xd9,0xf9,0x7e = frsqrte h22, h13
0x72,0xd8,0x30,0x5e = faddp h18, v3.2h
0x04,0xf8,0xf8,0x0e = fabs v4.4h, v0.4h
0x06,0xf9,0xf8,0x4e = fabs v6.8h, v8.8h
0x04,0xf8,0xf8,0x2e = fneg v4.4h, v0.4h
0x06,0xf9,0xf8,0x6e = fneg v6.8h, v8.8h
0x04,0x88,0x79,0x0e = frintn v4.4h, v0.4h
0x06,0x89,0x79,0x4e = frintn v6.8h, v8.8h
0x04,0x88,0x79,0x2e = frinta v4.4h, v0.4h
0x06,0x89,0x79,0x6e = frinta v6.8h, v8.8h
0x04,0x88,0xf9,0x0e = frintp v4.4h, v0.4h
0x06,0x89,0xf9,0x4e = frintp v6.8h, v8.8h
0x04,0x98,0x79,0x0e = frintm v4.4h, v0.4h
0x06,0x99,0x79,0x4e = frintm v6.8h, v8.8h
0x04,0x98,0x79,0x2e = frintx v4.4h, v0.4h
0x06,0x99,0x79,0x6e = frintx v6.8h, v8.8h
0x04,0x98,0xf9,0x0e = frintz v4.4h, v0.4h
0x06,0x99,0xf9,0x4e = frintz v6.8h, v8.8h
0x04,0x98,0xf9,0x2e = frinti v4.4h, v0.4h
0x06,0x99,0xf9,0x6e = frinti v6.8h, v8.8h
0x04,0xa8,0x79,0x0e = fcvtns v4.4h, v0.4h
0x06,0xa9,0x79,0x4e = fcvtns v6.8h, v8.8h
0x04,0xa8,0x79,0x2e = fcvtnu v4.4h, v0.4h
0x06,0xa9,0x79,0x6e = fcvtnu v6.8h, v8.8h
0x04,0xa8,0xf9,0x0e = fcvtps v4.4h, v0.4h
0x06,0xa9,0xf9,0x4e = fcvtps v6.8h, v8.8h
0x04,0xa8,0xf9,0x2e = fcvtpu v4.4h, v0.4h
0x06,0xa9,0xf9,0x6e = fcvtpu v6.8h, v8.8h
0x04,0xb8,0x79,0x0e = fcvtms v4.4h, v0.4h
0x06,0xb9,0x79,0x4e = fcvtms v6.8h, v8.8h
0x04,0xb8,0x79,0x2e = fcvtmu v4.4h, v0.4h
0x06,0xb9,0x79,0x6e = fcvtmu v6.8h, v8.8h
0x04,0xb8,0xf9,0x0e = fcvtzs v4.4h, v0.4h
0x06,0xb9,0xf9,0x4e = fcvtzs v6.8h, v8.8h
0x04,0xb8,0xf9,0x2e = fcvtzu v4.4h, v0.4h
0x06,0xb9,0xf9,0x6e = fcvtzu v6.8h, v8.8h
0x04,0xc8,0x79,0x0e = fcvtas v4.4h, v0.4h
0x06,0xc9,0x79,0x4e = fcvtas v6.8h, v8.8h
0x04,0xc8,0x79,0x2e = fcvtau v4.4h, v0.4h
0x06,0xc9,0x79,0x6e = fcvtau v6.8h, v8.8h
0x04,0xd8,0xf9,0x0e = frecpe v4.4h, v0.4h
0x06,0xd9,0xf9,0x4e = frecpe v6.8h, v8.8h
0x04,0xd8,0xf9,0x2e = frsqrte v4.4h, v0.4h
0x06,0xd9,0xf9,0x6e = frsqrte v6.8h, v8.8h
0x04,0xf8,0xf9,0x2e = fsqrt v4.4h, v0.4h
0x06,0xf9,0xf9,0x6e = fsqrt v6.8h, v8.8h