2016-10-19 22:28:05 +08:00
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/* Tang Yuhang <tyh000011112222@gmail.com> 2016 */
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2017-07-04 15:55:46 +08:00
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/* pancake <pancake@nopcode.org> 2017 */
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2016-10-10 15:16:56 +08:00
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#include <string.h>
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#include <ctype.h>
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#include <errno.h>
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2017-07-04 15:55:46 +08:00
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#include "getopt.h"
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2016-10-10 15:16:56 +08:00
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2016-10-11 00:04:46 +08:00
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#include <capstone/capstone.h>
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2016-10-10 15:16:56 +08:00
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2017-07-04 15:55:46 +08:00
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static struct {
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const char *name;
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cs_arch arch;
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cs_mode mode;
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2017-07-04 16:04:53 +08:00
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} all_archs[] = {
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2017-07-04 15:55:46 +08:00
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{ "arm", CS_ARCH_ARM, CS_MODE_ARM },
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{ "armb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
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{ "armbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_BIG_ENDIAN },
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{ "arml", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
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{ "armle", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_LITTLE_ENDIAN },
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{ "thumb", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB },
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{ "thumbbe", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_BIG_ENDIAN },
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{ "thumble", CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_THUMB | CS_MODE_LITTLE_ENDIAN },
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{ "arm64", CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN },
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{ "arm64be", CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN },
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{ "mips", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_LITTLE_ENDIAN },
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{ "mipsbe", CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN },
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{ "mips64", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN },
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{ "mips64be", CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_BIG_ENDIAN },
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{ "x16", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16
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{ "x16att", CS_ARCH_X86, CS_MODE_16 }, // CS_MODE_16 , CS_OPT_SYNTAX_ATT
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{ "x32", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32
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{ "x32att", CS_ARCH_X86, CS_MODE_32 }, // CS_MODE_32, CS_OPT_SYNTAX_ATT
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{ "x64", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64
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{ "x64att", CS_ARCH_X86, CS_MODE_64 }, // CS_MODE_64, CS_OPT_SYNTAX_ATT
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{ "ppc64", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_LITTLE_ENDIAN },
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{ "ppc64be", CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN },
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{ "sparc", CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN },
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{ "systemz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
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{ "sysz", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
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{ "s390x", CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN },
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{ "xcore", CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN },
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{ "m68k", CS_ARCH_M68K, CS_MODE_BIG_ENDIAN },
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{ "m68k40", CS_ARCH_M68K, CS_MODE_M68K_040 },
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{ "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN },
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{ "tms320c64x", CS_ARCH_TMS320C64X, CS_MODE_BIG_ENDIAN },
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M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 21:44:36 +08:00
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{ "m6800", CS_ARCH_M680X, CS_MODE_M680X_6800 },
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{ "m6801", CS_ARCH_M680X, CS_MODE_M680X_6801 },
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{ "m6805", CS_ARCH_M680X, CS_MODE_M680X_6805 },
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{ "m6808", CS_ARCH_M680X, CS_MODE_M680X_6808 },
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{ "m6809", CS_ARCH_M680X, CS_MODE_M680X_6809 },
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{ "m6811", CS_ARCH_M680X, CS_MODE_M680X_6811 },
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{ "cpu12", CS_ARCH_M680X, CS_MODE_M680X_CPU12 },
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{ "hd6301", CS_ARCH_M680X, CS_MODE_M680X_6301 },
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{ "hd6309", CS_ARCH_M680X, CS_MODE_M680X_6309 },
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{ "hcs08", CS_ARCH_M680X, CS_MODE_M680X_HCS08 },
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2017-07-04 15:55:46 +08:00
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{ NULL }
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};
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2016-10-14 17:29:56 +08:00
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void print_insn_detail_x86(csh ud, cs_mode mode, cs_insn *ins);
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2016-10-14 20:47:29 +08:00
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void print_insn_detail_arm(csh handle, cs_insn *ins);
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void print_insn_detail_arm64(csh handle, cs_insn *ins);
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void print_insn_detail_mips(csh handle, cs_insn *ins);
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void print_insn_detail_ppc(csh handle, cs_insn *ins);
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void print_insn_detail_sparc(csh handle, cs_insn *ins);
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void print_insn_detail_sysz(csh handle, cs_insn *ins);
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void print_insn_detail_xcore(csh handle, cs_insn *ins);
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2016-10-28 15:32:50 +08:00
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void print_insn_detail_m68k(csh handle, cs_insn *ins);
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2017-04-17 16:58:29 +08:00
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void print_insn_detail_tms320c64x(csh handle, cs_insn *ins);
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M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 21:44:36 +08:00
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void print_insn_detail_m680x(csh handle, cs_insn *ins);
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2017-07-04 15:55:46 +08:00
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static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins);
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2016-10-14 17:29:56 +08:00
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2016-10-21 16:42:47 +08:00
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void print_string_hex(char *comment, unsigned char *str, size_t len)
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{
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unsigned char *c;
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printf("%s", comment);
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for (c = str; c < str + len; c++) {
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printf("0x%02x ", *c & 0xff);
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}
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printf("\n");
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}
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2016-10-10 15:16:56 +08:00
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// convert hexchar to hexnum
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static uint8_t char_to_hexnum(char c)
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{
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2016-10-10 23:20:29 +08:00
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if (c >= '0' && c <= '9') {
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2016-10-21 16:03:35 +08:00
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return (uint8_t)(c - '0');
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2016-10-10 23:20:29 +08:00
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}
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if (c >= 'a' && c <= 'f') {
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return (uint8_t)(10 + c - 'a');
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}
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// c >= 'A' && c <= 'F'
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return (uint8_t)(10 + c - 'A');
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2016-10-10 15:16:56 +08:00
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}
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2016-10-10 23:20:29 +08:00
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// convert user input (char[]) to uint8_t[], each element of which is
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// valid hexadecimal, and return actual length of uint8_t[] in @size.
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2016-10-10 15:16:56 +08:00
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static uint8_t *preprocess(char *code, size_t *size)
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{
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2016-10-21 16:03:35 +08:00
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size_t i = 0, j = 0;
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2016-10-10 23:20:29 +08:00
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uint8_t high, low;
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uint8_t *result;
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2017-07-26 23:22:46 +08:00
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if (strlen(code) == 0)
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return NULL;
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2016-10-10 23:20:29 +08:00
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result = (uint8_t *)malloc(strlen(code));
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if (result != NULL) {
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while (code[i] != '\0') {
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if (isxdigit(code[i]) && isxdigit(code[i+1])) {
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high = 16 * char_to_hexnum(code[i]);
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low = char_to_hexnum(code[i+1]);
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result[j] = high + low;
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i++;
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j++;
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}
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i++;
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}
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*size = j;
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}
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return result;
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2016-10-10 15:16:56 +08:00
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}
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2016-10-10 23:20:29 +08:00
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static void usage(char *prog)
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2016-10-10 15:16:56 +08:00
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{
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2016-11-04 23:57:52 +08:00
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printf("Cstool for Capstone Disassembler Engine v%u.%u.%u\n\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA);
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2017-06-16 02:13:28 +08:00
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printf("Syntax: %s [-u|-d] <arch+mode> <assembly-hexstring> [start-address-in-hex-format]\n", prog);
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2016-10-10 23:20:29 +08:00
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printf("\nThe following <arch+mode> options are supported:\n");
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if (cs_support(CS_ARCH_X86)) {
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printf(" x16: 16-bit mode (X86)\n");
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printf(" x32: 32-bit mode (X86)\n");
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printf(" x64: 64-bit mode (X86)\n");
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printf(" x16att: 16-bit mode (X86) syntax-att\n");
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printf(" x32att: 32-bit mode (X86) syntax-att\n");
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printf(" x64att: 64-bit mode (X86) syntax-att\n");
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}
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if (cs_support(CS_ARCH_ARM)) {
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printf(" arm: arm\n");
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2017-03-10 20:30:55 +08:00
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printf(" armbe: arm + big endian\n");
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2016-10-10 23:20:29 +08:00
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printf(" thumb: thumb mode\n");
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printf(" thumbbe: thumb + big endian\n");
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}
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if (cs_support(CS_ARCH_ARM64)) {
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printf(" arm64: aarch64 mode\n");
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2017-04-25 21:33:26 +08:00
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printf(" arm64be: aarch64 + big endian\n");
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2016-10-10 23:20:29 +08:00
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}
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if (cs_support(CS_ARCH_MIPS)) {
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printf(" mips: mips32 + little endian\n");
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printf(" mipsbe: mips32 + big endian\n");
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printf(" mips64: mips64 + little endian\n");
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printf(" mips64be: mips64 + big endian\n");
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}
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if (cs_support(CS_ARCH_PPC)) {
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printf(" ppc64: ppc64 + little endian\n");
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printf(" ppc64be: ppc64 + big endian\n");
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}
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if (cs_support(CS_ARCH_SPARC)) {
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printf(" sparc: sparc\n");
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}
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|
|
|
|
if (cs_support(CS_ARCH_SYSZ)) {
|
|
|
|
printf(" systemz: systemz (s390x)\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_XCORE)) {
|
|
|
|
printf(" xcore: xcore\n");
|
|
|
|
}
|
2016-10-27 12:12:59 +08:00
|
|
|
|
|
|
|
if (cs_support(CS_ARCH_M68K)) {
|
2016-10-28 16:12:05 +08:00
|
|
|
printf(" m68k: m68k + big endian\n");
|
2016-10-27 12:12:59 +08:00
|
|
|
printf(" m68k40: m68k_040\n");
|
|
|
|
}
|
2016-10-10 23:20:29 +08:00
|
|
|
|
2017-04-17 16:58:29 +08:00
|
|
|
if (cs_support(CS_ARCH_TMS320C64X)) {
|
|
|
|
printf(" tms320c64x:TMS320C64x\n");
|
|
|
|
}
|
|
|
|
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 21:44:36 +08:00
|
|
|
if (cs_support(CS_ARCH_M680X)) {
|
|
|
|
printf(" m6800: M6800/2\n");
|
|
|
|
printf(" m6801: M6801/3\n");
|
|
|
|
printf(" m6805: M6805\n");
|
|
|
|
printf(" m6808: M68HC08\n");
|
|
|
|
printf(" m6809: M6809\n");
|
|
|
|
printf(" m6811: M68HC11\n");
|
|
|
|
printf(" cpu12: M68HC12/HCS12\n");
|
|
|
|
printf(" hd6301: HD6301/3\n");
|
|
|
|
printf(" hd6309: HD6309\n");
|
|
|
|
printf(" hcs08: HCS08\n");
|
|
|
|
}
|
|
|
|
|
2017-07-04 16:04:53 +08:00
|
|
|
printf("\nExtra options:\n");
|
|
|
|
printf(" -d show detailed information of the instructions\n");
|
|
|
|
printf(" -u show immediates as unsigned\n\n");
|
2016-10-10 15:16:56 +08:00
|
|
|
}
|
|
|
|
|
2017-07-04 15:55:46 +08:00
|
|
|
static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins)
|
|
|
|
{
|
|
|
|
switch(arch) {
|
|
|
|
case CS_ARCH_X86:
|
|
|
|
print_insn_detail_x86(handle, md, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_ARM:
|
|
|
|
print_insn_detail_arm(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_ARM64:
|
|
|
|
print_insn_detail_arm64(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_MIPS:
|
|
|
|
print_insn_detail_mips(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_PPC:
|
|
|
|
print_insn_detail_ppc(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_SPARC:
|
|
|
|
print_insn_detail_sparc(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_SYSZ:
|
|
|
|
print_insn_detail_sysz(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_XCORE:
|
|
|
|
print_insn_detail_xcore(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_M68K:
|
|
|
|
print_insn_detail_m68k(handle, ins);
|
|
|
|
break;
|
|
|
|
case CS_ARCH_TMS320C64X:
|
|
|
|
print_insn_detail_tms320c64x(handle, ins);
|
|
|
|
break;
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 21:44:36 +08:00
|
|
|
case CS_ARCH_M680X:
|
|
|
|
print_insn_detail_m680x(handle, ins);
|
|
|
|
break;
|
2017-07-04 15:55:46 +08:00
|
|
|
default: break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ins->detail->groups_count) {
|
|
|
|
int j;
|
|
|
|
|
|
|
|
printf("\tGroups: ");
|
|
|
|
for(j = 0; j < ins->detail->groups_count; j++) {
|
|
|
|
printf("%s ", cs_group_name(handle, ins->detail->groups[j]));
|
|
|
|
}
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
printf("\n");
|
|
|
|
}
|
|
|
|
|
2016-10-10 15:16:56 +08:00
|
|
|
int main(int argc, char **argv)
|
|
|
|
{
|
2017-07-04 15:55:46 +08:00
|
|
|
int i, c;
|
2016-10-10 23:20:29 +08:00
|
|
|
csh handle;
|
|
|
|
char *mode;
|
|
|
|
uint8_t *assembly;
|
|
|
|
size_t count, size;
|
2017-07-04 15:55:46 +08:00
|
|
|
uint64_t address = 0LL;
|
2016-10-10 23:20:29 +08:00
|
|
|
cs_insn *insn;
|
|
|
|
cs_err err;
|
2016-10-21 16:03:35 +08:00
|
|
|
cs_mode md;
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 21:44:36 +08:00
|
|
|
cs_arch arch = CS_ARCH_ALL;
|
2016-10-21 16:42:47 +08:00
|
|
|
bool detail_flag = false;
|
2017-06-16 02:13:28 +08:00
|
|
|
bool unsigned_flag = false;
|
2017-07-04 16:04:53 +08:00
|
|
|
int args_left;
|
2016-10-10 23:20:29 +08:00
|
|
|
|
2017-07-04 15:55:46 +08:00
|
|
|
while ((c = getopt (argc, argv, "udhv")) != -1) {
|
|
|
|
switch (c) {
|
|
|
|
case 'u':
|
2017-06-16 02:13:28 +08:00
|
|
|
unsigned_flag = true;
|
2017-07-04 15:55:46 +08:00
|
|
|
break;
|
|
|
|
case 'd':
|
|
|
|
detail_flag = true;
|
|
|
|
break;
|
|
|
|
case 'v':
|
|
|
|
printf("%u.%u.%u\n", CS_VERSION_MAJOR, CS_VERSION_MINOR, CS_VERSION_EXTRA);
|
|
|
|
return 0;
|
|
|
|
case 'h':
|
|
|
|
usage(argv[0]);
|
|
|
|
return 0;
|
|
|
|
default:
|
2016-10-21 16:03:35 +08:00
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
|
|
|
}
|
2016-10-10 23:20:29 +08:00
|
|
|
}
|
2017-07-04 16:04:53 +08:00
|
|
|
|
|
|
|
args_left = argc - optind;
|
2017-07-04 15:55:46 +08:00
|
|
|
if (args_left < 2 || args_left > 3) {
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
2016-10-10 23:20:29 +08:00
|
|
|
}
|
|
|
|
|
2017-07-04 15:55:46 +08:00
|
|
|
mode = argv[optind];
|
|
|
|
assembly = preprocess(argv[optind + 1], &size);
|
2017-07-26 23:22:46 +08:00
|
|
|
if (!assembly) {
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
|
|
|
}
|
2017-07-04 16:04:53 +08:00
|
|
|
|
2017-07-04 15:55:46 +08:00
|
|
|
if (args_left == 3) {
|
|
|
|
char *temp, *src = argv[optind + 2];
|
|
|
|
address = strtoull(src, &temp, 16);
|
|
|
|
if (temp == src || *temp != '\0' || errno == ERANGE) {
|
|
|
|
printf("ERROR: invalid address argument, quit!\n");
|
|
|
|
return -2;
|
2016-10-10 23:20:29 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2017-07-04 16:04:53 +08:00
|
|
|
for (i = 0; all_archs[i].name; i++) {
|
|
|
|
if (!strcmp(all_archs[i].name, mode)) {
|
|
|
|
arch = all_archs[i].arch;
|
|
|
|
err = cs_open(all_archs[i].arch, all_archs[i].mode, &handle);
|
2017-07-04 15:55:46 +08:00
|
|
|
if (!err) {
|
2017-07-04 16:04:53 +08:00
|
|
|
md = all_archs[i].mode;
|
2017-07-04 15:55:46 +08:00
|
|
|
if (strstr (mode, "att")) {
|
|
|
|
cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
2016-10-10 23:20:29 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
M680X: Target ready for pull request (#1034)
* Added new M680X target. Supports M6800/1/2/3/9, HD6301
* M680X: Reformat for coding guide lines. Set alphabetical order in HACK.TXT
* M680X: Prepare for python binding. Move cs_m680x, m680x_insn to m680x_info. Chec
> k cpu type, no default.
* M680X: Add python bindings. Added python tests.
* M680X: Added cpu types to usage message.
* cstool: Avoid segfault for invalid <arch+mode>.
* Make test_m680x.c/test_m680x.py output comparable (diff params: -bu). Keep xprint.py untouched.
* M680X: Update CMake/make for m680x support. Update .gitignore.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Reduce compiler warnings.
* M680X: Make test_m680x.c/test_m680x.py output comparable (diff params: -bu).
* M680X: Add ocaml bindings and tests.
* M680X: Add java bindings and tests.
* M680X: Added tests for all indexed addressing modes. C/Python/Ocaml
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Naming, use page1 for PAGE1 instructions (without prefix).
* M680X: Used M680X_FIRST_OP_IN_MNEM in tests C/python/java/ocaml.
* M680X: Added access property to cs_m680x_op.
* M680X: Added operand size.
* M680X: Remove compiler warnings.
* M680X: Added READ/WRITE access property per operator.
* M680X: Make reg_inherent_hdlr independent of CPU type.
* M680X: Add HD6309 support + bug fixes
* M680X: Remove errors and warning.
* M680X: Add Bcc/LBcc to group BRAREL (relative branch).
* M680X: Add group JUMP to BVS/BVC/LBVS/LBVC. Remove BRAREL from BRN/LBRN.
* M680X: Remove LBRN from group BRAREL.
* M680X: Refactored cpu_type initialization for better readability.
* M680X: Add two operands for insn having two reg. in mnemonic. e.g. ABX.
* M680X: Remove typo in cstool.c
* M680X: Some format improvements in changed_regs.
* M680X: Remove insn id string list from tests (C/python/java/ocaml).
* M680X: SEXW, set access of reg. D to WRITE.
* M680X: Sort changed_regs in increasing m680x_insn order.
* M680X: Add M68HC11 support + Reduced from two to one INDEXED operand.
* M680X: cstool, also write '(in mnemonic)' for second reg. operand.
* M680X: Add BRN/LBRN to group JUMP and BRAREL.
* M680X: For Bcc/LBcc/BRSET/BRCLR set reg. CC to read access.
* M680X: Correctly print negative immediate values with option CS_OPT_UNSIGNED.
* M680X: Rename some instruction handlers.
* M680X: Add M68HC05 support.
* M680X: Dont print prefix '<' for direct addr. mode.
* M680X: Add M68HC08 support + resorted tables + bug fixes.
* M680X: Add Freescale HCS08 support.
* M680X: Changed group names, avoid spaces.
* M680X: Refactoring, rename addessing mode handlers.
* M680X: indexed addr. mode, changed pre/post inc-/decrement representation.
* M680X: Rename some M6809/HD6309 specific functions.
* M680X: Add CPU12 (68HC12/HCS12) support.
* M680X: Correctly display illegal instruction as FCB .
* M680X: bugfix: BRA/BRN/BSR/LBRA/LBRN/LBSR does not read CC reg.
* M680X: bugfix: Correctly check for sufficient code size for M6809 indexed addressing.
* M680X: Better support for changing insn id within handler for addessing mode.
* M680X: Remove warnings.
* M680X: In set_changed_regs_read_write_counts use own access_mode.
* M680X: Split cpu specific tables into separate *.inc files.
* M680X: Remove warnings.
* M680X: Removed address_mode. Addressing mode is available in operand.type
* M680X: Bugfix: BSET/BCLR/BRSET/BRCLR correct read/modify CC reg.
* M680X: Remove register TMP1. It is first visible in CPU12X.
* M680X: Performance improvement + bug fixes.
* M680X: Performance improvement, make cpu_tables const static.
* M680X: Simplify operand decoding by using two handlers.
* M680X: Replace M680X_OP_INDEX by M680X_OP_CONSTANT + bugfix in java/python/ocaml bindings.
* M680X: Format with astyle.
* M680X: Update documentation.
* M680X: Corrected author for m680x specific files.
* M680X: Make max. number of architectures single source.
2017-10-21 21:44:36 +08:00
|
|
|
if (arch == CS_ARCH_ALL) {
|
|
|
|
printf("ERROR: Invalid <arch+mode>: \"%s\", quit!\n", mode);
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-10 23:20:29 +08:00
|
|
|
if (err) {
|
|
|
|
printf("ERROR: Failed on cs_open(), quit!\n");
|
|
|
|
usage(argv[0]);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2016-10-21 16:42:47 +08:00
|
|
|
if (detail_flag) {
|
2016-10-21 16:03:35 +08:00
|
|
|
cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
|
|
|
|
}
|
2017-07-04 16:04:53 +08:00
|
|
|
|
2017-06-16 02:13:28 +08:00
|
|
|
if (unsigned_flag) {
|
|
|
|
cs_option(handle, CS_OPT_UNSIGNED, CS_OPT_ON);
|
|
|
|
}
|
2016-10-14 17:29:56 +08:00
|
|
|
|
2016-10-21 16:03:35 +08:00
|
|
|
count = cs_disasm(handle, assembly, size, address, 0, &insn);
|
2016-10-10 23:20:29 +08:00
|
|
|
if (count > 0) {
|
2016-10-11 16:19:27 +08:00
|
|
|
size_t i;
|
|
|
|
|
|
|
|
for (i = 0; i < count; i++) {
|
|
|
|
int j;
|
2017-07-04 16:04:53 +08:00
|
|
|
|
2016-10-11 16:19:27 +08:00
|
|
|
printf("%"PRIx64" ", insn[i].address);
|
|
|
|
for (j = 0; j < insn[i].size; j++) {
|
2017-09-06 21:35:19 +08:00
|
|
|
if (j > 0)
|
|
|
|
putchar(' ');
|
2016-10-11 16:19:27 +08:00
|
|
|
printf("%02x", insn[i].bytes[j]);
|
|
|
|
}
|
|
|
|
// X86 instruction size is variable.
|
|
|
|
// align assembly instruction after the opcode
|
2016-10-21 16:42:47 +08:00
|
|
|
if (arch == CS_ARCH_X86) {
|
2016-10-11 16:19:27 +08:00
|
|
|
for (; j < 16; j++) {
|
|
|
|
printf(" ");
|
|
|
|
}
|
2016-10-10 23:20:29 +08:00
|
|
|
}
|
2016-10-21 16:42:47 +08:00
|
|
|
|
2016-10-11 16:19:27 +08:00
|
|
|
printf(" %s\t%s\n", insn[i].mnemonic, insn[i].op_str);
|
2016-10-21 16:42:47 +08:00
|
|
|
|
|
|
|
if (detail_flag) {
|
2017-07-04 15:55:46 +08:00
|
|
|
print_details(handle, arch, md, &insn[i]);
|
2016-10-21 16:03:35 +08:00
|
|
|
}
|
2016-10-10 23:20:29 +08:00
|
|
|
}
|
2016-11-05 00:43:22 +08:00
|
|
|
|
2016-10-10 23:20:29 +08:00
|
|
|
cs_free(insn, count);
|
|
|
|
} else {
|
|
|
|
printf("ERROR: invalid assembly code\n");
|
|
|
|
return(-4);
|
|
|
|
}
|
|
|
|
|
|
|
|
cs_close(&handle);
|
|
|
|
|
|
|
|
return 0;
|
2016-10-10 15:16:56 +08:00
|
|
|
}
|