26 lines
1.1 KiB
TableGen
26 lines
1.1 KiB
TableGen
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//===- AArch64SchedPredAmpere.td - AArch64 Sched Preds -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are used by the
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// AArch64 Ampere Computing processors.
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//
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//===----------------------------------------------------------------------===//
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// Auxiliary predicates.
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// Check for a LSL shift <= 4
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def AmpereCheapLSL : MCSchedPredicate<
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CheckAny<[CheckShiftBy0,
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CheckAll<
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[CheckShiftLSL,
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CheckAny<
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[CheckShiftBy1,
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CheckShiftBy2,
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CheckShiftBy3,
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CheckShiftBy4]>]>]>>;
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