capstone/suite/benchmark.py

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#!/usr/bin/python
# Simple benchmark for Capstone by disassembling random code. By Nguyen Anh Quynh, 2014
# Syntax:
# ./suite/benchmark.py --> Benchmark all archs
# ./suite/benchmark.py x86 --> Benchmark all X86 (all 16bit, 32bit, 64bit)
# ./suite/benchmark.py x86-32 --> Benchmark X86-32 arch only
# ./suite/benchmark.py arm --> Benchmark all ARM (arm, thumb)
# ./suite/benchmark.py aarch64 --> Benchmark ARM-64
# ./suite/benchmark.py mips --> Benchmark all Mips (32bit, 64bit)
# ./suite/benchmark.py ppc --> Benchmark PPC
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from capstone import *
from time import time
from random import randint
import sys
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# file providing code to disassemble
FILE = '/usr/bin/python'
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all_tests = (
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(CS_ARCH_X86, CS_MODE_16, "X86-16 (Intel syntax)", 0),
(CS_ARCH_X86, CS_MODE_32, "X86-32 (ATT syntax)", CS_OPT_SYNTAX_ATT),
(CS_ARCH_X86, CS_MODE_32, "X86-32 (Intel syntax)", 0),
(CS_ARCH_X86, CS_MODE_64, "X86-64 (Intel syntax)", 0),
(CS_ARCH_ARM, CS_MODE_ARM, "ARM", 0),
(CS_ARCH_ARM, CS_MODE_THUMB, "THUMB (ARM)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, "MIPS-32 (Big-endian)", 0),
(CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, "MIPS-64-EL (Little-endian)", 0),
(CS_ARCH_ARM64, CS_MODE_ARM, "ARM-64 (AArch64)", 0),
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(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC", 0),
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, "PPC, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
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(CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, "Sparc", 0),
(CS_ARCH_SYSZ, 0, "SystemZ", 0),
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(CS_ARCH_XCORE, 0, "XCore", 0),
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(CS_ARCH_M68K, 0, "M68K", 0),
RISCV support ISRV32/ISRV64 (#1401) * Added RISCV dir to contain the RISCV architecture engine code. Adding the TableGen files generated from llvm-tblgen. Add Disassembler.h * Started working on RISCVDisassembler.c - RISCV_init(), RISCVDisassembler_getInstruction, and RISCV_getInstruction * Added all functions to RISCVDisassembler.c and needed modifications to RISCVGenDisassemblerTables.inc. Add and modified RISCVGenSubtargetInfo.inc. Start creation of RISCVInstPrinter.h * Finished RISCVGenAsmWriter.inc. Finished RISCVGenRegisterInfo.inc. Minor fixes to RISCVDisassembler.c. Working on RISCVInstPrinter * Finished RISCVInstPrinter, RISCVMapping, RISCVBaseInfo, RISCVGenInstrInfo.inc, RISCVModule.c. Working on riscv.h * Backport it from: https://github.com/porto703/capstone/commit/0db412ce3bed9d963caf598a2cb7dc76b41a5a2b * All RISCV files added. Compiled correctly and initial test for ADD, ADDI, AND works properly. * Add refactored cs.c for RISCV * Testing all I instructions in test_riscv.c * Modify the orignal backport for RISCVGenRegisterInfo.inc, capstone.h and test_iter to work w/ the current code strcuture * Fix issue with RISCVGenRegisterInfo.inc - RISCVRegDesc[] (Excess elements in struct initializer). Added RISCV tests to test_iter.c * fixed bug related to incorrect initialization of memory after malloc * fix compile bug * Fix compile errors. * move riscv.h to include/capstone * fix indentation issues * fix coding style issues * Fix indentation issues * fix coding style * Move variable declaration to the top of the block * Fix coding indentation * Move some stuff into RISCVMappingInsn.inc * Fix code sytle * remove cs_mode support for RISCV * update asmwriter-inc to LLVM upstream * update the .inc files to riscv upstream * update riscv disassembler function for suport 16bit instructions * update printer & tablegen inc files which have fixed arguments mismatch * update headers and mapping source * add riscv architecture specific test code * fix all RISCV tons of compiler errors * pass final tests * add riscv tablegen patchs * merge with upstream/next * fix cstool missing riscv file * fix root Makefile * add new TableGen patchs for riscv * fix cmakefile.txt of missing one riscv file * fix declaration conflict * fix incompatible declaration type * change riscvc from arch to mode * fix test_riscv warnning * fix code style and add riscv part of test_basic * add RISCV64 mode * add suite for riscv * crack fuzz test * fix getfeaturebits test add riscvc * fix test missing const qualifier warnning * fix testcase type mismatch * fix return value missing * change getfeaturebits test * add test cs files * using a winder type contain the decode string * fix a copy typo * remove useless mode for riscv * change cs file blank type * add repo for update_riscv & fix cstool missing riscv mode * fix typo * add riscv for cstool useage * add TableGen patch for riscv asmwriter * clean ctags file * remove black comment line * fix fuzz related something * fix missing RISCV string of fuzz * update readme, etc.. * add riscv *.s.cs file * add riscv *.s.cs file & clear ctags * clear useless array declarations at capstone_test * update to 5e4069f * update readme change name more formal * change position of riscv after bpf and modify copyright more uniform * clear useless ctags file * change blank with tab in riscv.h * add riscv python bindings * add riscv in __init__.py * fix riscv define value for python binding * fix test_riscv.py typo * add missing riscvc in __init__.py of python bindings * fix alias-insn printer bug, remove useless newline * change inst print delimter from tab to bankspace for travis * add riscv tablegen patch * fix inst output more consistency * add TableGen patch which fix inst output formal * crack the effective address output for detail and change register print function * fix not detail crash bug * change item declaration position at cs_riscv * update riscv.py * change function name more meaningfull * update python binding makefile * fix register enum sequence according to riscvgenreginfo.inc * test function name * add enum s0/fp in riscv.h & update riscv_const.py * add register name enum
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(CS_ARCH_RISCV, 0, "RISCV", 0),
)
# for debugging
def to_hex(s):
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
def get_code(f, size):
code = f.read(size)
if len(code) != size: # reached end-of-file?
# then reset file position to begin-of-file
f.seek(0)
code = f.read(size)
return code
def cs(md, code):
insns = md.disasm(code, 0)
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# uncomment below line to speed up this function 200 times!
# return
for i in insns:
if i.address == 0x100000:
print i
def cs_lite(md, code):
insns = md.disasm_lite(code, 0)
for (addr, size, mnem, ops) in insns:
if addr == 0x100000:
print i
cfile = open(FILE)
for (arch, mode, comment, syntax) in all_tests:
try:
request = sys.argv[1]
if not request in comment.lower():
continue
except:
pass
print("Platform: %s" %comment)
try:
md = Cs(arch, mode)
#md.detail = True
if syntax != 0:
md.syntax = syntax
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# warm up few times
cfile.seek(0)
for i in xrange(3):
code = get_code(cfile, 128)
#print to_hex(code)
#print
cs(md, code)
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# start real benchmark
c_t = 0
for i in xrange(50000):
code = get_code(cfile, 128)
#print to_hex(code)
#print
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t1 = time()
cs(md, code)
c_t += time() - t1
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print "Benchmark - full obj:", c_t, "seconds"
print
cfile.seek(0)
c_t = 0
for i in xrange(50000):
code = get_code(cfile, 128)
#print to_hex(code)
#print
t1 = time()
cs_lite(md, code)
c_t += time() - t1
print "Benchmark - lite:", c_t, "seconds"
print
except CsError as e:
print("ERROR: %s" %e)