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suite: update Mips modes of MC input to CS_MODE_MIPS32 & CS_MODE_MIPS64

This commit is contained in:
Nguyen Anh Quynh 2014-11-13 12:46:48 +08:00
parent ff9a5743d9
commit 02cafeb8bd
53 changed files with 68 additions and 64 deletions
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2
suite/MC/Mips/hilo-addressing.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x3c,0x04,0xde,0xae = lui $4, %hi(addr)
0x03,0xe0,0x00,0x08 = jr $31
0x80,0x82,0xbe,0xef = lb $2, %lo(addr)($4)

2
suite/MC/Mips/micromips-alu-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO, None
0x00,0xe6,0x49,0x10 = add $9, $6, $7
0x11,0x26,0x45,0x67 = addi $9, $6, 17767
0x31,0x26,0xc5,0x67 = addiu $9, $6, -15001

2
suite/MC/Mips/micromips-alu-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xe6,0x00,0x10,0x49 = add $9, $6, $7
0x26,0x11,0x67,0x45 = addi $9, $6, 17767
0x26,0x31,0x67,0xc5 = addiu $9, $6, -15001

2
suite/MC/Mips/micromips-branch-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x94,0x00,0x02,0x9a = b 1332
0x94,0xc9,0x02,0x9a = beq $9, $6, 1332
0x40,0x46,0x02,0x9a = bgez $6, 1332

2
suite/MC/Mips/micromips-branch-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x00,0x94,0x9a,0x02 = b 1332
0xc9,0x94,0x9a,0x02 = beq $9, $6, 1332
0x46,0x40,0x9a,0x02 = bgez $6, 1332

2
suite/MC/Mips/micromips-expansions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xa0,0x50,0x7b,0x00 = ori $5, $zero, 123
0xc0,0x30,0xd7,0xf6 = addiu $6, $zero, -2345
0xa7,0x41,0x01,0x00 = lui $7, 1

2
suite/MC/Mips/micromips-jump-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0xd4,0x00,0x02,0x98 = j 1328
0xf4,0x00,0x02,0x98 = jal 1328
0x03,0xe6,0x0f,0x3c = jalr $6

2
suite/MC/Mips/micromips-jump-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x00,0xd4,0x98,0x02 = j 1328
0x00,0xf4,0x98,0x02 = jal 1328
0xe6,0x03,0x3c,0x0f = jalr $6

2
suite/MC/Mips/micromips-loadstore-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x1c,0xa4,0x00,0x08 = lb $5, 8($4)
0x14,0xc4,0x00,0x08 = lbu $6, 8($4)
0x3c,0x44,0x00,0x08 = lh $2, 8($4)

2
suite/MC/Mips/micromips-loadstore-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xa4,0x1c,0x08,0x00 = lb $5, 8($4)
0xc4,0x14,0x08,0x00 = lbu $6, 8($4)
0x44,0x3c,0x08,0x00 = lh $2, 8($4)

2
suite/MC/Mips/micromips-loadstore-unaligned-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x60,0x85,0x00,0x10 = lwl $4, 16($5)
0x60,0x85,0x10,0x10 = lwr $4, 16($5)
0x60,0x85,0x80,0x10 = swl $4, 16($5)

2
suite/MC/Mips/micromips-loadstore-unaligned.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x85,0x60,0x10,0x00 = lwl $4, 16($5)
0x85,0x60,0x10,0x10 = lwr $4, 16($5)
0x85,0x60,0x10,0x80 = swl $4, 16($5)

2
suite/MC/Mips/micromips-movcond-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x00,0xe6,0x48,0x58 = movz $9, $6, $7
0x00,0xe6,0x48,0x18 = movn $9, $6, $7
0x55,0x26,0x09,0x7b = movt $9, $6, $fcc0

2
suite/MC/Mips/micromips-movcond-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xe6,0x00,0x58,0x48 = movz $9, $6, $7
0xe6,0x00,0x18,0x48 = movn $9, $6, $7
0x26,0x55,0x7b,0x09 = movt $9, $6, $fcc0

2
suite/MC/Mips/micromips-multiply-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x00,0xa4,0xcb,0x3c = madd $4, $5
0x00,0xa4,0xdb,0x3c = maddu $4, $5
0x00,0xa4,0xeb,0x3c = msub $4, $5

2
suite/MC/Mips/micromips-multiply-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0xa4,0x00,0x3c,0xcb = madd $4, $5
0xa4,0x00,0x3c,0xdb = maddu $4, $5
0xa4,0x00,0x3c,0xeb = msub $4, $5

2
suite/MC/Mips/micromips-shift-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x00,0x83,0x38,0x00 = sll $4, $3, 7
0x00,0x65,0x10,0x10 = sllv $2, $3, $5
0x00,0x83,0x38,0x80 = sra $4, $3, 7

2
suite/MC/Mips/micromips-shift-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x83,0x00,0x00,0x38 = sll $4, $3, 7
0x65,0x00,0x10,0x10 = sllv $2, $3, $5
0x83,0x00,0x80,0x38 = sra $4, $3, 7

2
suite/MC/Mips/micromips-trap-instructions-EB.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN, None
0x01,0x28,0x00,0x3c = teq $8, $9
0x01,0x28,0x02,0x3c = tge $8, $9
0x01,0x28,0x04,0x3c = tgeu $8, $9

2
suite/MC/Mips/micromips-trap-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_MICRO, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_MICRO, None
0x28,0x01,0x3c,0x00 = teq $8, $9
0x28,0x01,0x3c,0x02 = tge $8, $9
0x28,0x01,0x3c,0x04 = tgeu $8, $9

2
suite/MC/Mips/mips-alu-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x24,0x48,0xc7,0x00 = and $9, $6, $7
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767

2
suite/MC/Mips/mips-control-instructions-64.s.cs
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# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x00,0x00,0x00,0x0d = break
0x00,0x07,0x00,0x0d = break 7, 0
0x00,0x07,0x01,0x4d = break 7, 5

2
suite/MC/Mips/mips-control-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x00,0x00,0x00,0x0d = break
0x00,0x07,0x00,0x0d = break 7, 0
0x00,0x07,0x01,0x4d = break 7, 5

2
suite/MC/Mips/mips-coprocessor-encodings.s.cs
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# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x40,0xac,0x80,0x02 = dmtc0 $12, $16, 2
0x40,0xac,0x80,0x00 = dmtc0 $12, $16, 0
0x40,0x8c,0x80,0x02 = mtc0 $12, $16, 2

2
suite/MC/Mips/mips-dsp-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7e,0x32,0x83,0x11 = precrq.qb.ph $16, $17, $18
0x7e,0x53,0x8d,0x11 = precrq.ph.w $17, $18, $19
0x7e,0x74,0x95,0x51 = precrq_rs.ph.w $18, $19, $20

2
suite/MC/Mips/mips-expansions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x7b,0x00,0x05,0x34 = ori $5, $zero, 123
0xd7,0xf6,0x06,0x24 = addiu $6, $zero, -2345
0x01,0x00,0x07,0x3c = lui $7, 1

2
suite/MC/Mips/mips-fpu-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x05,0x73,0x20,0x46 = abs.d $f12, $f14
0x85,0x39,0x00,0x46 = abs.s $f6, $f7
0x00,0x62,0x2e,0x46 = add.d $f8, $f12, $f14

2
suite/MC/Mips/mips-jump-instructions.s.cs
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@ -1 +1 @@
# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None

2
suite/MC/Mips/mips-memory-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x10,0x00,0xa4,0xa0 = sb $4, 16($5)
0x10,0x00,0xa4,0xe0 = sc $4, 16($5)
0x10,0x00,0xa4,0xa4 = sh $4, 16($5)

2
suite/MC/Mips/mips-register-names.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x24,0x00,0x00,0x00 = addiu $zero, $zero, 0
0x24,0x01,0x00,0x00 = addiu $at, $zero, 0
0x24,0x02,0x00,0x00 = addiu $v0, $zero, 0

2
suite/MC/Mips/mips64-alu-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_64, None
# CS_ARCH_MIPS, CS_MODE_MIPS64, None
0x24,0x48,0xc7,0x00 = and $9, $6, $7
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767
0x67,0x45,0xc9,0x30 = andi $9, $6, 17767

2
suite/MC/Mips/mips64-instructions.s.cs
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# CS_ARCH_MIPS, CS_MODE_64, None
# CS_ARCH_MIPS, CS_MODE_MIPS64, None
0x81,0x00,0x42,0x4d = ldxc1 $f2, $2($10)
0x09,0x40,0x24,0x4f = sdxc1 $f8, $4($25)

2
suite/MC/Mips/mips64-register-names.s.cs
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# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x64,0x00,0x00,0x00 = daddiu $zero, $zero, 0
0x64,0x01,0x00,0x00 = daddiu $at, $zero, 0
0x64,0x02,0x00,0x00 = daddiu $v0, $zero, 0

2
suite/MC/Mips/mips_directives.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x10,0x00,0x01,0x4d = b 1332
0x08,0x00,0x01,0x4c = j 1328
0x0c,0x00,0x01,0x4c = jal 1328

2
suite/MC/Mips/nabi-regs.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_64+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN, None
0x02,0x04,0x80,0x20 = add $16, $16, $4
0x02,0x06,0x80,0x20 = add $16, $16, $6
0x02,0x07,0x80,0x20 = add $16, $16, $7

2
suite/MC/Mips/set-at-directive.s.cs
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# CS_ARCH_MIPS, CS_MODE_32, None
# CS_ARCH_MIPS, CS_MODE_MIPS32, None
0x08,0x00,0x60,0x00 = jr $3
0x08,0x00,0x80,0x03 = jr $gp
0x08,0x00,0xc0,0x03 = jr $fp

2
suite/MC/Mips/test_2r.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x00,0x4f,0x9e = fill.b $w30, $9
0x7b,0x01,0xbf,0xde = fill.h $w31, $23
0x7b,0x02,0xc4,0x1e = fill.w $w16, $24

2
suite/MC/Mips/test_2rf.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x20,0x66,0x9e = fclass.w $w26, $w12
0x7b,0x21,0x8e,0x1e = fclass.d $w24, $w17
0x7b,0x30,0x02,0x1e = fexupl.w $w8, $w0

2
suite/MC/Mips/test_3r.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x04,0x4e,0x90 = add_a.b $w26, $w9, $w4
0x78,0x3f,0xdd,0xd0 = add_a.h $w23, $w27, $w31
0x78,0x56,0x32,0xd0 = add_a.w $w11, $w6, $w22

2
suite/MC/Mips/test_3rf.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1c,0x9f,0x1b = fadd.w $w28, $w19, $w28
0x78,0x3d,0x13,0x5b = fadd.d $w13, $w2, $w29
0x78,0x19,0x5b,0x9a = fcaf.w $w14, $w11, $w25

2
suite/MC/Mips/test_bit.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0xf2,0xf5,0x49 = bclri.b $w21, $w30, 2
0x79,0xe0,0xae,0x09 = bclri.h $w24, $w21, 0
0x79,0xc3,0xf5,0xc9 = bclri.w $w23, $w30, 3

2
suite/MC/Mips/test_cbranch.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x47,0x80,0x00,0x01 = bnz.b $w0, 4
0x47,0xa1,0x00,0x04 = bnz.h $w1, 16
0x47,0xc2,0x00,0x20 = bnz.w $w2, 128

2
suite/MC/Mips/test_ctrlregs.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x7e,0x00,0x59 = cfcmsa $1, $0
0x78,0x7e,0x00,0x59 = cfcmsa $1, $0
0x78,0x7e,0x08,0x99 = cfcmsa $2, $1

2
suite/MC/Mips/test_elm.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x82,0x43,0x59 = copy_s.b $13, $w8[2]
0x78,0xa0,0xc8,0x59 = copy_s.h $1, $w25[0]
0x78,0xb1,0x2d,0x99 = copy_s.w $22, $w5[1]

2
suite/MC/Mips/test_elm_insert.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0x03,0xed,0xd9 = insert.b $w23[3], $sp
0x79,0x22,0x2d,0x19 = insert.h $w20[2], $5
0x79,0x32,0x7a,0x19 = insert.w $w8[2], $15

2
suite/MC/Mips/test_elm_insve.s.cs
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# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x79,0x43,0x4e,0x59 = insve.b $w25[3], $w9[0]
0x79,0x62,0x16,0x19 = insve.h $w24[2], $w2[0]
0x79,0x72,0x68,0x19 = insve.w $w0[2], $w13[0]

2
suite/MC/Mips/test_i10.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7b,0x06,0x32,0x07 = ldi.b $w8, 198
0x7b,0x29,0xcd,0x07 = ldi.h $w20, 313
0x7b,0x4f,0x66,0x07 = ldi.w $w24, 492

2
suite/MC/Mips/test_i5.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1e,0xf8,0xc6 = addvi.b $w3, $w31, 30
0x78,0x3a,0x6e,0x06 = addvi.h $w24, $w13, 26
0x78,0x5a,0xa6,0x86 = addvi.w $w26, $w20, 26

2
suite/MC/Mips/test_i8.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x30,0xe8,0x80 = andi.b $w2, $w29, 48
0x78,0x7e,0xb1,0x81 = bmnzi.b $w6, $w22, 126
0x79,0x58,0x0e,0xc1 = bmzi.b $w27, $w1, 88

2
suite/MC/Mips/test_lsa.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x01,0x2a,0x40,0x05 = lsa $8, $9, $10, 1
0x01,0x2a,0x40,0x45 = lsa $8, $9, $10, 2
0x01,0x2a,0x40,0x85 = lsa $8, $9, $10, 3

2
suite/MC/Mips/test_mi10.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x7a,0x00,0x08,0x20 = ld.b $w0, -512($1)
0x78,0x00,0x10,0x60 = ld.b $w1, 0($2)
0x79,0xff,0x18,0xa0 = ld.b $w2, 511($3)

2
suite/MC/Mips/test_vec.s.cs
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@ -1,4 +1,4 @@
# CS_ARCH_MIPS, CS_MODE_32+CS_MODE_BIG_ENDIAN, None
# CS_ARCH_MIPS, CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN, None
0x78,0x1b,0xa6,0x5e = and.v $w25, $w20, $w27
0x78,0x87,0x34,0x5e = bmnz.v $w17, $w6, $w7
0x78,0xa9,0x88,0xde = bmz.v $w3, $w17, $w9

28
suite/test_mc.py
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@ -97,6 +97,8 @@ def test_file(fname):
"CS_MODE_16": CS_MODE_16,
"CS_MODE_32": CS_MODE_32,
"CS_MODE_64": CS_MODE_64,
"CS_MODE_MIPS32": CS_MODE_MIPS32,
"CS_MODE_MIPS64": CS_MODE_MIPS64,
"0": CS_MODE_ARM,
"CS_MODE_ARM": CS_MODE_ARM,
"CS_MODE_THUMB": CS_MODE_THUMB,
@ -105,14 +107,16 @@ def test_file(fname):
"CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS,
"CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
"CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_BIG_ENDIAN": CS_MODE_32+CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_LITTLE_ENDIAN": CS_MODE_32+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_MICRO": CS_MODE_32+CS_MODE_MICRO,
"CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO,
"CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
"CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9,
"CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN,
"CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN,
"CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN,
}
options = {
@ -129,13 +133,13 @@ def test_file(fname):
("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'],
("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'],
("CS_ARCH_ARM64", "0"): ['-triple=aarch64'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_64"): ['-triple=mips64el'],
("CS_ARCH_MIPS", "CS_MODE_32"): ['-triple=mipsel'],
("CS_ARCH_MIPS", "CS_MODE_64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'],
("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'],
("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'],
('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'],
('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'],