From 04ac9c3725a0942fde03b36090e20097ecfb4843 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Tue, 31 Dec 2013 18:15:12 +0800 Subject: [PATCH] arm,arm64,mips,x86: rename PPC_getFeatureBits() to getFeatureBits() --- arch/AArch64/AArch64Disassembler.c | 2 +- arch/AArch64/AArch64GenDisassemblerTables.inc | 2 +- arch/ARM/ARMDisassembler.c | 5 +---- arch/ARM/ARMGenDisassemblerTables.inc | 2 +- arch/ARM/ARMInstPrinter.c | 22 +++++++++++++------ arch/Mips/MipsDisassembler.c | 2 +- arch/Mips/MipsGenDisassemblerTables.inc | 2 +- 7 files changed, 21 insertions(+), 16 deletions(-) diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c index 4b5eb70a..e7f3f4a7 100644 --- a/arch/AArch64/AArch64Disassembler.c +++ b/arch/AArch64/AArch64Disassembler.c @@ -212,7 +212,7 @@ static bool Check(DecodeStatus *Out, DecodeStatus In); #include "AArch64GenSubtargetInfo.inc" // Hacky: enable all features for disassembler -static uint64_t AArch64_getFeatureBits(void) +static uint64_t getFeatureBits(void) { // enable all features return -1; diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc index 910e95d5..2b6c9a6f 100644 --- a/arch/AArch64/AArch64GenDisassemblerTables.inc +++ b/arch/AArch64/AArch64GenDisassemblerTables.inc @@ -14036,7 +14036,7 @@ static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst *MI, MCRegisterInfo *MRI) { //uint64_t Bits = 0; - uint64_t Bits = AArch64_getFeatureBits(); + uint64_t Bits = getFeatureBits(); const uint8_t *Ptr = DecodeTable; uint32_t CurFieldValue = 0; diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index dd6ecd6a..404af31a 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -362,7 +362,7 @@ static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val, uint64_t Address, const void *Decoder); // Hacky: enable all features for disassembler -uint64_t ARM_getFeatureBits(int mode) +static uint64_t getFeatureBits(int mode) { uint64_t Bits = -1; // everything by default @@ -442,9 +442,6 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t ud->ITBlock.size = 0; - //assert(!(STI.getFeatureBits() & ARM_ModeThumb) && - // "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!"); - if (code_len < 4) return MCDisassembler_Fail; diff --git a/arch/ARM/ARMGenDisassemblerTables.inc b/arch/ARM/ARMGenDisassemblerTables.inc index 0bdaaae3..5aca5c17 100644 --- a/arch/ARM/ARMGenDisassemblerTables.inc +++ b/arch/ARM/ARMGenDisassemblerTables.inc @@ -13451,7 +13451,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \ InsnType insn, size_t Address, \ int feature) \ { \ - uint64_t Bits = ARM_getFeatureBits(feature); \ + uint64_t Bits = getFeatureBits(feature); \ const uint8_t *Ptr = DecodeTable; \ uint32_t CurFieldValue = 0; \ DecodeStatus S = MCDisassembler_Success; \ diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index daa5fdb0..0f88aec4 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -277,11 +277,15 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info) case 3: SStream_concat(O, "wfi"); break; case 4: SStream_concat(O, "sev"); break; case 5: - if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) { - SStream_concat(O, "sevl"); break; - break; - } + // FIXME: HasV80Ops becomes a mode + //if ((ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)) { + // SStream_concat(O, "sevl"); + // break; + //} // Fallthrough for non-v8 + + SStream_concat(O, "sevl"); + break; default: // Anything else should just print normally. printInstruction(MI, O, MRI); @@ -1121,8 +1125,10 @@ static void printBitfieldInvMaskImmOperand(MCInst *MI, unsigned OpNum, SStream * static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O) { unsigned val = MCOperand_getImm(MCInst_getOperand(MI, OpNum)); - SStream_concat(O, ARM_MB_MemBOptToString(val, - ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)); + // FIXME: HasV80Ops becomes a mode + // SStream_concat(O, ARM_MB_MemBOptToString(val, + // ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops)); + SStream_concat(O, ARM_MB_MemBOptToString(val, ARM_HasV8Ops)); } void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O) @@ -1269,7 +1275,9 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O) unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4; unsigned Mask = MCOperand_getImm(Op) & 0xf; - if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) { + // FIXME: FeatureMClass becomes mode?? + //if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) { + if (true) { unsigned SYSm = MCOperand_getImm(Op); unsigned Opcode = MCInst_getOpcode(MI); // For reads of the special registers ignore the "mask encoding" bits diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index ae2cdbe3..c7d9a5b6 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -151,7 +151,7 @@ static DecodeStatus DecodeExtSize(MCInst *Inst, #include "MipsGenSubtargetInfo.inc" // Hacky: enable all features for disassembler -static uint64_t Mips_getFeatureBits(int mode) +static uint64_t getFeatureBits(int mode) { uint64_t Bits = -1; // include every features by default diff --git a/arch/Mips/MipsGenDisassemblerTables.inc b/arch/Mips/MipsGenDisassemblerTables.inc index 84db7ef9..bba8de91 100644 --- a/arch/Mips/MipsGenDisassemblerTables.inc +++ b/arch/Mips/MipsGenDisassemblerTables.inc @@ -5313,7 +5313,7 @@ static DecodeStatus decodeToMCInst(DecodeStatus S, unsigned Idx, uint32_t insn, static DecodeStatus decodeInstruction(uint8_t DecodeTable[], MCInst *MI, uint32_t insn, uint64_t Address, MCRegisterInfo *MRI, int mode) { - uint64_t Bits = Mips_getFeatureBits(mode); + uint64_t Bits = getFeatureBits(mode); uint8_t *Ptr = DecodeTable; uint32_t CurFieldValue = 0; DecodeStatus S = MCDisassembler_Success;