diff --git a/bindings/python/test.py b/bindings/python/test.py
index e2efcc5f..b032cb5a 100755
--- a/bindings/python/test.py
+++ b/bindings/python/test.py
@@ -1,10 +1,13 @@
 #!/usr/bin/env python
-from __future__ import print_function
 # Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
 
+from __future__ import print_function
 from capstone import *
 import binascii
 import sys
+
+from xprint import to_hex, to_x, to_x_32
+
 _python3 = sys.version_info.major == 3
 
 
@@ -43,32 +46,6 @@ all_tests = (
 )
 
 
-def to_hex(s):
-    if _python3:
-        return " ".join("0x{0:02x}".format(c) for c in s)  # <-- Python 3 is OK
-    else:
-        return " ".join("0x{0:02x}".format(ord(c)) for c in s)
-
-def to_x(s):
-    from struct import pack
-    if not s: return '0'
-    x = pack(">q", s)
-    while x[0] in ('\0', 0): x = x[1:]
-    if _python3:
-        return "".join("{0:02x}".format(c) for c in x)  # <-- Python 3 is OK
-    else:
-        return "".join("{0:02x}".format(ord(c)) for c in x)
-
-def to_x_32(s):
-    from struct import pack
-    if not s: return '0'
-    x = pack(">i", s)
-    while x[0] in ('\0', 0): x = x[1:]
-    if _python3:
-        return "".join("{0:02x}".format(c) for c in x)  # <-- Python 3 is OK
-    else:
-        return "".join("{0:02x}".format(ord(c)) for c in x)
-
 # ## Test cs_disasm_quick()
 def test_cs_disasm_quick():
     for arch, mode, code, comment, syntax in all_tests:
diff --git a/bindings/python/test_arm.py b/bindings/python/test_arm.py
index afebfcf2..959b35e3 100755
--- a/bindings/python/test_arm.py
+++ b/bindings/python/test_arm.py
@@ -1,11 +1,12 @@
 #!/usr/bin/env python
-from __future__ import print_function
 
 # Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
 
+from __future__ import print_function
 from capstone import *
 from capstone.arm import *
-from test import to_hex, to_x, to_x_32
+from xprint import to_hex, to_x, to_x_32
+
 
 ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
 ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
@@ -19,56 +20,59 @@ all_tests = (
         (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2"),
         )
 
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = 0
+        for i in insn.operands:
+            if i.type == ARM_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == ARM_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
+            if i.type == ARM_OP_PIMM:
+                print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm))
+            if i.type == ARM_OP_CIMM:
+                print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
+            if i.type == ARM_OP_FP:
+                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
+            if i.type == ARM_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                        % (c, insn.reg_name(i.mem.base)))
+                if i.mem.index != 0:
+                    print("\t\t\toperands[%u].mem.index: REG = %s" \
+                        % (c, insn.reg_name(i.mem.index)))
+                if i.mem.scale != 1:
+                    print("\t\t\toperands[%u].mem.scale: %u" \
+                        % (c, i.mem.scale))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                        % (c, to_x_32(i.mem.disp)))
+
+            if i.shift.type != ARM_SFT_INVALID and i.shift.value:
+                print("\t\t\tShift: type = %u, value = %u\n" \
+                    % (i.shift.type, i.shift.value))
+            c += 1
+
+    if insn.update_flags:
+        print("\tUpdate-flags: True")
+    if insn.writeback:
+        print("\tWrite-back: True")
+    if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
+        print("\tCode condition: %u" % insn.cc)
+
+
 # ## Test class Cs
 def test_class():
-    def print_insn_detail(insn):
-        # print address, mnemonic and operands
-        print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-        # "data" instruction generated by SKIPDATA option has no detail
-        if insn.id == 0:
-            return
-
-        if len(insn.operands) > 0:
-            print("\top_count: %u" % len(insn.operands))
-            c = 0
-            for i in insn.operands:
-                if i.type == ARM_OP_REG:
-                    print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-                if i.type == ARM_OP_IMM:
-                    print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
-                if i.type == ARM_OP_PIMM:
-                    print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm))
-                if i.type == ARM_OP_CIMM:
-                    print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
-                if i.type == ARM_OP_FP:
-                    print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
-                if i.type == ARM_OP_MEM:
-                    print("\t\toperands[%u].type: MEM" % c)
-                    if i.mem.base != 0:
-                        print("\t\t\toperands[%u].mem.base: REG = %s" \
-                            % (c, insn.reg_name(i.mem.base)))
-                    if i.mem.index != 0:
-                        print("\t\t\toperands[%u].mem.index: REG = %s" \
-                            % (c, insn.reg_name(i.mem.index)))
-                    if i.mem.scale != 1:
-                        print("\t\t\toperands[%u].mem.scale: %u" \
-                            % (c, i.mem.scale))
-                    if i.mem.disp != 0:
-                        print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                            % (c, to_x_32(i.mem.disp)))
-
-                if i.shift.type != ARM_SFT_INVALID and i.shift.value:
-                    print("\t\t\tShift: type = %u, value = %u\n" \
-                        % (i.shift.type, i.shift.value))
-                c += 1
-
-        if insn.update_flags:
-            print("\tUpdate-flags: True")
-        if insn.writeback:
-            print("\tWrite-back: True")
-        if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
-            print("\tCode condition: %u" % insn.cc)
 
     for (arch, mode, code, comment) in all_tests:
         print("*" * 16)
@@ -86,5 +90,6 @@ def test_class():
         except CsError as e:
             print("ERROR: %s" % e)
 
+
 if __name__ == '__main__':
     test_class()
diff --git a/bindings/python/test_arm64.py b/bindings/python/test_arm64.py
index 651055b6..5add698d 100755
--- a/bindings/python/test_arm64.py
+++ b/bindings/python/test_arm64.py
@@ -1,63 +1,69 @@
 #!/usr/bin/env python
 
 # Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
 from __future__ import print_function
 from capstone import *
 from capstone.arm64 import *
-from test import to_hex, to_x
+from xprint import to_hex, to_x
+
+
 ARM64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b"
 
 all_tests = (
         (CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
         )
 
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = -1
+        for i in insn.operands:
+            c += 1
+            if i.type == ARM64_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == ARM64_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
+            if i.type == ARM64_OP_CIMM:
+                print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
+            if i.type == ARM64_OP_FP:
+                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
+            if i.type == ARM64_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                        % (c, insn.reg_name(i.mem.base)))
+                if i.mem.index != 0:
+                    print("\t\t\toperands[%u].mem.index: REG = %s" \
+                        % (c, insn.reg_name(i.mem.index)))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                        % (c, to_x(i.mem.disp)))
+
+            if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
+                print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
+
+            if i.ext != ARM64_EXT_INVALID:
+                print("\t\t\tExt: %u" % i.ext)
+
+    if insn.writeback:
+        print("\tWrite-back: True")
+    if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
+        print("\tCode condition: %u" % insn.cc)
+    if insn.update_flags:
+        print("\tUpdate-flags: True")
+
+
 # ## Test class Cs
 def test_class():
-    def print_insn_detail(insn):
-        # print address, mnemonic and operands
-        print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-        # "data" instruction generated by SKIPDATA option has no detail
-        if insn.id == 0:
-            return
-
-        if len(insn.operands) > 0:
-            print("\top_count: %u" % len(insn.operands))
-            c = -1
-            for i in insn.operands:
-                c += 1
-                if i.type == ARM64_OP_REG:
-                    print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-                if i.type == ARM64_OP_IMM:
-                    print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-                if i.type == ARM64_OP_CIMM:
-                    print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
-                if i.type == ARM64_OP_FP:
-                    print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
-                if i.type == ARM64_OP_MEM:
-                    print("\t\toperands[%u].type: MEM" % c)
-                    if i.mem.base != 0:
-                        print("\t\t\toperands[%u].mem.base: REG = %s" \
-                            % (c, insn.reg_name(i.mem.base)))
-                    if i.mem.index != 0:
-                        print("\t\t\toperands[%u].mem.index: REG = %s" \
-                            % (c, insn.reg_name(i.mem.index)))
-                    if i.mem.disp != 0:
-                        print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                            % (c, to_x(i.mem.disp)))
-
-                if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
-                    print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
-
-                if i.ext != ARM64_EXT_INVALID:
-                    print("\t\t\tExt: %u" % i.ext)
-
-        if insn.writeback:
-            print("\tWrite-back: True")
-        if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
-            print("\tCode condition: %u" % insn.cc)
-        if insn.update_flags:
-            print("\tUpdate-flags: True")
 
     for (arch, mode, code, comment) in all_tests:
         print("*" * 16)
@@ -75,5 +81,6 @@ def test_class():
         except CsError as e:
             print("ERROR: %s" % e)
 
+
 if __name__ == '__main__':
     test_class()
diff --git a/bindings/python/test_detail.py b/bindings/python/test_detail.py
index 04b8e732..2844399d 100755
--- a/bindings/python/test_detail.py
+++ b/bindings/python/test_detail.py
@@ -4,6 +4,7 @@
 from __future__ import print_function
 from capstone import *
 
+
 X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
 X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
 X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
diff --git a/bindings/python/test_lite.py b/bindings/python/test_lite.py
index 490f7757..0e04262f 100755
--- a/bindings/python/test_lite.py
+++ b/bindings/python/test_lite.py
@@ -4,7 +4,8 @@
 from __future__ import print_function
 from capstone import *
 import binascii
-from test import to_hex
+from xprint import to_hex
+
 
 X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
 X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
diff --git a/bindings/python/test_mips.py b/bindings/python/test_mips.py
index ec1f1a30..6c32caab 100755
--- a/bindings/python/test_mips.py
+++ b/bindings/python/test_mips.py
@@ -4,7 +4,8 @@
 from __future__ import print_function
 from capstone import *
 from capstone.mips import *
-from test import to_hex, to_x
+from xprint import to_hex, to_x
+
 
 MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
 MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
@@ -14,35 +15,36 @@ all_tests = (
         (CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
 )
 
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = -1
+        for i in insn.operands:
+            c += 1
+            if i.type == MIPS_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == MIPS_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
+            if i.type == MIPS_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                        % (c, insn.reg_name(i.mem.base)))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                        % (c, to_x(i.mem.disp)))
+
+
 # ## Test class Cs
 def test_class():
-    def print_insn_detail(insn):
-        # print address, mnemonic and operands
-        print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-        # "data" instruction generated by SKIPDATA option has no detail
-        if insn.id == 0:
-            return
-
-        if len(insn.operands) > 0:
-            print("\top_count: %u" % len(insn.operands))
-            c = -1
-            for i in insn.operands:
-                c += 1
-                if i.type == MIPS_OP_REG:
-                    print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-                if i.type == MIPS_OP_IMM:
-                    print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-                if i.type == MIPS_OP_MEM:
-                    print("\t\toperands[%u].type: MEM" % c)
-                    if i.mem.base != 0:
-                        print("\t\t\toperands[%u].mem.base: REG = %s" \
-                            % (c, insn.reg_name(i.mem.base)))
-                    if i.mem.disp != 0:
-                        print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                            % (c, to_x(i.mem.disp)))
-
-
     for (arch, mode, code, comment) in all_tests:
         print("*" * 16)
         print("Platform: %s" % comment)
diff --git a/bindings/python/test_ppc.py b/bindings/python/test_ppc.py
index cb005b84..bdfd5ccd 100755
--- a/bindings/python/test_ppc.py
+++ b/bindings/python/test_ppc.py
@@ -4,47 +4,50 @@
 from __future__ import print_function
 from capstone import *
 from capstone.ppc import *
-from test import to_x, to_hex, to_x_32
+from xprint import to_x, to_hex, to_x_32
 PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
 
 all_tests = (
         (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64"),
         )
 
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = 0
+        for i in insn.operands:
+            if i.type == PPC_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == PPC_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
+            if i.type == PPC_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                        % (c, insn.reg_name(i.mem.base)))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                        % (c, to_x_32(i.mem.disp)))
+            c += 1
+
+    if insn.bc:
+        print("\tBranch code: %u" % insn.bc)
+    if insn.bh:
+        print("\tBranch hint: %u" % insn.bh)
+    if insn.update_cr0:
+        print("\tUpdate-CR0: True")
+
+
 # ## Test class Cs
 def test_class():
-    def print_insn_detail(insn):
-        # print address, mnemonic and operands
-        print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-        # "data" instruction generated by SKIPDATA option has no detail
-        if insn.id == 0:
-            return
-
-        if len(insn.operands) > 0:
-            print("\top_count: %u" % len(insn.operands))
-            c = 0
-            for i in insn.operands:
-                if i.type == PPC_OP_REG:
-                    print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-                if i.type == PPC_OP_IMM:
-                    print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
-                if i.type == PPC_OP_MEM:
-                    print("\t\toperands[%u].type: MEM" % c)
-                    if i.mem.base != 0:
-                        print("\t\t\toperands[%u].mem.base: REG = %s" \
-                            % (c, insn.reg_name(i.mem.base)))
-                    if i.mem.disp != 0:
-                        print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                            % (c, to_x_32(i.mem.disp)))
-                c += 1
-
-        if insn.bc:
-            print("\tBranch code: %u" % insn.bc)
-        if insn.bh:
-            print("\tBranch hint: %u" % insn.bh)
-        if insn.update_cr0:
-            print("\tUpdate-CR0: True")
 
     for (arch, mode, code, comment) in all_tests:
         print("*" * 16)
diff --git a/bindings/python/test_skipdata.py b/bindings/python/test_skipdata.py
index 1f2803ae..dff6c8ba 100755
--- a/bindings/python/test_skipdata.py
+++ b/bindings/python/test_skipdata.py
@@ -5,8 +5,8 @@
 from __future__ import print_function
 from capstone import *
 import binascii
+from xprint import to_x, to_hex, to_x_32
 
-from test import to_x, to_hex, to_x_32
 
 X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x00\x91\x92"
 RANDOM_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
diff --git a/bindings/python/test_sparc.py b/bindings/python/test_sparc.py
index 57889161..d7d6b551 100755
--- a/bindings/python/test_sparc.py
+++ b/bindings/python/test_sparc.py
@@ -5,8 +5,8 @@
 from __future__ import print_function
 from capstone import *
 from capstone.sparc import *
+from xprint import to_x, to_hex, to_x_32
 
-from test import to_x, to_hex, to_x_32
 
 SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
 SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
@@ -16,38 +16,41 @@ all_tests = (
         (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN+CS_MODE_V9, SPARCV9_CODE, "SparcV9"),
 )
 
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = 0
+        for i in insn.operands:
+            if i.type == SPARC_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == SPARC_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
+            if i.type == SPARC_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                        % (c, insn.reg_name(i.mem.base)))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                        % (c, to_x_32(i.mem.disp)))
+            c += 1
+
+    if insn.cc:
+        print("\tConditional code: %u" % insn.cc)
+    if insn.hint:
+        print("\tBranch hint: %u" % insn.hint)
+
+
 # ## Test class Cs
 def test_class():
-    def print_insn_detail(insn):
-        # print address, mnemonic and operands
-        print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-        # "data" instruction generated by SKIPDATA option has no detail
-        if insn.id == 0:
-            return
-
-        if len(insn.operands) > 0:
-            print("\top_count: %u" % len(insn.operands))
-            c = 0
-            for i in insn.operands:
-                if i.type == SPARC_OP_REG:
-                    print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-                if i.type == SPARC_OP_IMM:
-                    print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
-                if i.type == SPARC_OP_MEM:
-                    print("\t\toperands[%u].type: MEM" % c)
-                    if i.mem.base != 0:
-                        print("\t\t\toperands[%u].mem.base: REG = %s" \
-                            % (c, insn.reg_name(i.mem.base)))
-                    if i.mem.disp != 0:
-                        print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                            % (c, to_x_32(i.mem.disp)))
-                c += 1
-
-        if insn.cc:
-            print("\tConditional code: %u" % insn.cc)
-        if insn.hint:
-            print("\tBranch hint: %u" % insn.hint)
 
     for (arch, mode, code, comment) in all_tests:
         print("*" * 16)
diff --git a/bindings/python/test_systemz.py b/bindings/python/test_systemz.py
index 07158804..7eb238b3 100755
--- a/bindings/python/test_systemz.py
+++ b/bindings/python/test_systemz.py
@@ -5,8 +5,8 @@
 from __future__ import print_function
 from capstone import *
 from capstone.systemz import *
+from xprint import to_x, to_hex, to_x_32
 
-from test import to_x, to_hex, to_x_32
 
 SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
 
@@ -14,44 +14,47 @@ all_tests = (
         (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ"),
 )
 
+
+def print_insn_detail(insn):
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
+
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = 0
+        for i in insn.operands:
+            if i.type == SYSZ_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == SYSZ_OP_ACREG:
+                print("\t\toperands[%u].type: ACREG = %u" % (c, i.reg))
+            if i.type == SYSZ_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
+            if i.type == SYSZ_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" \
+                        % (c, insn.reg_name(i.mem.base)))
+                if i.mem.index != 0:
+                    print("\t\t\toperands[%u].mem.index: REG = %s" \
+                        % (c, insn.reg_name(i.mem.index)))
+                if i.mem.length != 0:
+                    print("\t\t\toperands[%u].mem.length: 0x%s" \
+                        % (c, to_x(i.mem.length)))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
+                        % (c, to_x(i.mem.disp)))
+            c += 1
+
+    if insn.cc:
+        print("\tConditional code: %u" % insn.cc)
+
+
 # ## Test class Cs
 def test_class():
-    def print_insn_detail(insn):
-        # print address, mnemonic and operands
-        print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-        # "data" instruction generated by SKIPDATA option has no detail
-        if insn.id == 0:
-            return
-
-        if len(insn.operands) > 0:
-            print("\top_count: %u" % len(insn.operands))
-            c = 0
-            for i in insn.operands:
-                if i.type == SYSZ_OP_REG:
-                    print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-                if i.type == SYSZ_OP_ACREG:
-                    print("\t\toperands[%u].type: ACREG = %u" % (c, i.reg))
-                if i.type == SYSZ_OP_IMM:
-                    print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-                if i.type == SYSZ_OP_MEM:
-                    print("\t\toperands[%u].type: MEM" % c)
-                    if i.mem.base != 0:
-                        print("\t\t\toperands[%u].mem.base: REG = %s" \
-                            % (c, insn.reg_name(i.mem.base)))
-                    if i.mem.index != 0:
-                        print("\t\t\toperands[%u].mem.index: REG = %s" \
-                            % (c, insn.reg_name(i.mem.index)))
-                    if i.mem.length != 0:
-                        print("\t\t\toperands[%u].mem.length: 0x%s" \
-                            % (c, to_x(i.mem.length)))
-                    if i.mem.disp != 0:
-                        print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                            % (c, to_x(i.mem.disp)))
-                c += 1
-
-        if insn.cc:
-            print("\tConditional code: %u" % insn.cc)
 
     for (arch, mode, code, comment) in all_tests:
         print("*" * 16)
diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py
index 5e0f663c..ed6da463 100755
--- a/bindings/python/test_x86.py
+++ b/bindings/python/test_x86.py
@@ -4,7 +4,8 @@
 from __future__ import print_function
 from capstone import *
 from capstone.x86 import *
-from test import to_hex, to_x, to_x_32
+from xprint import to_hex, to_x, to_x_32
+
 
 X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
 X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
@@ -17,79 +18,81 @@ all_tests = (
         (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", 0),
         )
 
-# ## Test class Cs
-def test_class():
+
+def print_insn_detail(mode, insn):
     def print_string_hex(comment, str):
         print(comment, end=' '),
         for c in str:
             print("0x%02x" % c, end=''),
         print()
 
-    def print_insn_detail(mode, insn):
-        # print address, mnemonic and operands
-        print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
+    # print address, mnemonic and operands
+    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
 
-        # "data" instruction generated by SKIPDATA option has no detail
-        if insn.id == 0:
-            return
+    # "data" instruction generated by SKIPDATA option has no detail
+    if insn.id == 0:
+        return
 
-        # print instruction prefix
-        print_string_hex("\tPrefix:", insn.prefix)
+    # print instruction prefix
+    print_string_hex("\tPrefix:", insn.prefix)
 
-        # print segment override (if applicable)
-        if insn.segment != X86_REG_INVALID:
-            print("\tSegment override: %s" % insn.reg_name(insn.segment))
+    # print segment override (if applicable)
+    if insn.segment != X86_REG_INVALID:
+        print("\tSegment override: %s" % insn.reg_name(insn.segment))
 
-        # print instruction's opcode
-        print_string_hex("\tOpcode:", insn.opcode)
+    # print instruction's opcode
+    print_string_hex("\tOpcode:", insn.opcode)
 
-        # print operand's size, address size, displacement size & immediate size
-        print("\top_size: %u, addr_size: %u, disp_size: %u, imm_size: %u" \
-            % (insn.op_size, insn.addr_size, insn.disp_size, insn.imm_size))
+    # print operand's size, address size, displacement size & immediate size
+    print("\top_size: %u, addr_size: %u, disp_size: %u, imm_size: %u" \
+        % (insn.op_size, insn.addr_size, insn.disp_size, insn.imm_size))
 
-        # print modRM byte
-        print("\tmodrm: 0x%x" % (insn.modrm))
+    # print modRM byte
+    print("\tmodrm: 0x%x" % (insn.modrm))
 
-        # print displacement value
-        print("\tdisp: 0x%s" % to_x_32(insn.disp))
+    # print displacement value
+    print("\tdisp: 0x%s" % to_x_32(insn.disp))
 
-        # SIB is not available in 16-bit mode
-        if (mode & CS_MODE_16 == 0):
-            # print SIB byte
-            print("\tsib: 0x%x" % (insn.sib))
-            if (insn.sib):
-                print("\tsib_index: %s, sib_scale: %d, sib_base: %s" % (insn.reg_name(insn.sib_index), insn.sib_scale, insn.reg_name(insn.sib_base)))
+    # SIB is not available in 16-bit mode
+    if (mode & CS_MODE_16 == 0):
+        # print SIB byte
+        print("\tsib: 0x%x" % (insn.sib))
+        if (insn.sib):
+            print("\tsib_index: %s, sib_scale: %d, sib_base: %s" % (insn.reg_name(insn.sib_index), insn.sib_scale, insn.reg_name(insn.sib_base)))
 
-        count = insn.op_count(X86_OP_IMM)
-        if count > 0:
-            print("\timm_count: %u" % count)
-            for i in range(count):
-                op = insn.op_find(X86_OP_IMM, i + 1)
-                print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm)))
+    count = insn.op_count(X86_OP_IMM)
+    if count > 0:
+        print("\timm_count: %u" % count)
+        for i in range(count):
+            op = insn.op_find(X86_OP_IMM, i + 1)
+            print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm)))
 
-        if len(insn.operands) > 0:
-            print("\top_count: %u" % len(insn.operands))
-            c = -1
-            for i in insn.operands:
-                c += 1
-                if i.type == X86_OP_REG:
-                    print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-                if i.type == X86_OP_IMM:
-                    print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-                if i.type == X86_OP_FP:
-                    print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
-                if i.type == X86_OP_MEM:
-                    print("\t\toperands[%u].type: MEM" % c)
-                    if i.mem.base != 0:
-                        print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base)))
-                    if i.mem.index != 0:
-                        print("\t\t\toperands[%u].mem.index: REG = %s" % (c, insn.reg_name(i.mem.index)))
-                    if i.mem.scale != 1:
-                        print("\t\t\toperands[%u].mem.scale: %u" % (c, i.mem.scale))
-                    if i.mem.disp != 0:
-                        print("\t\t\toperands[%u].mem.disp: 0x%s" % (c, to_x(i.mem.disp)))
+    if len(insn.operands) > 0:
+        print("\top_count: %u" % len(insn.operands))
+        c = -1
+        for i in insn.operands:
+            c += 1
+            if i.type == X86_OP_REG:
+                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
+            if i.type == X86_OP_IMM:
+                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
+            if i.type == X86_OP_FP:
+                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
+            if i.type == X86_OP_MEM:
+                print("\t\toperands[%u].type: MEM" % c)
+                if i.mem.base != 0:
+                    print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base)))
+                if i.mem.index != 0:
+                    print("\t\t\toperands[%u].mem.index: REG = %s" % (c, insn.reg_name(i.mem.index)))
+                if i.mem.scale != 1:
+                    print("\t\t\toperands[%u].mem.scale: %u" % (c, i.mem.scale))
+                if i.mem.disp != 0:
+                    print("\t\t\toperands[%u].mem.disp: 0x%s" % (c, to_x(i.mem.disp)))
 
 
+# ## Test class Cs
+def test_class():
+
     for (arch, mode, code, comment, syntax) in all_tests:
         print("*" * 16)
         print("Platform: %s" % comment)
diff --git a/bindings/python/xprint.py b/bindings/python/xprint.py
new file mode 100755
index 00000000..243d66d6
--- /dev/null
+++ b/bindings/python/xprint.py
@@ -0,0 +1,35 @@
+#!/usr/bin/env python
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+from __future__ import print_function
+import sys
+_python3 = sys.version_info.major == 3
+
+
+def to_hex(s):
+    if _python3:
+        return " ".join("0x{0:02x}".format(c) for c in s)  # <-- Python 3 is OK
+    else:
+        return " ".join("0x{0:02x}".format(ord(c)) for c in s)
+
+
+def to_x(s):
+    from struct import pack
+    if not s: return '0'
+    x = pack(">q", s)
+    while x[0] in ('\0', 0): x = x[1:]
+    if _python3:
+        return "".join("{0:02x}".format(c) for c in x)  # <-- Python 3 is OK
+    else:
+        return "".join("{0:02x}".format(ord(c)) for c in x)
+
+
+def to_x_32(s):
+    from struct import pack
+    if not s: return '0'
+    x = pack(">i", s)
+    while x[0] in ('\0', 0): x = x[1:]
+    if _python3:
+        return "".join("{0:02x}".format(c) for c in x)  # <-- Python 3 is OK
+    else:
+        return "".join("{0:02x}".format(ord(c)) for c in x)