arm: sync with llvm 7.0.1
This commit is contained in:
Nguyen Anh Quynh
parent
5fc297fe09
commit
124f91b303
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@ -28,8 +28,8 @@ option(CAPSTONE_BUILD_TESTS "Build tests" ON)
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option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON)
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option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
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set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM RISCV MOS65XX WASM BPF)
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set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM RISCV MOS65XX WASM BPF)
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set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF)
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set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF)
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list(LENGTH SUPPORTED_ARCHITECTURES count)
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math(EXPR count "${count}-1")
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@ -111,7 +111,6 @@ set(HEADERS_COMMON
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include/capstone/sparc.h
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include/capstone/systemz.h
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include/capstone/xcore.h
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include/capstone/riscv.h
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include/capstone/m68k.h
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include/capstone/tms320c64x.h
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include/capstone/m680x.h
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@ -135,27 +134,20 @@ if (NOT CAPSTONE_X86_ONLY AND CAPSTONE_ARM_SUPPORT)
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arch/ARM/ARMAddressingModes.h
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arch/ARM/ARMBaseInfo.h
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arch/ARM/ARMDisassembler.h
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arch/ARM/ARMInstPrinter.h
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arch/ARM/ARMMapping.h
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arch/ARM/ARMGenAsmWriter.inc
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arch/ARM/ARMGenDisassemblerTables.inc
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arch/ARM/ARMGenInstrInfo.inc
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arch/ARM/ARMGenRegisterInfo.inc
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arch/ARM/ARMGenSubtargetInfo.inc
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arch/ARM/ARMInstPrinter.h
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arch/ARM/ARMMapping.h
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arch/ARM/ARMMappingInsn.inc
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arch/ARM/ARMMappingInsnOp.inc
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)
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set(HEADERS_ARM
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arch/ARM/ARMAddressingModes.h
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arch/ARM/ARMBaseInfo.h
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arch/ARM/ARMDisassembler.h
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arch/ARM/ARMGenAsmWriter.inc
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arch/ARM/ARMGenDisassemblerTables.inc
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arch/ARM/ARMGenInstrInfo.inc
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arch/ARM/ARMGenRegisterInfo.inc
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arch/ARM/ARMGenSubtargetInfo.inc
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arch/ARM/ARMInstPrinter.h
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arch/ARM/ARMMapping.h
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arch/ARM/ARMGenRegisterName.inc
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arch/ARM/ARMGenRegisterName_digit.inc
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arch/ARM/ARMGenSystemRegister.inc
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arch/ARM/ARMMappingInsnName.inc
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arch/ARM/ARMRegisterName.inc
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)
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set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
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endif ()
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@ -278,31 +270,38 @@ if (CAPSTONE_X86_SUPPORT)
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arch/X86/X86Disassembler.h
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arch/X86/X86DisassemblerDecoder.h
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arch/X86/X86DisassemblerDecoderCommon.h
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arch/X86/X86InstPrinter.h
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arch/X86/X86Mapping.h
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arch/X86/X86GenAsmWriter.inc
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arch/X86/X86GenAsmWriter_reduce.inc
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arch/X86/X86GenAsmWriter1.inc
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arch/X86/X86GenAsmWriter1_reduce.inc
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arch/X86/X86GenAsmWriter_reduce.inc
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arch/X86/X86GenDisassemblerTables.inc
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arch/X86/X86GenDisassemblerTables_reduce.inc
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arch/X86/X86GenDisassemblerTables2.inc
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arch/X86/X86GenDisassemblerTables_reduce2.inc
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arch/X86/X86GenInstrInfo.inc
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arch/X86/X86GenInstrInfo_reduce.inc
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arch/X86/X86GenRegisterInfo.inc
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arch/X86/X86GenRegisterName.inc
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arch/X86/X86GenRegisterName1.inc
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arch/X86/X86InstPrinter.h
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arch/X86/X86Mapping.h
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arch/X86/X86MappingInsn.inc
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arch/X86/X86MappingInsn_reduce.inc
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arch/X86/X86MappingInsnOp.inc
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arch/X86/X86MappingInsnOp_reduce.inc
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arch/X86/X86MappingReg.inc
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arch/X86/X86MappingInsnName.inc
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arch/X86/X86MappingInsnName_reduce.inc
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arch/X86/X86Lookup16.inc
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arch/X86/X86Lookup16_reduce.inc
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arch/X86/X86ImmSize.inc
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arch/X86/X86MappingInsn_reduce.inc
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)
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set(HEADERS_X86
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arch/X86/X86BaseInfo.h
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arch/X86/X86Disassembler.h
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arch/X86/X86DisassemblerDecoder.h
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arch/X86/X86DisassemblerDecoderCommon.h
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arch/X86/X86GenAsmWriter.inc
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arch/X86/X86GenAsmWriter1.inc
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arch/X86/X86GenAsmWriter1_reduce.inc
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arch/X86/X86GenAsmWriter_reduce.inc
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arch/X86/X86GenDisassemblerTables.inc
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arch/X86/X86GenDisassemblerTables_reduce.inc
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arch/X86/X86GenInstrInfo.inc
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arch/X86/X86GenInstrInfo_reduce.inc
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arch/X86/X86GenRegisterInfo.inc
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arch/X86/X86InstPrinter.h
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arch/X86/X86Mapping.h
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)
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if (NOT CAPSTONE_BUILD_DIET)
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set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
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@ -444,31 +443,6 @@ if (NOT CAPSTONE_X86_ONLY AND CAPSTONE_EVM_SUPPORT)
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set(TEST_SOURCES ${TEST_SOURCES} test_evm.c)
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endif ()
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if (NOT CAPSTONE_X86_ONLY AND CAPSTONE_RISCV_SUPPORT)
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add_definitions(-DCAPSTONE_HAS_RISCV)
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set(SOURCES_RISCV
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arch/RISCV/RISCVDisassembler.c
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arch/RISCV/RISCVInstPrinter.c
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arch/RISCV/RISCVMapping.c
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arch/RISCV/RISCVModule.c
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)
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set(HEADERS_RISCV
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arch/RISCV/RISCVBaseInfo.h
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arch/RISCV/RISCVDisassembler.h
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arch/RISCV/RISCVGenAsmWriter.inc
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arch/RISCV/RISCVGenDisassemblerTables.inc
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arch/RISCV/RISCVGenInsnNameMaps.inc
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arch/RISCV/RISCVGenInstrInfo.inc
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arch/RISCV/RISCVGenRegisterInfo.inc
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arch/RISCV/RISCVGenSubtargetInfo.inc
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arch/RISCV/RISCVInstPrinter.h
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arch/RISCV/RISCVMapping.h
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arch/RISCV/RISCVModule.h
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arch/RISCV/RISCVMappingInsn.inc
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)
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set(TEST_SOURCES ${TEST_SOURCES} test_riscv.c)
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endif ()
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if (NOT CAPSTONE_X86_ONLY AND CAPSTONE_WASM_SUPPORT)
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add_definitions(-DCAPSTONE_HAS_WASM)
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set(SOURCES_WASM
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@ -532,7 +506,6 @@ set(ALL_SOURCES
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${SOURCES_TMS320C64X}
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${SOURCES_M680X}
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${SOURCES_EVM}
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${SOURCES_RISCV}
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${SOURCES_WASM}
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${SOURCES_MOS65XX}
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${SOURCES_BPF}
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@ -553,7 +526,6 @@ set(ALL_HEADERS
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${HEADERS_TMS320C64X}
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${HEADERS_M680X}
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${HEADERS_EVM}
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${HEADERS_RISCV}
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${HEADERS_WASM}
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${HEADERS_MOS65XX}
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${HEADERS_BPF}
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@ -637,10 +609,10 @@ source_group("Source\\M68K" FILES ${SOURCES_M68K})
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source_group("Source\\TMS320C64x" FILES ${SOURCES_TMS320C64X})
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source_group("Source\\M680X" FILES ${SOURCES_M680X})
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source_group("Source\\EVM" FILES ${SOURCES_EVM})
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source_group("Source\\RISCV" FILES ${SOURCES_RISCV})
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source_group("Source\\WASM" FILES ${SOURCES_WASM})
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source_group("Source\\MOS65XX" FILES ${SOURCES_MOS65XX})
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source_group("Source\\BPF" FILES ${SOURCES_BPF})
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source_group("Include\\Common" FILES ${HEADERS_COMMON})
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source_group("Include\\Engine" FILES ${HEADERS_ENGINE})
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source_group("Include\\ARM" FILES ${HEADERS_ARM})
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@ -655,7 +627,6 @@ source_group("Include\\M68K" FILES ${HEADERS_M68K})
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source_group("Include\\TMS320C64x" FILES ${HEADERS_TMS320C64X})
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source_group("Include\\M680X" FILES ${HEADERS_MC680X})
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source_group("Include\\EVM" FILES ${HEADERS_EVM})
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source_group("Include\\RISCV" FILES ${HEADERS_RISCV})
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source_group("Include\\WASM" FILES ${HEADERS_WASM})
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source_group("Include\\MOS65XX" FILES ${HEADERS_MOS65XX})
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source_group("Include\\BPF" FILES ${HEADERS_BPF})
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2
MCInst.h
2
MCInst.h
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@ -20,6 +20,7 @@
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#define CS_MCINST_H
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#include "include/capstone/capstone.h"
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#include "MCRegisterInfo.h"
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typedef struct MCInst MCInst;
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typedef struct cs_struct cs_struct;
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@ -114,6 +115,7 @@ struct MCInst {
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char assembly[8]; // for special instruction, so that we dont need printer
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unsigned char evm_data[32]; // for EVM PUSH operand
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cs_wasm_op wasm_data; // for WASM operand
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MCRegisterInfo *MRI;
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};
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void MCInst_Init(MCInst *inst);
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@ -12,7 +12,7 @@
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
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#define CS_LLVM_TARGET_ARM_ARMADDRESSINGMODES_H
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@ -555,6 +555,34 @@ static inline ARM_AM_AddrOpc ARM_AM_getAM5Op(unsigned AM5Opc)
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return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #5 FP16
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//===--------------------------------------------------------------------===//
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//
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// This is used for coprocessor instructions, such as 16-bit FP load/stores.
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//
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// addrmode5fp16 := reg +/- imm8*2
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//
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// The first operand is always a Reg. The second operand encodes the
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// operation (add or subtract) in bit 8 and the immediate in bits 0-7.
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/// getAM5FP16Opc - This function encodes the addrmode5fp16 opc field.
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static inline unsigned getAM5FP16Opc(ARM_AM_AddrOpc Opc, unsigned char Offset)
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{
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bool isSub = Opc == ARM_AM_sub;
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return ((int)isSub << 8) | Offset;
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}
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static inline unsigned char getAM5FP16Offset(unsigned AM5Opc)
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{
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return AM5Opc & 0xFF;
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}
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static inline ARM_AM_AddrOpc getAM5FP16Op(unsigned AM5Opc)
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{
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return ((AM5Opc >> 8) & 1) ? ARM_AM_sub : ARM_AM_add;
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}
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//===--------------------------------------------------------------------===//
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// Addressing Mode #6
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//===--------------------------------------------------------------------===//
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@ -15,7 +15,7 @@
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_ARMBASEINFO_H
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#define CS_ARMBASEINFO_H
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@ -113,7 +113,8 @@ inline static const char *ARM_PROC_IModToString(unsigned val)
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inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
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{
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switch (val) {
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// TODO: add details
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switch (val + 1) {
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default: return "BUGBUG";
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case ARM_MB_SY: return "sy";
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case ARM_MB_ST: return "st";
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@ -121,16 +122,16 @@ inline static const char *ARM_MB_MemBOptToString(unsigned val, bool HasV8)
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case ARM_MB_RESERVED_12: return "#0xc";
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case ARM_MB_ISH: return "ish";
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case ARM_MB_ISHST: return "ishst";
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case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#0x9";
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case ARM_MB_RESERVED_8: return "#0x8";
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case ARM_MB_ISHLD: return HasV8 ? "ishld" : "#9";
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case ARM_MB_RESERVED_8: return "#8";
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case ARM_MB_NSH: return "nsh";
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case ARM_MB_NSHST: return "nshst";
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case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#0x5";
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case ARM_MB_RESERVED_4: return "#0x4";
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case ARM_MB_NSHLD: return HasV8 ? "nshld" : "#5";
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case ARM_MB_RESERVED_4: return "#4";
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case ARM_MB_OSH: return "osh";
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case ARM_MB_OSHST: return "oshst";
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case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#0x1";
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case ARM_MB_RESERVED_0: return "#0x0";
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case ARM_MB_OSHLD: return HasV8 ? "oshld" : "#1";
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case ARM_MB_RESERVED_0: return "#0";
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}
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}
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@ -429,4 +430,57 @@ enum {
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ARMII_CondShift = 28
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};
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typedef struct MClassSysReg {
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const char *Name;
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arm_sysreg sysreg;
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uint16_t M1Encoding12;
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uint16_t M2M3Encoding8;
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uint16_t Encoding;
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int FeaturesRequired[2]; // 2 is enough for MClassSysRegsList
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} MClassSysReg;
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enum TraceSyncBOpt {
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CSYNC = 0
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};
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MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding);
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MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t M1Encoding12);
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// returns APSR with _<bits> qualifier.
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// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
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static inline MClassSysReg *lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
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{
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return lookupMClassSysRegByM2M3Encoding8((1<<9) | (SYSm & 0xFF));
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}
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static inline MClassSysReg *lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
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{
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return lookupMClassSysRegByM2M3Encoding8((1<<8) | (SYSm & 0xFF));
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}
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// returns true if TestFeatures are all present in FeaturesRequired
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static inline bool MClassSysReg_isInRequiredFeatures(MClassSysReg *TheReg, int TestFeatures)
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{
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return (TheReg->FeaturesRequired[0] == TestFeatures || TheReg->FeaturesRequired[1] == TestFeatures);
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}
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// lookup system register using 12-bit SYSm value.
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// Note: the search is uniqued using M1 mask
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static inline MClassSysReg *lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
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{
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return lookupMClassSysRegByM1Encoding12(SYSm);
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}
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static inline const char *ARM_TSB_TraceSyncBOptToString(unsigned val)
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{
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switch (val) {
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default:
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// llvm_unreachable("Unknown trace synchronization barrier operation");
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return NULL;
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case CSYNC:
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return "csync";
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}
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}
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -1,5 +1,5 @@
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_ARMDISASSEMBLER_H
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#define CS_ARMDISASSEMBLER_H
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@ -13,6 +13,6 @@ bool ARM_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst
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bool Thumb_getInstruction(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
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uint64_t ARM_getFeatureBits(unsigned int mode);
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bool ARM_getFeatureBits(unsigned int mode, unsigned int feature);
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#endif
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,231 @@
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/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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/// getRegisterName - This method is automatically generated by tblgen
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/// from the register set description. This returns the assembler name
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/// for the specified register.
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static const char *getRegisterName(unsigned RegNo)
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{
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#ifndef CAPSTONE_DIET
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static const char AsmStrs[] = {
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/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
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/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
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/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
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/* 39 */ 'd', '1', '0', 0,
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/* 43 */ 'q', '1', '0', 0,
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/* 47 */ 's', '1', '0', 0,
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/* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
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/* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
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/* 83 */ 'd', '2', '0', 0,
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/* 87 */ 's', '2', '0', 0,
|
||||
/* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
|
||||
/* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
|
||||
/* 123 */ 'd', '3', '0', 0,
|
||||
/* 127 */ 's', '3', '0', 0,
|
||||
/* 131 */ 'd', '0', 0,
|
||||
/* 134 */ 'q', '0', 0,
|
||||
/* 137 */ 'm', 'v', 'f', 'r', '0', 0,
|
||||
/* 143 */ 's', '0', 0,
|
||||
/* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
|
||||
/* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
|
||||
/* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
|
||||
/* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
|
||||
/* 192 */ 'd', '1', '1', 0,
|
||||
/* 196 */ 'q', '1', '1', 0,
|
||||
/* 200 */ 's', '1', '1', 0,
|
||||
/* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
|
||||
/* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
|
||||
/* 232 */ 'd', '2', '1', 0,
|
||||
/* 236 */ 's', '2', '1', 0,
|
||||
/* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
|
||||
/* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
|
||||
/* 268 */ 'd', '3', '1', 0,
|
||||
/* 272 */ 's', '3', '1', 0,
|
||||
/* 276 */ 'Q', '0', '_', 'Q', '1', 0,
|
||||
/* 282 */ 'R', '0', '_', 'R', '1', 0,
|
||||
/* 288 */ 'd', '1', 0,
|
||||
/* 291 */ 'q', '1', 0,
|
||||
/* 294 */ 'm', 'v', 'f', 'r', '1', 0,
|
||||
/* 300 */ 's', '1', 0,
|
||||
/* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
|
||||
/* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
|
||||
/* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
|
||||
/* 347 */ 'd', '1', '2', 0,
|
||||
/* 351 */ 'q', '1', '2', 0,
|
||||
/* 355 */ 's', '1', '2', 0,
|
||||
/* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
|
||||
/* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
|
||||
/* 391 */ 'd', '2', '2', 0,
|
||||
/* 395 */ 's', '2', '2', 0,
|
||||
/* 399 */ 'D', '0', '_', 'D', '2', 0,
|
||||
/* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
|
||||
/* 414 */ 'Q', '1', '_', 'Q', '2', 0,
|
||||
/* 420 */ 'd', '2', 0,
|
||||
/* 423 */ 'q', '2', 0,
|
||||
/* 426 */ 'm', 'v', 'f', 'r', '2', 0,
|
||||
/* 432 */ 's', '2', 0,
|
||||
/* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
|
||||
/* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
|
||||
/* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
|
||||
/* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
|
||||
/* 485 */ 'd', '1', '3', 0,
|
||||
/* 489 */ 'q', '1', '3', 0,
|
||||
/* 493 */ 's', '1', '3', 0,
|
||||
/* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
|
||||
/* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
|
||||
/* 525 */ 'd', '2', '3', 0,
|
||||
/* 529 */ 's', '2', '3', 0,
|
||||
/* 533 */ 'D', '1', '_', 'D', '3', 0,
|
||||
/* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
|
||||
/* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
|
||||
/* 560 */ 'R', '2', '_', 'R', '3', 0,
|
||||
/* 566 */ 'd', '3', 0,
|
||||
/* 569 */ 'q', '3', 0,
|
||||
/* 572 */ 'r', '3', 0,
|
||||
/* 575 */ 's', '3', 0,
|
||||
/* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
|
||||
/* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
|
||||
/* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
|
||||
/* 625 */ 'd', '1', '4', 0,
|
||||
/* 629 */ 'q', '1', '4', 0,
|
||||
/* 633 */ 's', '1', '4', 0,
|
||||
/* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
|
||||
/* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
|
||||
/* 669 */ 'd', '2', '4', 0,
|
||||
/* 673 */ 's', '2', '4', 0,
|
||||
/* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
|
||||
/* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
|
||||
/* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
|
||||
/* 710 */ 'd', '4', 0,
|
||||
/* 713 */ 'q', '4', 0,
|
||||
/* 716 */ 'r', '4', 0,
|
||||
/* 719 */ 's', '4', 0,
|
||||
/* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
|
||||
/* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
|
||||
/* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
|
||||
/* 765 */ 'd', '1', '5', 0,
|
||||
/* 769 */ 'q', '1', '5', 0,
|
||||
/* 773 */ 's', '1', '5', 0,
|
||||
/* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
|
||||
/* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
|
||||
/* 805 */ 'd', '2', '5', 0,
|
||||
/* 809 */ 's', '2', '5', 0,
|
||||
/* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
|
||||
/* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
|
||||
/* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
|
||||
/* 843 */ 'R', '4', '_', 'R', '5', 0,
|
||||
/* 849 */ 'd', '5', 0,
|
||||
/* 852 */ 'q', '5', 0,
|
||||
/* 855 */ 'r', '5', 0,
|
||||
/* 858 */ 's', '5', 0,
|
||||
/* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
|
||||
/* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
|
||||
/* 893 */ 'd', '1', '6', 0,
|
||||
/* 897 */ 's', '1', '6', 0,
|
||||
/* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
|
||||
/* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
|
||||
/* 933 */ 'd', '2', '6', 0,
|
||||
/* 937 */ 's', '2', '6', 0,
|
||||
/* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
|
||||
/* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
|
||||
/* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
|
||||
/* 977 */ 'd', '6', 0,
|
||||
/* 980 */ 'q', '6', 0,
|
||||
/* 983 */ 'r', '6', 0,
|
||||
/* 986 */ 's', '6', 0,
|
||||
/* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
|
||||
/* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
|
||||
/* 1017 */ 'd', '1', '7', 0,
|
||||
/* 1021 */ 's', '1', '7', 0,
|
||||
/* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
|
||||
/* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
|
||||
/* 1053 */ 'd', '2', '7', 0,
|
||||
/* 1057 */ 's', '2', '7', 0,
|
||||
/* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
|
||||
/* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
|
||||
/* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
|
||||
/* 1094 */ 'R', '6', '_', 'R', '7', 0,
|
||||
/* 1100 */ 'd', '7', 0,
|
||||
/* 1103 */ 'q', '7', 0,
|
||||
/* 1106 */ 'r', '7', 0,
|
||||
/* 1109 */ 's', '7', 0,
|
||||
/* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
|
||||
/* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
|
||||
/* 1144 */ 'd', '1', '8', 0,
|
||||
/* 1148 */ 's', '1', '8', 0,
|
||||
/* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
|
||||
/* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
|
||||
/* 1184 */ 'd', '2', '8', 0,
|
||||
/* 1188 */ 's', '2', '8', 0,
|
||||
/* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
|
||||
/* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
|
||||
/* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
|
||||
/* 1228 */ 'd', '8', 0,
|
||||
/* 1231 */ 'q', '8', 0,
|
||||
/* 1234 */ 'r', '8', 0,
|
||||
/* 1237 */ 's', '8', 0,
|
||||
/* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
|
||||
/* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
|
||||
/* 1268 */ 'd', '1', '9', 0,
|
||||
/* 1272 */ 's', '1', '9', 0,
|
||||
/* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
|
||||
/* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
|
||||
/* 1304 */ 'd', '2', '9', 0,
|
||||
/* 1308 */ 's', '2', '9', 0,
|
||||
/* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
|
||||
/* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
|
||||
/* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
|
||||
/* 1345 */ 'R', '8', '_', 'R', '9', 0,
|
||||
/* 1351 */ 'd', '9', 0,
|
||||
/* 1354 */ 'q', '9', 0,
|
||||
/* 1357 */ 's', '9', 0,
|
||||
/* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0,
|
||||
/* 1367 */ 's', 'b', 0,
|
||||
/* 1370 */ 'p', 'c', 0,
|
||||
/* 1373 */ 'f', 'p', 'e', 'x', 'c', 0,
|
||||
/* 1379 */ 'f', 'p', 's', 'i', 'd', 0,
|
||||
/* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
|
||||
/* 1393 */ 's', 'l', 0,
|
||||
/* 1396 */ 'f', 'p', 0,
|
||||
/* 1399 */ 'i', 'p', 0,
|
||||
/* 1402 */ 's', 'p', 0,
|
||||
/* 1405 */ 'f', 'p', 's', 'c', 'r', 0,
|
||||
/* 1411 */ 'l', 'r', 0,
|
||||
/* 1414 */ 'a', 'p', 's', 'r', 0,
|
||||
/* 1419 */ 'c', 'p', 's', 'r', 0,
|
||||
/* 1424 */ 's', 'p', 's', 'r', 0,
|
||||
/* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0,
|
||||
/* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
|
||||
/* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
|
||||
};
|
||||
|
||||
static const uint16_t RegAsmOffset[] = {
|
||||
1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131,
|
||||
288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625,
|
||||
765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184,
|
||||
1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980,
|
||||
1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716,
|
||||
855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858,
|
||||
986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272,
|
||||
87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533,
|
||||
680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997,
|
||||
1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260,
|
||||
276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617,
|
||||
757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749,
|
||||
1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207,
|
||||
1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379,
|
||||
513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195,
|
||||
1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363,
|
||||
501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0,
|
||||
157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637,
|
||||
777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601,
|
||||
885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593,
|
||||
877, 1128, 67, 375, 653, 917, 1168, 107,
|
||||
};
|
||||
|
||||
return AsmStrs+RegAsmOffset[RegNo-1];
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static const char *getRegisterName_digit(unsigned RegNo)
|
||||
{
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
|
||||
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
|
||||
/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
|
||||
/* 39 */ 'd', '1', '0', 0,
|
||||
/* 43 */ 'q', '1', '0', 0,
|
||||
/* 47 */ 'r', '1', '0', 0,
|
||||
/* 51 */ 's', '1', '0', 0,
|
||||
/* 55 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
|
||||
/* 71 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
|
||||
/* 87 */ 'd', '2', '0', 0,
|
||||
/* 91 */ 's', '2', '0', 0,
|
||||
/* 95 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
|
||||
/* 111 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
|
||||
/* 127 */ 'd', '3', '0', 0,
|
||||
/* 131 */ 's', '3', '0', 0,
|
||||
/* 135 */ 'd', '0', 0,
|
||||
/* 138 */ 'q', '0', 0,
|
||||
/* 141 */ 'm', 'v', 'f', 'r', '0', 0,
|
||||
/* 147 */ 's', '0', 0,
|
||||
/* 150 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
|
||||
/* 161 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
|
||||
/* 174 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
|
||||
/* 188 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
|
||||
/* 196 */ 'd', '1', '1', 0,
|
||||
/* 200 */ 'q', '1', '1', 0,
|
||||
/* 204 */ 'r', '1', '1', 0,
|
||||
/* 208 */ 's', '1', '1', 0,
|
||||
/* 212 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
|
||||
/* 224 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
|
||||
/* 240 */ 'd', '2', '1', 0,
|
||||
/* 244 */ 's', '2', '1', 0,
|
||||
/* 248 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
|
||||
/* 260 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
|
||||
/* 276 */ 'd', '3', '1', 0,
|
||||
/* 280 */ 's', '3', '1', 0,
|
||||
/* 284 */ 'Q', '0', '_', 'Q', '1', 0,
|
||||
/* 290 */ 'R', '0', '_', 'R', '1', 0,
|
||||
/* 296 */ 'd', '1', 0,
|
||||
/* 299 */ 'q', '1', 0,
|
||||
/* 302 */ 'm', 'v', 'f', 'r', '1', 0,
|
||||
/* 308 */ 's', '1', 0,
|
||||
/* 311 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
|
||||
/* 325 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
|
||||
/* 340 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
|
||||
/* 355 */ 'd', '1', '2', 0,
|
||||
/* 359 */ 'q', '1', '2', 0,
|
||||
/* 363 */ 'r', '1', '2', 0,
|
||||
/* 367 */ 's', '1', '2', 0,
|
||||
/* 371 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
|
||||
/* 387 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
|
||||
/* 403 */ 'd', '2', '2', 0,
|
||||
/* 407 */ 's', '2', '2', 0,
|
||||
/* 411 */ 'D', '0', '_', 'D', '2', 0,
|
||||
/* 417 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
|
||||
/* 426 */ 'Q', '1', '_', 'Q', '2', 0,
|
||||
/* 432 */ 'd', '2', 0,
|
||||
/* 435 */ 'q', '2', 0,
|
||||
/* 438 */ 'm', 'v', 'f', 'r', '2', 0,
|
||||
/* 444 */ 's', '2', 0,
|
||||
/* 447 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
|
||||
/* 455 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
|
||||
/* 469 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
|
||||
/* 481 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
|
||||
/* 497 */ 'd', '1', '3', 0,
|
||||
/* 501 */ 'q', '1', '3', 0,
|
||||
/* 505 */ 'r', '1', '3', 0,
|
||||
/* 509 */ 's', '1', '3', 0,
|
||||
/* 513 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
|
||||
/* 529 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
|
||||
/* 541 */ 'd', '2', '3', 0,
|
||||
/* 545 */ 's', '2', '3', 0,
|
||||
/* 549 */ 'D', '1', '_', 'D', '3', 0,
|
||||
/* 555 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
|
||||
/* 564 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
|
||||
/* 576 */ 'R', '2', '_', 'R', '3', 0,
|
||||
/* 582 */ 'd', '3', 0,
|
||||
/* 585 */ 'q', '3', 0,
|
||||
/* 588 */ 'r', '3', 0,
|
||||
/* 591 */ 's', '3', 0,
|
||||
/* 594 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
|
||||
/* 609 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
|
||||
/* 625 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
|
||||
/* 641 */ 'd', '1', '4', 0,
|
||||
/* 645 */ 'q', '1', '4', 0,
|
||||
/* 649 */ 'r', '1', '4', 0,
|
||||
/* 653 */ 's', '1', '4', 0,
|
||||
/* 657 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
|
||||
/* 673 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
|
||||
/* 689 */ 'd', '2', '4', 0,
|
||||
/* 693 */ 's', '2', '4', 0,
|
||||
/* 697 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
|
||||
/* 706 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
|
||||
/* 718 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
|
||||
/* 730 */ 'd', '4', 0,
|
||||
/* 733 */ 'q', '4', 0,
|
||||
/* 736 */ 'r', '4', 0,
|
||||
/* 739 */ 's', '4', 0,
|
||||
/* 742 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
|
||||
/* 757 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
|
||||
/* 769 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
|
||||
/* 785 */ 'd', '1', '5', 0,
|
||||
/* 789 */ 'q', '1', '5', 0,
|
||||
/* 793 */ 's', '1', '5', 0,
|
||||
/* 797 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
|
||||
/* 813 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
|
||||
/* 825 */ 'd', '2', '5', 0,
|
||||
/* 829 */ 's', '2', '5', 0,
|
||||
/* 833 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
|
||||
/* 842 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
|
||||
/* 851 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
|
||||
/* 863 */ 'R', '4', '_', 'R', '5', 0,
|
||||
/* 869 */ 'd', '5', 0,
|
||||
/* 872 */ 'q', '5', 0,
|
||||
/* 875 */ 'r', '5', 0,
|
||||
/* 878 */ 's', '5', 0,
|
||||
/* 881 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
|
||||
/* 897 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
|
||||
/* 913 */ 'd', '1', '6', 0,
|
||||
/* 917 */ 's', '1', '6', 0,
|
||||
/* 921 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
|
||||
/* 937 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
|
||||
/* 953 */ 'd', '2', '6', 0,
|
||||
/* 957 */ 's', '2', '6', 0,
|
||||
/* 961 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
|
||||
/* 973 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
|
||||
/* 985 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
|
||||
/* 997 */ 'd', '6', 0,
|
||||
/* 1000 */ 'q', '6', 0,
|
||||
/* 1003 */ 'r', '6', 0,
|
||||
/* 1006 */ 's', '6', 0,
|
||||
/* 1009 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
|
||||
/* 1025 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
|
||||
/* 1037 */ 'd', '1', '7', 0,
|
||||
/* 1041 */ 's', '1', '7', 0,
|
||||
/* 1045 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
|
||||
/* 1061 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
|
||||
/* 1073 */ 'd', '2', '7', 0,
|
||||
/* 1077 */ 's', '2', '7', 0,
|
||||
/* 1081 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
|
||||
/* 1093 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
|
||||
/* 1102 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
|
||||
/* 1114 */ 'R', '6', '_', 'R', '7', 0,
|
||||
/* 1120 */ 'd', '7', 0,
|
||||
/* 1123 */ 'q', '7', 0,
|
||||
/* 1126 */ 'r', '7', 0,
|
||||
/* 1129 */ 's', '7', 0,
|
||||
/* 1132 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
|
||||
/* 1148 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
|
||||
/* 1164 */ 'd', '1', '8', 0,
|
||||
/* 1168 */ 's', '1', '8', 0,
|
||||
/* 1172 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
|
||||
/* 1188 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
|
||||
/* 1204 */ 'd', '2', '8', 0,
|
||||
/* 1208 */ 's', '2', '8', 0,
|
||||
/* 1212 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
|
||||
/* 1224 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
|
||||
/* 1236 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
|
||||
/* 1248 */ 'd', '8', 0,
|
||||
/* 1251 */ 'q', '8', 0,
|
||||
/* 1254 */ 'r', '8', 0,
|
||||
/* 1257 */ 's', '8', 0,
|
||||
/* 1260 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
|
||||
/* 1276 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
|
||||
/* 1288 */ 'd', '1', '9', 0,
|
||||
/* 1292 */ 's', '1', '9', 0,
|
||||
/* 1296 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
|
||||
/* 1312 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
|
||||
/* 1324 */ 'd', '2', '9', 0,
|
||||
/* 1328 */ 's', '2', '9', 0,
|
||||
/* 1332 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
|
||||
/* 1344 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
|
||||
/* 1353 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
|
||||
/* 1365 */ 'R', '8', '_', 'R', '9', 0,
|
||||
/* 1371 */ 'd', '9', 0,
|
||||
/* 1374 */ 'q', '9', 0,
|
||||
/* 1377 */ 'r', '9', 0,
|
||||
/* 1380 */ 's', '9', 0,
|
||||
/* 1383 */ 'R', '1', '2', '_', 'S', 'P', 0,
|
||||
/* 1390 */ 'p', 'c', 0,
|
||||
/* 1393 */ 'f', 'p', 'e', 'x', 'c', 0,
|
||||
/* 1399 */ 'f', 'p', 's', 'i', 'd', 0,
|
||||
/* 1405 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
|
||||
/* 1413 */ 'f', 'p', 's', 'c', 'r', 0,
|
||||
/* 1419 */ 'a', 'p', 's', 'r', 0,
|
||||
/* 1424 */ 'c', 'p', 's', 'r', 0,
|
||||
/* 1429 */ 's', 'p', 's', 'r', 0,
|
||||
/* 1434 */ 'f', 'p', 'i', 'n', 's', 't', 0,
|
||||
/* 1441 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
|
||||
/* 1452 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
|
||||
};
|
||||
|
||||
static const uint16_t RegAsmOffset[] = {
|
||||
1419, 1452, 1424, 1393, 1434, 1413, 1441, 1399, 1405, 649, 1390, 505, 1429, 135,
|
||||
296, 432, 582, 730, 869, 997, 1120, 1248, 1371, 39, 196, 355, 497, 641,
|
||||
785, 913, 1037, 1164, 1288, 87, 240, 403, 541, 689, 825, 953, 1073, 1204,
|
||||
1324, 127, 276, 447, 141, 302, 438, 138, 299, 435, 585, 733, 872, 1000,
|
||||
1123, 1251, 1374, 43, 200, 359, 501, 645, 789, 144, 305, 441, 588, 736,
|
||||
875, 1003, 1126, 1254, 1377, 47, 204, 363, 147, 308, 444, 591, 739, 878,
|
||||
1006, 1129, 1257, 1380, 51, 208, 367, 509, 653, 793, 917, 1041, 1168, 1292,
|
||||
91, 244, 407, 545, 693, 829, 957, 1077, 1208, 1328, 131, 280, 411, 549,
|
||||
700, 836, 967, 1087, 1218, 1338, 6, 167, 317, 461, 601, 749, 889, 1017,
|
||||
1140, 1268, 63, 232, 379, 521, 665, 805, 929, 1053, 1180, 1304, 103, 268,
|
||||
284, 426, 570, 724, 857, 991, 1108, 1242, 1359, 32, 180, 347, 489, 633,
|
||||
777, 564, 718, 851, 985, 1102, 1236, 1353, 26, 174, 340, 481, 625, 769,
|
||||
1383, 290, 576, 863, 1114, 1365, 188, 417, 555, 709, 842, 976, 1093, 1227,
|
||||
1344, 16, 150, 328, 469, 613, 757, 901, 1025, 1152, 1276, 75, 212, 391,
|
||||
529, 677, 813, 941, 1061, 1192, 1312, 115, 248, 697, 833, 964, 1084, 1215,
|
||||
1335, 3, 164, 314, 458, 597, 745, 885, 1013, 1136, 1264, 59, 228, 375,
|
||||
517, 661, 801, 925, 1049, 1176, 1300, 99, 264, 961, 1081, 1212, 1332, 0,
|
||||
161, 311, 455, 594, 742, 881, 1009, 1132, 1260, 55, 224, 371, 513, 657,
|
||||
797, 921, 1045, 1172, 1296, 95, 260, 420, 712, 979, 1230, 19, 332, 617,
|
||||
905, 1156, 79, 395, 681, 945, 1196, 119, 706, 973, 1224, 13, 325, 609,
|
||||
897, 1148, 71, 387, 673, 937, 1188, 111,
|
||||
};
|
||||
|
||||
return AsmStrs+RegAsmOffset[RegNo-1];
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -1,72 +1,162 @@
|
|||
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|
||||
|* *|
|
||||
|*Subtarget Enumeration Source Fragment *|
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *|
|
||||
|* Subtarget Enumeration Source Fragment *|
|
||||
|* *|
|
||||
|* Automatically generated file, do not edit! *|
|
||||
|* *|
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
|
||||
enum {
|
||||
ARM_ARMv2 = 0,
|
||||
ARM_ARMv2a = 1,
|
||||
ARM_ARMv3 = 2,
|
||||
ARM_ARMv3m = 3,
|
||||
ARM_ARMv4 = 4,
|
||||
ARM_ARMv4t = 5,
|
||||
ARM_ARMv5t = 6,
|
||||
ARM_ARMv5te = 7,
|
||||
ARM_ARMv5tej = 8,
|
||||
ARM_ARMv6 = 9,
|
||||
ARM_ARMv6j = 10,
|
||||
ARM_ARMv6k = 11,
|
||||
ARM_ARMv6kz = 12,
|
||||
ARM_ARMv6m = 13,
|
||||
ARM_ARMv6sm = 14,
|
||||
ARM_ARMv6t2 = 15,
|
||||
ARM_ARMv7a = 16,
|
||||
ARM_ARMv7em = 17,
|
||||
ARM_ARMv7k = 18,
|
||||
ARM_ARMv7m = 19,
|
||||
ARM_ARMv7r = 20,
|
||||
ARM_ARMv7s = 21,
|
||||
ARM_ARMv7ve = 22,
|
||||
ARM_ARMv8a = 23,
|
||||
ARM_ARMv8mBaseline = 24,
|
||||
ARM_ARMv8mMainline = 25,
|
||||
ARM_ARMv8r = 26,
|
||||
ARM_ARMv81a = 27,
|
||||
ARM_ARMv82a = 28,
|
||||
ARM_ARMv83a = 29,
|
||||
ARM_ARMv84a = 30,
|
||||
ARM_Feature8MSecExt = 31,
|
||||
ARM_FeatureAClass = 32,
|
||||
ARM_FeatureAES = 33,
|
||||
ARM_FeatureAcquireRelease = 34,
|
||||
ARM_FeatureAvoidMOVsShOp = 35,
|
||||
ARM_FeatureAvoidPartialCPSR = 36,
|
||||
ARM_FeatureCRC = 37,
|
||||
ARM_FeatureCheapPredicableCPSR = 38,
|
||||
ARM_FeatureCheckVLDnAlign = 39,
|
||||
ARM_FeatureCrypto = 40,
|
||||
ARM_FeatureD16 = 41,
|
||||
ARM_FeatureDB = 42,
|
||||
ARM_FeatureDFB = 43,
|
||||
ARM_FeatureDSP = 44,
|
||||
ARM_FeatureDontWidenVMOVS = 45,
|
||||
ARM_FeatureDotProd = 46,
|
||||
ARM_FeatureExecuteOnly = 47,
|
||||
ARM_FeatureExpandMLx = 48,
|
||||
ARM_FeatureFP16 = 49,
|
||||
ARM_FeatureFPAO = 50,
|
||||
ARM_FeatureFPARMv8 = 51,
|
||||
ARM_FeatureFullFP16 = 52,
|
||||
ARM_FeatureFuseAES = 53,
|
||||
ARM_FeatureFuseLiterals = 54,
|
||||
ARM_FeatureHWDivARM = 55,
|
||||
ARM_FeatureHWDivThumb = 56,
|
||||
ARM_FeatureHasNoBranchPredictor = 57,
|
||||
ARM_FeatureHasRetAddrStack = 58,
|
||||
ARM_FeatureHasSlowFPVMLx = 59,
|
||||
ARM_FeatureHasVMLxHazards = 60,
|
||||
ARM_FeatureLongCalls = 61,
|
||||
ARM_FeatureMClass = 62,
|
||||
ARM_FeatureMP = 63,
|
||||
ARM_FeatureMuxedUnits = 64,
|
||||
ARM_FeatureNEON = 65,
|
||||
ARM_FeatureNEONForFP = 66,
|
||||
ARM_FeatureNEONForFPMovs = 67,
|
||||
ARM_FeatureNaClTrap = 68,
|
||||
ARM_FeatureNoARM = 69,
|
||||
ARM_FeatureNoMovt = 70,
|
||||
ARM_FeatureNoNegativeImmediates = 71,
|
||||
ARM_FeatureNoPostRASched = 72,
|
||||
ARM_FeatureNonpipelinedVFP = 73,
|
||||
ARM_FeaturePerfMon = 74,
|
||||
ARM_FeaturePref32BitThumb = 75,
|
||||
ARM_FeaturePrefISHSTBarrier = 76,
|
||||
ARM_FeaturePreferVMOVSR = 77,
|
||||
ARM_FeatureProfUnpredicate = 78,
|
||||
ARM_FeatureRAS = 79,
|
||||
ARM_FeatureRClass = 80,
|
||||
ARM_FeatureReadTp = 81,
|
||||
ARM_FeatureReserveR9 = 82,
|
||||
ARM_FeatureSHA2 = 83,
|
||||
ARM_FeatureSlowFPBrcc = 84,
|
||||
ARM_FeatureSlowLoadDSubreg = 85,
|
||||
ARM_FeatureSlowOddRegister = 86,
|
||||
ARM_FeatureSlowVDUP32 = 87,
|
||||
ARM_FeatureSlowVGETLNi32 = 88,
|
||||
ARM_FeatureSplatVFPToNeon = 89,
|
||||
ARM_FeatureStrictAlign = 90,
|
||||
ARM_FeatureThumb2 = 91,
|
||||
ARM_FeatureTrustZone = 92,
|
||||
ARM_FeatureUseAA = 93,
|
||||
ARM_FeatureUseMISched = 94,
|
||||
ARM_FeatureV7Clrex = 95,
|
||||
ARM_FeatureVFP2 = 96,
|
||||
ARM_FeatureVFP3 = 97,
|
||||
ARM_FeatureVFP4 = 98,
|
||||
ARM_FeatureVFPOnlySP = 99,
|
||||
ARM_FeatureVMLxForwarding = 100,
|
||||
ARM_FeatureVirtualization = 101,
|
||||
ARM_FeatureZCZeroing = 102,
|
||||
ARM_HasV4TOps = 103,
|
||||
ARM_HasV5TEOps = 104,
|
||||
ARM_HasV5TOps = 105,
|
||||
ARM_HasV6KOps = 106,
|
||||
ARM_HasV6MOps = 107,
|
||||
ARM_HasV6Ops = 108,
|
||||
ARM_HasV6T2Ops = 109,
|
||||
ARM_HasV7Ops = 110,
|
||||
ARM_HasV8MBaselineOps = 111,
|
||||
ARM_HasV8MMainlineOps = 112,
|
||||
ARM_HasV8Ops = 113,
|
||||
ARM_HasV8_1aOps = 114,
|
||||
ARM_HasV8_2aOps = 115,
|
||||
ARM_HasV8_3aOps = 116,
|
||||
ARM_HasV8_4aOps = 117,
|
||||
ARM_IWMMXT = 118,
|
||||
ARM_IWMMXT2 = 119,
|
||||
ARM_ModeSoftFloat = 120,
|
||||
ARM_ModeThumb = 121,
|
||||
ARM_ProcA5 = 122,
|
||||
ARM_ProcA7 = 123,
|
||||
ARM_ProcA8 = 124,
|
||||
ARM_ProcA9 = 125,
|
||||
ARM_ProcA12 = 126,
|
||||
ARM_ProcA15 = 127,
|
||||
ARM_ProcA17 = 128,
|
||||
ARM_ProcA32 = 129,
|
||||
ARM_ProcA35 = 130,
|
||||
ARM_ProcA53 = 131,
|
||||
ARM_ProcA55 = 132,
|
||||
ARM_ProcA57 = 133,
|
||||
ARM_ProcA72 = 134,
|
||||
ARM_ProcA73 = 135,
|
||||
ARM_ProcA75 = 136,
|
||||
ARM_ProcExynosM1 = 137,
|
||||
ARM_ProcKrait = 138,
|
||||
ARM_ProcKryo = 139,
|
||||
ARM_ProcM3 = 140,
|
||||
ARM_ProcR4 = 141,
|
||||
ARM_ProcR5 = 142,
|
||||
ARM_ProcR7 = 143,
|
||||
ARM_ProcR52 = 144,
|
||||
ARM_ProcSwift = 145,
|
||||
ARM_XScale = 146,
|
||||
};
|
||||
|
||||
#ifdef GET_SUBTARGETINFO_ENUM
|
||||
#undef GET_SUBTARGETINFO_ENUM
|
||||
|
||||
#define ARM_FeatureAClass (1ULL << 0)
|
||||
#define ARM_FeatureAvoidMOVsShOp (1ULL << 1)
|
||||
#define ARM_FeatureAvoidPartialCPSR (1ULL << 2)
|
||||
#define ARM_FeatureCRC (1ULL << 3)
|
||||
#define ARM_FeatureCrypto (1ULL << 4)
|
||||
#define ARM_FeatureD16 (1ULL << 5)
|
||||
#define ARM_FeatureDB (1ULL << 6)
|
||||
#define ARM_FeatureDSPThumb2 (1ULL << 7)
|
||||
#define ARM_FeatureFP16 (1ULL << 8)
|
||||
#define ARM_FeatureFPARMv8 (1ULL << 9)
|
||||
#define ARM_FeatureHWDiv (1ULL << 10)
|
||||
#define ARM_FeatureHWDivARM (1ULL << 11)
|
||||
#define ARM_FeatureHasRAS (1ULL << 12)
|
||||
#define ARM_FeatureHasSlowFPVMLx (1ULL << 13)
|
||||
#define ARM_FeatureMClass (1ULL << 14)
|
||||
#define ARM_FeatureMP (1ULL << 15)
|
||||
#define ARM_FeatureNEON (1ULL << 16)
|
||||
#define ARM_FeatureNEONForFP (1ULL << 17)
|
||||
#define ARM_FeatureNaClTrap (1ULL << 18)
|
||||
#define ARM_FeatureNoARM (1ULL << 19)
|
||||
#define ARM_FeaturePerfMon (1ULL << 20)
|
||||
#define ARM_FeaturePref32BitThumb (1ULL << 21)
|
||||
#define ARM_FeatureRClass (1ULL << 22)
|
||||
#define ARM_FeatureSlowFPBrcc (1ULL << 23)
|
||||
#define ARM_FeatureT2XtPk (1ULL << 24)
|
||||
#define ARM_FeatureThumb2 (1ULL << 25)
|
||||
#define ARM_FeatureTrustZone (1ULL << 26)
|
||||
#define ARM_FeatureVFP2 (1ULL << 27)
|
||||
#define ARM_FeatureVFP3 (1ULL << 28)
|
||||
#define ARM_FeatureVFP4 (1ULL << 29)
|
||||
#define ARM_FeatureVFPOnlySP (1ULL << 30)
|
||||
#define ARM_FeatureVMLxForwarding (1ULL << 31)
|
||||
#define ARM_FeatureVirtualization (1ULL << 32)
|
||||
#define ARM_FeatureZCZeroing (1ULL << 33)
|
||||
#define ARM_HasV4TOps (1ULL << 34)
|
||||
#define ARM_HasV5TEOps (1ULL << 35)
|
||||
#define ARM_HasV5TOps (1ULL << 36)
|
||||
#define ARM_HasV6MOps (1ULL << 37)
|
||||
#define ARM_HasV6Ops (1ULL << 38)
|
||||
#define ARM_HasV6T2Ops (1ULL << 39)
|
||||
#define ARM_HasV7Ops (1ULL << 40)
|
||||
#define ARM_HasV8Ops (1ULL << 41)
|
||||
#define ARM_ModeThumb (1ULL << 42)
|
||||
#define ARM_ProcA5 (1ULL << 43)
|
||||
#define ARM_ProcA7 (1ULL << 44)
|
||||
#define ARM_ProcA8 (1ULL << 45)
|
||||
#define ARM_ProcA9 (1ULL << 46)
|
||||
#define ARM_ProcA12 (1ULL << 47)
|
||||
#define ARM_ProcA15 (1ULL << 48)
|
||||
#define ARM_ProcA17 (1ULL << 49)
|
||||
#define ARM_ProcA53 (1ULL << 50)
|
||||
#define ARM_ProcA57 (1ULL << 51)
|
||||
#define ARM_ProcKrait (1ULL << 52)
|
||||
#define ARM_ProcR5 (1ULL << 53)
|
||||
#define ARM_ProcSwift (1ULL << 54)
|
||||
|
||||
#endif // GET_SUBTARGETINFO_ENUM
|
||||
|
|
|
|||
|
|
@ -0,0 +1,270 @@
|
|||
|
||||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*|* *|
|
||||
|* GenSystemRegister Source Fragment *|
|
||||
|* *|
|
||||
|* Automatically generated file, do not edit! *|
|
||||
|* *|
|
||||
\*===----------------------------------------------------------------------===*/
|
||||
|
||||
|
||||
enum BankedRegValues {
|
||||
elr_hyp = 0,
|
||||
lr_abt = 1,
|
||||
lr_fiq = 2,
|
||||
lr_irq = 3,
|
||||
lr_mon = 4,
|
||||
lr_svc = 5,
|
||||
lr_und = 6,
|
||||
lr_usr = 7,
|
||||
r10_fiq = 8,
|
||||
r10_usr = 9,
|
||||
r11_fiq = 10,
|
||||
r11_usr = 11,
|
||||
r12_fiq = 12,
|
||||
r12_usr = 13,
|
||||
r8_fiq = 14,
|
||||
r8_usr = 15,
|
||||
r9_fiq = 16,
|
||||
r9_usr = 17,
|
||||
sp_abt = 18,
|
||||
sp_fiq = 19,
|
||||
sp_hyp = 20,
|
||||
sp_irq = 21,
|
||||
sp_mon = 22,
|
||||
sp_svc = 23,
|
||||
sp_und = 24,
|
||||
sp_usr = 25,
|
||||
spsr_abt = 26,
|
||||
spsr_fiq = 27,
|
||||
spsr_hyp = 28,
|
||||
spsr_irq = 29,
|
||||
spsr_mon = 30,
|
||||
spsr_svc = 31,
|
||||
spsr_und = 32,
|
||||
};
|
||||
|
||||
static MClassSysReg MClassSysRegsList[] = {
|
||||
{ "apsr_g", ARM_SYSREG_APSR_G, 0x400, 0x0, 0x400, {ARM_FeatureDSP} }, // 0
|
||||
{ "apsr_nzcvqg", ARM_SYSREG_APSR_NZCVQG, 0xC00, 0x300, 0xC00, {ARM_FeatureDSP} }, // 1
|
||||
{ "iapsr_g", ARM_SYSREG_IAPSR_G, 0x401, 0x1, 0x401, {ARM_FeatureDSP} }, // 2
|
||||
{ "iapsr_nzcvqg", ARM_SYSREG_IAPSR_NZCVQG, 0xC01, 0x301, 0xC01, {ARM_FeatureDSP} }, // 3
|
||||
{ "eapsr_g", ARM_SYSREG_EAPSR_G, 0x402, 0x2, 0x402, {ARM_FeatureDSP} }, // 4
|
||||
{ "eapsr_nzcvqg", ARM_SYSREG_EAPSR_NZCVQG, 0xC02, 0x302, 0xC02, {ARM_FeatureDSP} }, // 5
|
||||
{ "xpsr_g", ARM_SYSREG_XPSR_G, 0x403, 0x3, 0x403, {ARM_FeatureDSP} }, // 6
|
||||
{ "xpsr_nzcvqg", ARM_SYSREG_XPSR_NZCVQG, 0xC03, 0x303, 0xC03, {ARM_FeatureDSP} }, // 7
|
||||
{ "apsr", ARM_SYSREG_APSR, 0x800, 0x100, 0x800, {} }, // 8
|
||||
{ "apsr_nzcvq", ARM_SYSREG_APSR_NZCVQ, 0x1800, 0x200, 0x800, {} }, // 9
|
||||
{ "iapsr", ARM_SYSREG_IAPSR, 0x801, 0x101, 0x801, {} }, // 10
|
||||
{ "iapsr_nzcvq", ARM_SYSREG_IAPSR_NZCVQ, 0x1801, 0x201, 0x801, {} }, // 11
|
||||
{ "eapsr", ARM_SYSREG_EAPSR, 0x802, 0x102, 0x802, {} }, // 12
|
||||
{ "eapsr_nzcvq", ARM_SYSREG_EAPSR_NZCVQ, 0x1802, 0x202, 0x802, {} }, // 13
|
||||
{ "xpsr", ARM_SYSREG_XPSR, 0x803, 0x103, 0x803, {} }, // 14
|
||||
{ "xpsr_nzcvq", ARM_SYSREG_XPSR_NZCVQ, 0x1803, 0x203, 0x803, {} }, // 15
|
||||
{ "ipsr", ARM_SYSREG_IPSR, 0x805, 0x105, 0x805, {} }, // 16
|
||||
{ "epsr", ARM_SYSREG_EPSR, 0x806, 0x106, 0x806, {} }, // 17
|
||||
{ "iepsr", ARM_SYSREG_IEPSR, 0x807, 0x107, 0x807, {} }, // 18
|
||||
{ "msp", ARM_SYSREG_MSP, 0x808, 0x108, 0x808, {} }, // 19
|
||||
{ "psp", ARM_SYSREG_PSP, 0x809, 0x109, 0x809, {} }, // 20
|
||||
{ "msplim", ARM_SYSREG_MSPLIM, 0x80A, 0x10A, 0x80A, {ARM_HasV8MBaselineOps} }, // 21
|
||||
{ "psplim", ARM_SYSREG_PSPLIM, 0x80B, 0x10B, 0x80B, {ARM_HasV8MBaselineOps} }, // 22
|
||||
{ "primask", ARM_SYSREG_PRIMASK, 0x810, 0x110, 0x810, {} }, // 23
|
||||
{ "basepri", ARM_SYSREG_BASEPRI, 0x811, 0x111, 0x811, {ARM_HasV7Ops} }, // 24
|
||||
{ "basepri_max", ARM_SYSREG_BASEPRI_MAX, 0x812, 0x112, 0x812, {ARM_HasV7Ops} }, // 25
|
||||
{ "faultmask", ARM_SYSREG_FAULTMASK, 0x813, 0x113, 0x813, {ARM_HasV7Ops} }, // 26
|
||||
{ "control", ARM_SYSREG_CONTROL, 0x814, 0x114, 0x814, {} }, // 27
|
||||
{ "msp_ns", ARM_SYSREG_MSP_NS, 0x888, 0x188, 0x888, {ARM_Feature8MSecExt} }, // 28
|
||||
{ "psp_ns", ARM_SYSREG_PSP_NS, 0x889, 0x189, 0x889, {ARM_Feature8MSecExt} }, // 29
|
||||
{ "msplim_ns", ARM_SYSREG_MSPLIM_NS, 0x88A, 0x18A, 0x88A, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 30
|
||||
{ "psplim_ns", ARM_SYSREG_PSPLIM_NS, 0x88B, 0x18B, 0x88B, {ARM_Feature8MSecExt, ARM_HasV8MBaselineOps} }, // 31
|
||||
{ "primask_ns", ARM_SYSREG_PRIMASK_NS, 0x890, 0x190, 0x890, {} }, // 32
|
||||
{ "basepri_ns", ARM_SYSREG_BASEPRI_NS, 0x891, 0x191, 0x891, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 33
|
||||
{ "faultmask_ns", ARM_SYSREG_FAULTMASK_NS, 0x893, 0x193, 0x893, {ARM_Feature8MSecExt, ARM_HasV7Ops} }, // 34
|
||||
{ "control_ns", ARM_SYSREG_CONTROL_NS, 0x894, 0x194, 0x894, {ARM_Feature8MSecExt} }, // 35
|
||||
{ "sp_ns", ARM_SYSREG_SP_NS, 0x898, 0x198, 0x898, {ARM_Feature8MSecExt} }, // 36
|
||||
};
|
||||
|
||||
static BankedReg BankedRegsList[] = {
|
||||
{ "r8_usr", ARM_SYSREG_R8_USR, 0x0 }, // 0
|
||||
{ "r9_usr", ARM_SYSREG_R9_USR, 0x1 }, // 1
|
||||
{ "r10_usr", ARM_SYSREG_R10_USR, 0x2 }, // 2
|
||||
{ "r11_usr", ARM_SYSREG_R11_USR, 0x3 }, // 3
|
||||
{ "r12_usr", ARM_SYSREG_R12_USR, 0x4 }, // 4
|
||||
{ "sp_usr", ARM_SYSREG_SP_USR, 0x5 }, // 5
|
||||
{ "lr_usr", ARM_SYSREG_LR_USR, 0x6 }, // 6
|
||||
{ "r8_fiq", ARM_SYSREG_R8_FIQ, 0x8 }, // 7
|
||||
{ "r9_fiq", ARM_SYSREG_R9_FIQ, 0x9 }, // 8
|
||||
{ "r10_fiq", ARM_SYSREG_R10_FIQ, 0xA }, // 9
|
||||
{ "r11_fiq", ARM_SYSREG_R11_FIQ, 0xB }, // 10
|
||||
{ "r12_fiq", ARM_SYSREG_R12_FIQ, 0xC }, // 11
|
||||
{ "sp_fiq", ARM_SYSREG_SP_FIQ, 0xD }, // 12
|
||||
{ "lr_fiq", ARM_SYSREG_LR_FIQ, 0xE }, // 13
|
||||
{ "lr_irq", ARM_SYSREG_LR_IRQ, 0x10 }, // 14
|
||||
{ "sp_irq", ARM_SYSREG_SP_IRQ, 0x11 }, // 15
|
||||
{ "lr_svc", ARM_SYSREG_LR_SVC, 0x12 }, // 16
|
||||
{ "sp_svc", ARM_SYSREG_SP_SVC, 0x13 }, // 17
|
||||
{ "lr_abt", ARM_SYSREG_LR_ABT, 0x14 }, // 18
|
||||
{ "sp_abt", ARM_SYSREG_SP_ABT, 0x15 }, // 19
|
||||
{ "lr_und", ARM_SYSREG_LR_UND, 0x16 }, // 20
|
||||
{ "sp_und", ARM_SYSREG_SP_UND, 0x17 }, // 21
|
||||
{ "lr_mon", ARM_SYSREG_LR_MON, 0x1C }, // 22
|
||||
{ "sp_mon", ARM_SYSREG_SP_MON, 0x1D }, // 23
|
||||
{ "elr_hyp", ARM_SYSREG_ELR_HYP, 0x1E }, // 24
|
||||
{ "sp_hyp", ARM_SYSREG_SP_HYP, 0x1F }, // 25
|
||||
{ "spsr_fiq", ARM_SYSREG_SPSR_FIQ, 0x2E }, // 26
|
||||
{ "spsr_irq", ARM_SYSREG_SPSR_IRQ, 0x30 }, // 27
|
||||
{ "spsr_svc", ARM_SYSREG_SPSR_SVC, 0x32 }, // 28
|
||||
{ "spsr_abt", ARM_SYSREG_SPSR_ABT, 0x34 }, // 29
|
||||
{ "spsr_und", ARM_SYSREG_SPSR_UND, 0x36 }, // 30
|
||||
{ "spsr_mon", ARM_SYSREG_SPSR_MON, 0x3C }, // 31
|
||||
{ "spsr_hyp", ARM_SYSREG_SPSR_HYP, 0x3E }, // 32
|
||||
};
|
||||
|
||||
MClassSysReg *lookupMClassSysRegByM2M3Encoding8(uint16_t encoding)
|
||||
{
|
||||
unsigned int i;
|
||||
static const struct IndexType Index[] = {
|
||||
{ 0x0, 0 },
|
||||
{ 0x1, 2 },
|
||||
{ 0x2, 4 },
|
||||
{ 0x3, 6 },
|
||||
{ 0x100, 8 },
|
||||
{ 0x101, 10 },
|
||||
{ 0x102, 12 },
|
||||
{ 0x103, 14 },
|
||||
{ 0x105, 16 },
|
||||
{ 0x106, 17 },
|
||||
{ 0x107, 18 },
|
||||
{ 0x108, 19 },
|
||||
{ 0x109, 20 },
|
||||
{ 0x10A, 21 },
|
||||
{ 0x10B, 22 },
|
||||
{ 0x110, 23 },
|
||||
{ 0x111, 24 },
|
||||
{ 0x112, 25 },
|
||||
{ 0x113, 26 },
|
||||
{ 0x114, 27 },
|
||||
{ 0x188, 28 },
|
||||
{ 0x189, 29 },
|
||||
{ 0x18A, 30 },
|
||||
{ 0x18B, 31 },
|
||||
{ 0x190, 32 },
|
||||
{ 0x191, 33 },
|
||||
{ 0x193, 34 },
|
||||
{ 0x194, 35 },
|
||||
{ 0x198, 36 },
|
||||
{ 0x200, 9 },
|
||||
{ 0x201, 11 },
|
||||
{ 0x202, 13 },
|
||||
{ 0x203, 15 },
|
||||
{ 0x300, 1 },
|
||||
{ 0x301, 3 },
|
||||
{ 0x302, 5 },
|
||||
{ 0x303, 7 },
|
||||
};
|
||||
|
||||
i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding);
|
||||
if (i == -1)
|
||||
return NULL;
|
||||
else
|
||||
return &MClassSysRegsList[Index[i].index];
|
||||
}
|
||||
|
||||
MClassSysReg *lookupMClassSysRegByM1Encoding12(uint16_t encoding)
|
||||
{
|
||||
unsigned int i;
|
||||
static const struct IndexType Index[] = {
|
||||
{ 0x400, 0 },
|
||||
{ 0x401, 2 },
|
||||
{ 0x402, 4 },
|
||||
{ 0x403, 6 },
|
||||
{ 0x800, 8 },
|
||||
{ 0x801, 10 },
|
||||
{ 0x802, 12 },
|
||||
{ 0x803, 14 },
|
||||
{ 0x805, 16 },
|
||||
{ 0x806, 17 },
|
||||
{ 0x807, 18 },
|
||||
{ 0x808, 19 },
|
||||
{ 0x809, 20 },
|
||||
{ 0x80A, 21 },
|
||||
{ 0x80B, 22 },
|
||||
{ 0x810, 23 },
|
||||
{ 0x811, 24 },
|
||||
{ 0x812, 25 },
|
||||
{ 0x813, 26 },
|
||||
{ 0x814, 27 },
|
||||
{ 0x888, 28 },
|
||||
{ 0x889, 29 },
|
||||
{ 0x88A, 30 },
|
||||
{ 0x88B, 31 },
|
||||
{ 0x890, 32 },
|
||||
{ 0x891, 33 },
|
||||
{ 0x893, 34 },
|
||||
{ 0x894, 35 },
|
||||
{ 0x898, 36 },
|
||||
{ 0xC00, 1 },
|
||||
{ 0xC01, 3 },
|
||||
{ 0xC02, 5 },
|
||||
{ 0xC03, 7 },
|
||||
{ 0x1800, 9 },
|
||||
{ 0x1801, 11 },
|
||||
{ 0x1802, 13 },
|
||||
{ 0x1803, 15 },
|
||||
};
|
||||
|
||||
i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding);
|
||||
if (i == -1)
|
||||
return NULL;
|
||||
else
|
||||
return &MClassSysRegsList[Index[i].index];
|
||||
}
|
||||
|
||||
BankedReg *lookupBankedRegByEncoding(uint8_t encoding)
|
||||
{
|
||||
unsigned int i;
|
||||
static const struct IndexType Index[] = {
|
||||
{ 0x0, 0 },
|
||||
{ 0x1, 1 },
|
||||
{ 0x2, 2 },
|
||||
{ 0x3, 3 },
|
||||
{ 0x4, 4 },
|
||||
{ 0x5, 5 },
|
||||
{ 0x6, 6 },
|
||||
{ 0x8, 7 },
|
||||
{ 0x9, 8 },
|
||||
{ 0xA, 9 },
|
||||
{ 0xB, 10 },
|
||||
{ 0xC, 11 },
|
||||
{ 0xD, 12 },
|
||||
{ 0xE, 13 },
|
||||
{ 0x10, 14 },
|
||||
{ 0x11, 15 },
|
||||
{ 0x12, 16 },
|
||||
{ 0x13, 17 },
|
||||
{ 0x14, 18 },
|
||||
{ 0x15, 19 },
|
||||
{ 0x16, 20 },
|
||||
{ 0x17, 21 },
|
||||
{ 0x1C, 22 },
|
||||
{ 0x1D, 23 },
|
||||
{ 0x1E, 24 },
|
||||
{ 0x1F, 25 },
|
||||
{ 0x2E, 26 },
|
||||
{ 0x30, 27 },
|
||||
{ 0x32, 28 },
|
||||
{ 0x34, 29 },
|
||||
{ 0x36, 30 },
|
||||
{ 0x3C, 31 },
|
||||
{ 0x3E, 32 },
|
||||
};
|
||||
|
||||
i = binsearch_IndexType(Index, ARR_SIZE(Index), encoding);
|
||||
if (i == -1)
|
||||
return NULL;
|
||||
else
|
||||
return &BankedRegsList[Index[i].index];
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -12,7 +12,7 @@
|
|||
//===----------------------------------------------------------------------===//
|
||||
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifndef CS_ARMINSTPRINTER_H
|
||||
#define CS_ARMINSTPRINTER_H
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_ARM
|
||||
|
||||
|
|
@ -949,4 +949,35 @@ void ARM_reg_access(const cs_insn *insn,
|
|||
}
|
||||
#endif
|
||||
|
||||
// binary search for encoding in IndexType array
|
||||
// return -1 if not found, or index if found
|
||||
unsigned int binsearch_IndexType(const struct IndexType *index, size_t size, uint16_t encoding)
|
||||
{
|
||||
// binary searching since the index is sorted in encoding order
|
||||
unsigned int left, right, m;
|
||||
|
||||
right = size - 1;
|
||||
|
||||
if (encoding < index[0].encoding || encoding > index[right].encoding)
|
||||
// not found
|
||||
return -1;
|
||||
|
||||
left = 0;
|
||||
|
||||
while(left <= right) {
|
||||
m = (left + right) / 2;
|
||||
if (encoding == index[m].encoding) {
|
||||
return m;
|
||||
}
|
||||
|
||||
if (encoding < index[m].encoding)
|
||||
right = m - 1;
|
||||
else
|
||||
left = m + 1;
|
||||
}
|
||||
|
||||
// not found
|
||||
return -1;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/* Capstone Disassembly Engine */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
#ifndef CS_ARM_MAP_H
|
||||
#define CS_ARM_MAP_H
|
||||
|
|
@ -29,4 +29,21 @@ void ARM_reg_access(const cs_insn *insn,
|
|||
cs_regs regs_read, uint8_t *regs_read_count,
|
||||
cs_regs regs_write, uint8_t *regs_write_count);
|
||||
|
||||
struct IndexType {
|
||||
uint16_t encoding;
|
||||
unsigned index;
|
||||
};
|
||||
|
||||
// binary search for encoding in IndexType array
|
||||
// return -1 if not found, or index if found
|
||||
unsigned int binsearch_IndexType(const struct IndexType *index, size_t size, uint16_t encoding);
|
||||
|
||||
typedef struct BankedReg {
|
||||
const char *Name;
|
||||
arm_sysreg sysreg;
|
||||
uint16_t Encoding;
|
||||
} BankedReg;
|
||||
|
||||
BankedReg *lookupBankedRegByEncoding(uint8_t encoding);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,475 @@
|
|||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* This is auto-gen data for Capstone disassembly engine (www.capstone-engine.org) */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
"adc", // ARM_INS_ADC,
|
||||
"add", // ARM_INS_ADD,
|
||||
"addw", // ARM_INS_ADDW,
|
||||
"adr", // ARM_INS_ADR,
|
||||
"aesd", // ARM_INS_AESD,
|
||||
"aese", // ARM_INS_AESE,
|
||||
"aesimc", // ARM_INS_AESIMC,
|
||||
"aesmc", // ARM_INS_AESMC,
|
||||
"and", // ARM_INS_AND,
|
||||
"asr", // ARM_INS_ASR,
|
||||
"b", // ARM_INS_B,
|
||||
"bfc", // ARM_INS_BFC,
|
||||
"bfi", // ARM_INS_BFI,
|
||||
"bic", // ARM_INS_BIC,
|
||||
"bkpt", // ARM_INS_BKPT,
|
||||
"bl", // ARM_INS_BL,
|
||||
"blx", // ARM_INS_BLX,
|
||||
"blxns", // ARM_INS_BLXNS,
|
||||
"bx", // ARM_INS_BX,
|
||||
"bxj", // ARM_INS_BXJ,
|
||||
"bxns", // ARM_INS_BXNS,
|
||||
"cbnz", // ARM_INS_CBNZ,
|
||||
"cbz", // ARM_INS_CBZ,
|
||||
"cdp", // ARM_INS_CDP,
|
||||
"cdp2", // ARM_INS_CDP2,
|
||||
"clrex", // ARM_INS_CLREX,
|
||||
"clz", // ARM_INS_CLZ,
|
||||
"cmn", // ARM_INS_CMN,
|
||||
"cmp", // ARM_INS_CMP,
|
||||
"cps", // ARM_INS_CPS,
|
||||
"crc32b", // ARM_INS_CRC32B,
|
||||
"crc32cb", // ARM_INS_CRC32CB,
|
||||
"crc32ch", // ARM_INS_CRC32CH,
|
||||
"crc32cw", // ARM_INS_CRC32CW,
|
||||
"crc32h", // ARM_INS_CRC32H,
|
||||
"crc32w", // ARM_INS_CRC32W,
|
||||
"csdb", // ARM_INS_CSDB,
|
||||
"dbg", // ARM_INS_DBG,
|
||||
"dcps1", // ARM_INS_DCPS1,
|
||||
"dcps2", // ARM_INS_DCPS2,
|
||||
"dcps3", // ARM_INS_DCPS3,
|
||||
"dfb", // ARM_INS_DFB,
|
||||
"dmb", // ARM_INS_DMB,
|
||||
"dsb", // ARM_INS_DSB,
|
||||
"eor", // ARM_INS_EOR,
|
||||
"eret", // ARM_INS_ERET,
|
||||
"esb", // ARM_INS_ESB,
|
||||
"faddd", // ARM_INS_FADDD,
|
||||
"fadds", // ARM_INS_FADDS,
|
||||
"fcmpzd", // ARM_INS_FCMPZD,
|
||||
"fcmpzs", // ARM_INS_FCMPZS,
|
||||
"fconstd", // ARM_INS_FCONSTD,
|
||||
"fconsts", // ARM_INS_FCONSTS,
|
||||
"fldmdbx", // ARM_INS_FLDMDBX,
|
||||
"fldmiax", // ARM_INS_FLDMIAX,
|
||||
"fmdhr", // ARM_INS_FMDHR,
|
||||
"fmdlr", // ARM_INS_FMDLR,
|
||||
"fmstat", // ARM_INS_FMSTAT,
|
||||
"fstmdbx", // ARM_INS_FSTMDBX,
|
||||
"fstmiax", // ARM_INS_FSTMIAX,
|
||||
"fsubd", // ARM_INS_FSUBD,
|
||||
"fsubs", // ARM_INS_FSUBS,
|
||||
"hint", // ARM_INS_HINT,
|
||||
"hlt", // ARM_INS_HLT,
|
||||
"hvc", // ARM_INS_HVC,
|
||||
"isb", // ARM_INS_ISB,
|
||||
"it", // ARM_INS_IT,
|
||||
"lda", // ARM_INS_LDA,
|
||||
"ldab", // ARM_INS_LDAB,
|
||||
"ldaex", // ARM_INS_LDAEX,
|
||||
"ldaexb", // ARM_INS_LDAEXB,
|
||||
"ldaexd", // ARM_INS_LDAEXD,
|
||||
"ldaexh", // ARM_INS_LDAEXH,
|
||||
"ldah", // ARM_INS_LDAH,
|
||||
"ldc", // ARM_INS_LDC,
|
||||
"ldc2", // ARM_INS_LDC2,
|
||||
"ldc2l", // ARM_INS_LDC2L,
|
||||
"ldcl", // ARM_INS_LDCL,
|
||||
"ldm", // ARM_INS_LDM,
|
||||
"ldmda", // ARM_INS_LDMDA,
|
||||
"ldmdb", // ARM_INS_LDMDB,
|
||||
"ldmib", // ARM_INS_LDMIB,
|
||||
"ldr", // ARM_INS_LDR,
|
||||
"ldrb", // ARM_INS_LDRB,
|
||||
"ldrbt", // ARM_INS_LDRBT,
|
||||
"ldrd", // ARM_INS_LDRD,
|
||||
"ldrex", // ARM_INS_LDREX,
|
||||
"ldrexb", // ARM_INS_LDREXB,
|
||||
"ldrexd", // ARM_INS_LDREXD,
|
||||
"ldrexh", // ARM_INS_LDREXH,
|
||||
"ldrh", // ARM_INS_LDRH,
|
||||
"ldrht", // ARM_INS_LDRHT,
|
||||
"ldrsb", // ARM_INS_LDRSB,
|
||||
"ldrsbt", // ARM_INS_LDRSBT,
|
||||
"ldrsh", // ARM_INS_LDRSH,
|
||||
"ldrsht", // ARM_INS_LDRSHT,
|
||||
"ldrt", // ARM_INS_LDRT,
|
||||
"lsl", // ARM_INS_LSL,
|
||||
"lsr", // ARM_INS_LSR,
|
||||
"mcr", // ARM_INS_MCR,
|
||||
"mcr2", // ARM_INS_MCR2,
|
||||
"mcrr", // ARM_INS_MCRR,
|
||||
"mcrr2", // ARM_INS_MCRR2,
|
||||
"mla", // ARM_INS_MLA,
|
||||
"mls", // ARM_INS_MLS,
|
||||
"mov", // ARM_INS_MOV,
|
||||
"movs", // ARM_INS_MOVS,
|
||||
"movt", // ARM_INS_MOVT,
|
||||
"movw", // ARM_INS_MOVW,
|
||||
"mrc", // ARM_INS_MRC,
|
||||
"mrc2", // ARM_INS_MRC2,
|
||||
"mrrc", // ARM_INS_MRRC,
|
||||
"mrrc2", // ARM_INS_MRRC2,
|
||||
"mrs", // ARM_INS_MRS,
|
||||
"msr", // ARM_INS_MSR,
|
||||
"mul", // ARM_INS_MUL,
|
||||
"mvn", // ARM_INS_MVN,
|
||||
"neg", // ARM_INS_NEG,
|
||||
"nop", // ARM_INS_NOP,
|
||||
"orn", // ARM_INS_ORN,
|
||||
"orr", // ARM_INS_ORR,
|
||||
"pkhbt", // ARM_INS_PKHBT,
|
||||
"pkhtb", // ARM_INS_PKHTB,
|
||||
"pld", // ARM_INS_PLD,
|
||||
"pldw", // ARM_INS_PLDW,
|
||||
"pli", // ARM_INS_PLI,
|
||||
"pop", // ARM_INS_POP,
|
||||
"push", // ARM_INS_PUSH,
|
||||
"qadd", // ARM_INS_QADD,
|
||||
"qadd16", // ARM_INS_QADD16,
|
||||
"qadd8", // ARM_INS_QADD8,
|
||||
"qasx", // ARM_INS_QASX,
|
||||
"qdadd", // ARM_INS_QDADD,
|
||||
"qdsub", // ARM_INS_QDSUB,
|
||||
"qsax", // ARM_INS_QSAX,
|
||||
"qsub", // ARM_INS_QSUB,
|
||||
"qsub16", // ARM_INS_QSUB16,
|
||||
"qsub8", // ARM_INS_QSUB8,
|
||||
"rbit", // ARM_INS_RBIT,
|
||||
"rev", // ARM_INS_REV,
|
||||
"rev16", // ARM_INS_REV16,
|
||||
"revsh", // ARM_INS_REVSH,
|
||||
"rfeda", // ARM_INS_RFEDA,
|
||||
"rfedb", // ARM_INS_RFEDB,
|
||||
"rfeia", // ARM_INS_RFEIA,
|
||||
"rfeib", // ARM_INS_RFEIB,
|
||||
"ror", // ARM_INS_ROR,
|
||||
"rrx", // ARM_INS_RRX,
|
||||
"rsb", // ARM_INS_RSB,
|
||||
"rsc", // ARM_INS_RSC,
|
||||
"sadd16", // ARM_INS_SADD16,
|
||||
"sadd8", // ARM_INS_SADD8,
|
||||
"sasx", // ARM_INS_SASX,
|
||||
"sbc", // ARM_INS_SBC,
|
||||
"sbfx", // ARM_INS_SBFX,
|
||||
"sdiv", // ARM_INS_SDIV,
|
||||
"sel", // ARM_INS_SEL,
|
||||
"setend", // ARM_INS_SETEND,
|
||||
"setpan", // ARM_INS_SETPAN,
|
||||
"sev", // ARM_INS_SEV,
|
||||
"sevl", // ARM_INS_SEVL,
|
||||
"sg", // ARM_INS_SG,
|
||||
"sha1c", // ARM_INS_SHA1C,
|
||||
"sha1h", // ARM_INS_SHA1H,
|
||||
"sha1m", // ARM_INS_SHA1M,
|
||||
"sha1p", // ARM_INS_SHA1P,
|
||||
"sha1su0", // ARM_INS_SHA1SU0,
|
||||
"sha1su1", // ARM_INS_SHA1SU1,
|
||||
"sha256h", // ARM_INS_SHA256H,
|
||||
"sha256h2", // ARM_INS_SHA256H2,
|
||||
"sha256su0", // ARM_INS_SHA256SU0,
|
||||
"sha256su1", // ARM_INS_SHA256SU1,
|
||||
"shadd16", // ARM_INS_SHADD16,
|
||||
"shadd8", // ARM_INS_SHADD8,
|
||||
"shasx", // ARM_INS_SHASX,
|
||||
"shsax", // ARM_INS_SHSAX,
|
||||
"shsub16", // ARM_INS_SHSUB16,
|
||||
"shsub8", // ARM_INS_SHSUB8,
|
||||
"smc", // ARM_INS_SMC,
|
||||
"smlabb", // ARM_INS_SMLABB,
|
||||
"smlabt", // ARM_INS_SMLABT,
|
||||
"smlad", // ARM_INS_SMLAD,
|
||||
"smladx", // ARM_INS_SMLADX,
|
||||
"smlal", // ARM_INS_SMLAL,
|
||||
"smlalbb", // ARM_INS_SMLALBB,
|
||||
"smlalbt", // ARM_INS_SMLALBT,
|
||||
"smlald", // ARM_INS_SMLALD,
|
||||
"smlaldx", // ARM_INS_SMLALDX,
|
||||
"smlaltb", // ARM_INS_SMLALTB,
|
||||
"smlaltt", // ARM_INS_SMLALTT,
|
||||
"smlatb", // ARM_INS_SMLATB,
|
||||
"smlatt", // ARM_INS_SMLATT,
|
||||
"smlawb", // ARM_INS_SMLAWB,
|
||||
"smlawt", // ARM_INS_SMLAWT,
|
||||
"smlsd", // ARM_INS_SMLSD,
|
||||
"smlsdx", // ARM_INS_SMLSDX,
|
||||
"smlsld", // ARM_INS_SMLSLD,
|
||||
"smlsldx", // ARM_INS_SMLSLDX,
|
||||
"smmla", // ARM_INS_SMMLA,
|
||||
"smmlar", // ARM_INS_SMMLAR,
|
||||
"smmls", // ARM_INS_SMMLS,
|
||||
"smmlsr", // ARM_INS_SMMLSR,
|
||||
"smmul", // ARM_INS_SMMUL,
|
||||
"smmulr", // ARM_INS_SMMULR,
|
||||
"smuad", // ARM_INS_SMUAD,
|
||||
"smuadx", // ARM_INS_SMUADX,
|
||||
"smulbb", // ARM_INS_SMULBB,
|
||||
"smulbt", // ARM_INS_SMULBT,
|
||||
"smull", // ARM_INS_SMULL,
|
||||
"smultb", // ARM_INS_SMULTB,
|
||||
"smultt", // ARM_INS_SMULTT,
|
||||
"smulwb", // ARM_INS_SMULWB,
|
||||
"smulwt", // ARM_INS_SMULWT,
|
||||
"smusd", // ARM_INS_SMUSD,
|
||||
"smusdx", // ARM_INS_SMUSDX,
|
||||
"srsda", // ARM_INS_SRSDA,
|
||||
"srsdb", // ARM_INS_SRSDB,
|
||||
"srsia", // ARM_INS_SRSIA,
|
||||
"srsib", // ARM_INS_SRSIB,
|
||||
"ssat", // ARM_INS_SSAT,
|
||||
"ssat16", // ARM_INS_SSAT16,
|
||||
"ssax", // ARM_INS_SSAX,
|
||||
"ssub16", // ARM_INS_SSUB16,
|
||||
"ssub8", // ARM_INS_SSUB8,
|
||||
"stc", // ARM_INS_STC,
|
||||
"stc2", // ARM_INS_STC2,
|
||||
"stc2l", // ARM_INS_STC2L,
|
||||
"stcl", // ARM_INS_STCL,
|
||||
"stl", // ARM_INS_STL,
|
||||
"stlb", // ARM_INS_STLB,
|
||||
"stlex", // ARM_INS_STLEX,
|
||||
"stlexb", // ARM_INS_STLEXB,
|
||||
"stlexd", // ARM_INS_STLEXD,
|
||||
"stlexh", // ARM_INS_STLEXH,
|
||||
"stlh", // ARM_INS_STLH,
|
||||
"stm", // ARM_INS_STM,
|
||||
"stmda", // ARM_INS_STMDA,
|
||||
"stmdb", // ARM_INS_STMDB,
|
||||
"stmib", // ARM_INS_STMIB,
|
||||
"str", // ARM_INS_STR,
|
||||
"strb", // ARM_INS_STRB,
|
||||
"strbt", // ARM_INS_STRBT,
|
||||
"strd", // ARM_INS_STRD,
|
||||
"strex", // ARM_INS_STREX,
|
||||
"strexb", // ARM_INS_STREXB,
|
||||
"strexd", // ARM_INS_STREXD,
|
||||
"strexh", // ARM_INS_STREXH,
|
||||
"strh", // ARM_INS_STRH,
|
||||
"strht", // ARM_INS_STRHT,
|
||||
"strt", // ARM_INS_STRT,
|
||||
"sub", // ARM_INS_SUB,
|
||||
"subs", // ARM_INS_SUBS,
|
||||
"subw", // ARM_INS_SUBW,
|
||||
"svc", // ARM_INS_SVC,
|
||||
"swp", // ARM_INS_SWP,
|
||||
"swpb", // ARM_INS_SWPB,
|
||||
"sxtab", // ARM_INS_SXTAB,
|
||||
"sxtab16", // ARM_INS_SXTAB16,
|
||||
"sxtah", // ARM_INS_SXTAH,
|
||||
"sxtb", // ARM_INS_SXTB,
|
||||
"sxtb16", // ARM_INS_SXTB16,
|
||||
"sxth", // ARM_INS_SXTH,
|
||||
"tbb", // ARM_INS_TBB,
|
||||
"tbh", // ARM_INS_TBH,
|
||||
"teq", // ARM_INS_TEQ,
|
||||
"trap", // ARM_INS_TRAP,
|
||||
"tsb", // ARM_INS_TSB,
|
||||
"tst", // ARM_INS_TST,
|
||||
"tt", // ARM_INS_TT,
|
||||
"tta", // ARM_INS_TTA,
|
||||
"ttat", // ARM_INS_TTAT,
|
||||
"ttt", // ARM_INS_TTT,
|
||||
"uadd16", // ARM_INS_UADD16,
|
||||
"uadd8", // ARM_INS_UADD8,
|
||||
"uasx", // ARM_INS_UASX,
|
||||
"ubfx", // ARM_INS_UBFX,
|
||||
"udf", // ARM_INS_UDF,
|
||||
"udiv", // ARM_INS_UDIV,
|
||||
"uhadd16", // ARM_INS_UHADD16,
|
||||
"uhadd8", // ARM_INS_UHADD8,
|
||||
"uhasx", // ARM_INS_UHASX,
|
||||
"uhsax", // ARM_INS_UHSAX,
|
||||
"uhsub16", // ARM_INS_UHSUB16,
|
||||
"uhsub8", // ARM_INS_UHSUB8,
|
||||
"umaal", // ARM_INS_UMAAL,
|
||||
"umlal", // ARM_INS_UMLAL,
|
||||
"umull", // ARM_INS_UMULL,
|
||||
"uqadd16", // ARM_INS_UQADD16,
|
||||
"uqadd8", // ARM_INS_UQADD8,
|
||||
"uqasx", // ARM_INS_UQASX,
|
||||
"uqsax", // ARM_INS_UQSAX,
|
||||
"uqsub16", // ARM_INS_UQSUB16,
|
||||
"uqsub8", // ARM_INS_UQSUB8,
|
||||
"usad8", // ARM_INS_USAD8,
|
||||
"usada8", // ARM_INS_USADA8,
|
||||
"usat", // ARM_INS_USAT,
|
||||
"usat16", // ARM_INS_USAT16,
|
||||
"usax", // ARM_INS_USAX,
|
||||
"usub16", // ARM_INS_USUB16,
|
||||
"usub8", // ARM_INS_USUB8,
|
||||
"uxtab", // ARM_INS_UXTAB,
|
||||
"uxtab16", // ARM_INS_UXTAB16,
|
||||
"uxtah", // ARM_INS_UXTAH,
|
||||
"uxtb", // ARM_INS_UXTB,
|
||||
"uxtb16", // ARM_INS_UXTB16,
|
||||
"uxth", // ARM_INS_UXTH,
|
||||
"vaba", // ARM_INS_VABA,
|
||||
"vabal", // ARM_INS_VABAL,
|
||||
"vabd", // ARM_INS_VABD,
|
||||
"vabdl", // ARM_INS_VABDL,
|
||||
"vabs", // ARM_INS_VABS,
|
||||
"vacge", // ARM_INS_VACGE,
|
||||
"vacgt", // ARM_INS_VACGT,
|
||||
"vacle", // ARM_INS_VACLE,
|
||||
"vaclt", // ARM_INS_VACLT,
|
||||
"vadd", // ARM_INS_VADD,
|
||||
"vaddhn", // ARM_INS_VADDHN,
|
||||
"vaddl", // ARM_INS_VADDL,
|
||||
"vaddw", // ARM_INS_VADDW,
|
||||
"vand", // ARM_INS_VAND,
|
||||
"vbic", // ARM_INS_VBIC,
|
||||
"vbif", // ARM_INS_VBIF,
|
||||
"vbit", // ARM_INS_VBIT,
|
||||
"vbsl", // ARM_INS_VBSL,
|
||||
"vcadd", // ARM_INS_VCADD,
|
||||
"vceq", // ARM_INS_VCEQ,
|
||||
"vcge", // ARM_INS_VCGE,
|
||||
"vcgt", // ARM_INS_VCGT,
|
||||
"vcle", // ARM_INS_VCLE,
|
||||
"vcls", // ARM_INS_VCLS,
|
||||
"vclt", // ARM_INS_VCLT,
|
||||
"vclz", // ARM_INS_VCLZ,
|
||||
"vcmla", // ARM_INS_VCMLA,
|
||||
"vcmp", // ARM_INS_VCMP,
|
||||
"vcmpe", // ARM_INS_VCMPE,
|
||||
"vcnt", // ARM_INS_VCNT,
|
||||
"vcvt", // ARM_INS_VCVT,
|
||||
"vcvta", // ARM_INS_VCVTA,
|
||||
"vcvtb", // ARM_INS_VCVTB,
|
||||
"vcvtm", // ARM_INS_VCVTM,
|
||||
"vcvtn", // ARM_INS_VCVTN,
|
||||
"vcvtp", // ARM_INS_VCVTP,
|
||||
"vcvtr", // ARM_INS_VCVTR,
|
||||
"vcvtt", // ARM_INS_VCVTT,
|
||||
"vdiv", // ARM_INS_VDIV,
|
||||
"vdup", // ARM_INS_VDUP,
|
||||
"veor", // ARM_INS_VEOR,
|
||||
"vext", // ARM_INS_VEXT,
|
||||
"vfma", // ARM_INS_VFMA,
|
||||
"vfms", // ARM_INS_VFMS,
|
||||
"vfnma", // ARM_INS_VFNMA,
|
||||
"vfnms", // ARM_INS_VFNMS,
|
||||
"vhadd", // ARM_INS_VHADD,
|
||||
"vhsub", // ARM_INS_VHSUB,
|
||||
"vins", // ARM_INS_VINS,
|
||||
"vjcvt", // ARM_INS_VJCVT,
|
||||
"vld1", // ARM_INS_VLD1,
|
||||
"vld2", // ARM_INS_VLD2,
|
||||
"vld3", // ARM_INS_VLD3,
|
||||
"vld4", // ARM_INS_VLD4,
|
||||
"vldmdb", // ARM_INS_VLDMDB,
|
||||
"vldmia", // ARM_INS_VLDMIA,
|
||||
"vldr", // ARM_INS_VLDR,
|
||||
"vlldm", // ARM_INS_VLLDM,
|
||||
"vlstm", // ARM_INS_VLSTM,
|
||||
"vmax", // ARM_INS_VMAX,
|
||||
"vmaxnm", // ARM_INS_VMAXNM,
|
||||
"vmin", // ARM_INS_VMIN,
|
||||
"vminnm", // ARM_INS_VMINNM,
|
||||
"vmla", // ARM_INS_VMLA,
|
||||
"vmlal", // ARM_INS_VMLAL,
|
||||
"vmls", // ARM_INS_VMLS,
|
||||
"vmlsl", // ARM_INS_VMLSL,
|
||||
"vmov", // ARM_INS_VMOV,
|
||||
"vmovl", // ARM_INS_VMOVL,
|
||||
"vmovn", // ARM_INS_VMOVN,
|
||||
"vmovx", // ARM_INS_VMOVX,
|
||||
"vmrs", // ARM_INS_VMRS,
|
||||
"vmsr", // ARM_INS_VMSR,
|
||||
"vmul", // ARM_INS_VMUL,
|
||||
"vmull", // ARM_INS_VMULL,
|
||||
"vmvn", // ARM_INS_VMVN,
|
||||
"vneg", // ARM_INS_VNEG,
|
||||
"vnmla", // ARM_INS_VNMLA,
|
||||
"vnmls", // ARM_INS_VNMLS,
|
||||
"vnmul", // ARM_INS_VNMUL,
|
||||
"vorn", // ARM_INS_VORN,
|
||||
"vorr", // ARM_INS_VORR,
|
||||
"vpadal", // ARM_INS_VPADAL,
|
||||
"vpadd", // ARM_INS_VPADD,
|
||||
"vpaddl", // ARM_INS_VPADDL,
|
||||
"vpmax", // ARM_INS_VPMAX,
|
||||
"vpmin", // ARM_INS_VPMIN,
|
||||
"vpop", // ARM_INS_VPOP,
|
||||
"vpush", // ARM_INS_VPUSH,
|
||||
"vqabs", // ARM_INS_VQABS,
|
||||
"vqadd", // ARM_INS_VQADD,
|
||||
"vqdmlal", // ARM_INS_VQDMLAL,
|
||||
"vqdmlsl", // ARM_INS_VQDMLSL,
|
||||
"vqdmulh", // ARM_INS_VQDMULH,
|
||||
"vqdmull", // ARM_INS_VQDMULL,
|
||||
"vqmovn", // ARM_INS_VQMOVN,
|
||||
"vqmovun", // ARM_INS_VQMOVUN,
|
||||
"vqneg", // ARM_INS_VQNEG,
|
||||
"vqrdmlah", // ARM_INS_VQRDMLAH,
|
||||
"vqrdmlsh", // ARM_INS_VQRDMLSH,
|
||||
"vqrdmulh", // ARM_INS_VQRDMULH,
|
||||
"vqrshl", // ARM_INS_VQRSHL,
|
||||
"vqrshrn", // ARM_INS_VQRSHRN,
|
||||
"vqrshrun", // ARM_INS_VQRSHRUN,
|
||||
"vqshl", // ARM_INS_VQSHL,
|
||||
"vqshlu", // ARM_INS_VQSHLU,
|
||||
"vqshrn", // ARM_INS_VQSHRN,
|
||||
"vqshrun", // ARM_INS_VQSHRUN,
|
||||
"vqsub", // ARM_INS_VQSUB,
|
||||
"vraddhn", // ARM_INS_VRADDHN,
|
||||
"vrecpe", // ARM_INS_VRECPE,
|
||||
"vrecps", // ARM_INS_VRECPS,
|
||||
"vrev16", // ARM_INS_VREV16,
|
||||
"vrev32", // ARM_INS_VREV32,
|
||||
"vrev64", // ARM_INS_VREV64,
|
||||
"vrhadd", // ARM_INS_VRHADD,
|
||||
"vrinta", // ARM_INS_VRINTA,
|
||||
"vrintm", // ARM_INS_VRINTM,
|
||||
"vrintn", // ARM_INS_VRINTN,
|
||||
"vrintp", // ARM_INS_VRINTP,
|
||||
"vrintr", // ARM_INS_VRINTR,
|
||||
"vrintx", // ARM_INS_VRINTX,
|
||||
"vrintz", // ARM_INS_VRINTZ,
|
||||
"vrshl", // ARM_INS_VRSHL,
|
||||
"vrshr", // ARM_INS_VRSHR,
|
||||
"vrshrn", // ARM_INS_VRSHRN,
|
||||
"vrsqrte", // ARM_INS_VRSQRTE,
|
||||
"vrsqrts", // ARM_INS_VRSQRTS,
|
||||
"vrsra", // ARM_INS_VRSRA,
|
||||
"vrsubhn", // ARM_INS_VRSUBHN,
|
||||
"vsdot", // ARM_INS_VSDOT,
|
||||
"vseleq", // ARM_INS_VSELEQ,
|
||||
"vselge", // ARM_INS_VSELGE,
|
||||
"vselgt", // ARM_INS_VSELGT,
|
||||
"vselvs", // ARM_INS_VSELVS,
|
||||
"vshl", // ARM_INS_VSHL,
|
||||
"vshll", // ARM_INS_VSHLL,
|
||||
"vshr", // ARM_INS_VSHR,
|
||||
"vshrn", // ARM_INS_VSHRN,
|
||||
"vsli", // ARM_INS_VSLI,
|
||||
"vsqrt", // ARM_INS_VSQRT,
|
||||
"vsra", // ARM_INS_VSRA,
|
||||
"vsri", // ARM_INS_VSRI,
|
||||
"vst1", // ARM_INS_VST1,
|
||||
"vst2", // ARM_INS_VST2,
|
||||
"vst3", // ARM_INS_VST3,
|
||||
"vst4", // ARM_INS_VST4,
|
||||
"vstmdb", // ARM_INS_VSTMDB,
|
||||
"vstmia", // ARM_INS_VSTMIA,
|
||||
"vstr", // ARM_INS_VSTR,
|
||||
"vsub", // ARM_INS_VSUB,
|
||||
"vsubhn", // ARM_INS_VSUBHN,
|
||||
"vsubl", // ARM_INS_VSUBL,
|
||||
"vsubw", // ARM_INS_VSUBW,
|
||||
"vswp", // ARM_INS_VSWP,
|
||||
"vtbl", // ARM_INS_VTBL,
|
||||
"vtbx", // ARM_INS_VTBX,
|
||||
"vtrn", // ARM_INS_VTRN,
|
||||
"vtst", // ARM_INS_VTST,
|
||||
"vudot", // ARM_INS_VUDOT,
|
||||
"vuzp", // ARM_INS_VUZP,
|
||||
"vzip", // ARM_INS_VZIP,
|
||||
"wfe", // ARM_INS_WFE,
|
||||
"wfi", // ARM_INS_WFI,
|
||||
"yield", // ARM_INS_YIELD,
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,231 @@
|
|||
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
|
||||
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
|
||||
|
||||
/// getRegisterName - This method is automatically generated by tblgen
|
||||
/// from the register set description. This returns the assembler name
|
||||
/// for the specified register.
|
||||
static const char *getRegisterName(unsigned RegNo)
|
||||
{
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const char AsmStrs[] = {
|
||||
/* 0 */ 'D', '4', '_', 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', 0,
|
||||
/* 13 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', '_', 'D', '1', '0', 0,
|
||||
/* 26 */ 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', 0,
|
||||
/* 39 */ 'd', '1', '0', 0,
|
||||
/* 43 */ 'q', '1', '0', 0,
|
||||
/* 47 */ 's', '1', '0', 0,
|
||||
/* 51 */ 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', 0,
|
||||
/* 67 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', '_', 'D', '2', '0', 0,
|
||||
/* 83 */ 'd', '2', '0', 0,
|
||||
/* 87 */ 's', '2', '0', 0,
|
||||
/* 91 */ 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', '_', 'D', '3', '0', 0,
|
||||
/* 107 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', '_', 'D', '3', '0', 0,
|
||||
/* 123 */ 'd', '3', '0', 0,
|
||||
/* 127 */ 's', '3', '0', 0,
|
||||
/* 131 */ 'd', '0', 0,
|
||||
/* 134 */ 'q', '0', 0,
|
||||
/* 137 */ 'm', 'v', 'f', 'r', '0', 0,
|
||||
/* 143 */ 's', '0', 0,
|
||||
/* 146 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', 0,
|
||||
/* 157 */ 'D', '5', '_', 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', 0,
|
||||
/* 170 */ 'Q', '8', '_', 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', 0,
|
||||
/* 184 */ 'R', '1', '0', '_', 'R', '1', '1', 0,
|
||||
/* 192 */ 'd', '1', '1', 0,
|
||||
/* 196 */ 'q', '1', '1', 0,
|
||||
/* 200 */ 's', '1', '1', 0,
|
||||
/* 204 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', 0,
|
||||
/* 216 */ 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', 0,
|
||||
/* 232 */ 'd', '2', '1', 0,
|
||||
/* 236 */ 's', '2', '1', 0,
|
||||
/* 240 */ 'D', '2', '9', '_', 'D', '3', '0', '_', 'D', '3', '1', 0,
|
||||
/* 252 */ 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', '_', 'D', '3', '1', 0,
|
||||
/* 268 */ 'd', '3', '1', 0,
|
||||
/* 272 */ 's', '3', '1', 0,
|
||||
/* 276 */ 'Q', '0', '_', 'Q', '1', 0,
|
||||
/* 282 */ 'R', '0', '_', 'R', '1', 0,
|
||||
/* 288 */ 'd', '1', 0,
|
||||
/* 291 */ 'q', '1', 0,
|
||||
/* 294 */ 'm', 'v', 'f', 'r', '1', 0,
|
||||
/* 300 */ 's', '1', 0,
|
||||
/* 303 */ 'D', '6', '_', 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', 0,
|
||||
/* 317 */ 'D', '9', '_', 'D', '1', '0', '_', 'D', '1', '1', '_', 'D', '1', '2', 0,
|
||||
/* 332 */ 'Q', '9', '_', 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', 0,
|
||||
/* 347 */ 'd', '1', '2', 0,
|
||||
/* 351 */ 'q', '1', '2', 0,
|
||||
/* 355 */ 's', '1', '2', 0,
|
||||
/* 359 */ 'D', '1', '6', '_', 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', 0,
|
||||
/* 375 */ 'D', '1', '9', '_', 'D', '2', '0', '_', 'D', '2', '1', '_', 'D', '2', '2', 0,
|
||||
/* 391 */ 'd', '2', '2', 0,
|
||||
/* 395 */ 's', '2', '2', 0,
|
||||
/* 399 */ 'D', '0', '_', 'D', '2', 0,
|
||||
/* 405 */ 'D', '0', '_', 'D', '1', '_', 'D', '2', 0,
|
||||
/* 414 */ 'Q', '1', '_', 'Q', '2', 0,
|
||||
/* 420 */ 'd', '2', 0,
|
||||
/* 423 */ 'q', '2', 0,
|
||||
/* 426 */ 'm', 'v', 'f', 'r', '2', 0,
|
||||
/* 432 */ 's', '2', 0,
|
||||
/* 435 */ 'f', 'p', 'i', 'n', 's', 't', '2', 0,
|
||||
/* 443 */ 'D', '7', '_', 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', 0,
|
||||
/* 457 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', 0,
|
||||
/* 469 */ 'Q', '1', '0', '_', 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', 0,
|
||||
/* 485 */ 'd', '1', '3', 0,
|
||||
/* 489 */ 'q', '1', '3', 0,
|
||||
/* 493 */ 's', '1', '3', 0,
|
||||
/* 497 */ 'D', '1', '7', '_', 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', 0,
|
||||
/* 513 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', 0,
|
||||
/* 525 */ 'd', '2', '3', 0,
|
||||
/* 529 */ 's', '2', '3', 0,
|
||||
/* 533 */ 'D', '1', '_', 'D', '3', 0,
|
||||
/* 539 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', 0,
|
||||
/* 548 */ 'Q', '0', '_', 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', 0,
|
||||
/* 560 */ 'R', '2', '_', 'R', '3', 0,
|
||||
/* 566 */ 'd', '3', 0,
|
||||
/* 569 */ 'q', '3', 0,
|
||||
/* 572 */ 'r', '3', 0,
|
||||
/* 575 */ 's', '3', 0,
|
||||
/* 578 */ 'D', '8', '_', 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', 0,
|
||||
/* 593 */ 'D', '1', '1', '_', 'D', '1', '2', '_', 'D', '1', '3', '_', 'D', '1', '4', 0,
|
||||
/* 609 */ 'Q', '1', '1', '_', 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', 0,
|
||||
/* 625 */ 'd', '1', '4', 0,
|
||||
/* 629 */ 'q', '1', '4', 0,
|
||||
/* 633 */ 's', '1', '4', 0,
|
||||
/* 637 */ 'D', '1', '8', '_', 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', 0,
|
||||
/* 653 */ 'D', '2', '1', '_', 'D', '2', '2', '_', 'D', '2', '3', '_', 'D', '2', '4', 0,
|
||||
/* 669 */ 'd', '2', '4', 0,
|
||||
/* 673 */ 's', '2', '4', 0,
|
||||
/* 677 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', 0,
|
||||
/* 686 */ 'D', '1', '_', 'D', '2', '_', 'D', '3', '_', 'D', '4', 0,
|
||||
/* 698 */ 'Q', '1', '_', 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', 0,
|
||||
/* 710 */ 'd', '4', 0,
|
||||
/* 713 */ 'q', '4', 0,
|
||||
/* 716 */ 'r', '4', 0,
|
||||
/* 719 */ 's', '4', 0,
|
||||
/* 722 */ 'D', '9', '_', 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', 0,
|
||||
/* 737 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', 0,
|
||||
/* 749 */ 'Q', '1', '2', '_', 'Q', '1', '3', '_', 'Q', '1', '4', '_', 'Q', '1', '5', 0,
|
||||
/* 765 */ 'd', '1', '5', 0,
|
||||
/* 769 */ 'q', '1', '5', 0,
|
||||
/* 773 */ 's', '1', '5', 0,
|
||||
/* 777 */ 'D', '1', '9', '_', 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', 0,
|
||||
/* 793 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', 0,
|
||||
/* 805 */ 'd', '2', '5', 0,
|
||||
/* 809 */ 's', '2', '5', 0,
|
||||
/* 813 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', 0,
|
||||
/* 822 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', 0,
|
||||
/* 831 */ 'Q', '2', '_', 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', 0,
|
||||
/* 843 */ 'R', '4', '_', 'R', '5', 0,
|
||||
/* 849 */ 'd', '5', 0,
|
||||
/* 852 */ 'q', '5', 0,
|
||||
/* 855 */ 'r', '5', 0,
|
||||
/* 858 */ 's', '5', 0,
|
||||
/* 861 */ 'D', '1', '0', '_', 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', 0,
|
||||
/* 877 */ 'D', '1', '3', '_', 'D', '1', '4', '_', 'D', '1', '5', '_', 'D', '1', '6', 0,
|
||||
/* 893 */ 'd', '1', '6', 0,
|
||||
/* 897 */ 's', '1', '6', 0,
|
||||
/* 901 */ 'D', '2', '0', '_', 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', 0,
|
||||
/* 917 */ 'D', '2', '3', '_', 'D', '2', '4', '_', 'D', '2', '5', '_', 'D', '2', '6', 0,
|
||||
/* 933 */ 'd', '2', '6', 0,
|
||||
/* 937 */ 's', '2', '6', 0,
|
||||
/* 941 */ 'D', '0', '_', 'D', '2', '_', 'D', '4', '_', 'D', '6', 0,
|
||||
/* 953 */ 'D', '3', '_', 'D', '4', '_', 'D', '5', '_', 'D', '6', 0,
|
||||
/* 965 */ 'Q', '3', '_', 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', 0,
|
||||
/* 977 */ 'd', '6', 0,
|
||||
/* 980 */ 'q', '6', 0,
|
||||
/* 983 */ 'r', '6', 0,
|
||||
/* 986 */ 's', '6', 0,
|
||||
/* 989 */ 'D', '1', '1', '_', 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', 0,
|
||||
/* 1005 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', 0,
|
||||
/* 1017 */ 'd', '1', '7', 0,
|
||||
/* 1021 */ 's', '1', '7', 0,
|
||||
/* 1025 */ 'D', '2', '1', '_', 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', 0,
|
||||
/* 1041 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', 0,
|
||||
/* 1053 */ 'd', '2', '7', 0,
|
||||
/* 1057 */ 's', '2', '7', 0,
|
||||
/* 1061 */ 'D', '1', '_', 'D', '3', '_', 'D', '5', '_', 'D', '7', 0,
|
||||
/* 1073 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', 0,
|
||||
/* 1082 */ 'Q', '4', '_', 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', 0,
|
||||
/* 1094 */ 'R', '6', '_', 'R', '7', 0,
|
||||
/* 1100 */ 'd', '7', 0,
|
||||
/* 1103 */ 'q', '7', 0,
|
||||
/* 1106 */ 'r', '7', 0,
|
||||
/* 1109 */ 's', '7', 0,
|
||||
/* 1112 */ 'D', '1', '2', '_', 'D', '1', '4', '_', 'D', '1', '6', '_', 'D', '1', '8', 0,
|
||||
/* 1128 */ 'D', '1', '5', '_', 'D', '1', '6', '_', 'D', '1', '7', '_', 'D', '1', '8', 0,
|
||||
/* 1144 */ 'd', '1', '8', 0,
|
||||
/* 1148 */ 's', '1', '8', 0,
|
||||
/* 1152 */ 'D', '2', '2', '_', 'D', '2', '4', '_', 'D', '2', '6', '_', 'D', '2', '8', 0,
|
||||
/* 1168 */ 'D', '2', '5', '_', 'D', '2', '6', '_', 'D', '2', '7', '_', 'D', '2', '8', 0,
|
||||
/* 1184 */ 'd', '2', '8', 0,
|
||||
/* 1188 */ 's', '2', '8', 0,
|
||||
/* 1192 */ 'D', '2', '_', 'D', '4', '_', 'D', '6', '_', 'D', '8', 0,
|
||||
/* 1204 */ 'D', '5', '_', 'D', '6', '_', 'D', '7', '_', 'D', '8', 0,
|
||||
/* 1216 */ 'Q', '5', '_', 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', 0,
|
||||
/* 1228 */ 'd', '8', 0,
|
||||
/* 1231 */ 'q', '8', 0,
|
||||
/* 1234 */ 'r', '8', 0,
|
||||
/* 1237 */ 's', '8', 0,
|
||||
/* 1240 */ 'D', '1', '3', '_', 'D', '1', '5', '_', 'D', '1', '7', '_', 'D', '1', '9', 0,
|
||||
/* 1256 */ 'D', '1', '7', '_', 'D', '1', '8', '_', 'D', '1', '9', 0,
|
||||
/* 1268 */ 'd', '1', '9', 0,
|
||||
/* 1272 */ 's', '1', '9', 0,
|
||||
/* 1276 */ 'D', '2', '3', '_', 'D', '2', '5', '_', 'D', '2', '7', '_', 'D', '2', '9', 0,
|
||||
/* 1292 */ 'D', '2', '7', '_', 'D', '2', '8', '_', 'D', '2', '9', 0,
|
||||
/* 1304 */ 'd', '2', '9', 0,
|
||||
/* 1308 */ 's', '2', '9', 0,
|
||||
/* 1312 */ 'D', '3', '_', 'D', '5', '_', 'D', '7', '_', 'D', '9', 0,
|
||||
/* 1324 */ 'D', '7', '_', 'D', '8', '_', 'D', '9', 0,
|
||||
/* 1333 */ 'Q', '6', '_', 'Q', '7', '_', 'Q', '8', '_', 'Q', '9', 0,
|
||||
/* 1345 */ 'R', '8', '_', 'R', '9', 0,
|
||||
/* 1351 */ 'd', '9', 0,
|
||||
/* 1354 */ 'q', '9', 0,
|
||||
/* 1357 */ 's', '9', 0,
|
||||
/* 1360 */ 'R', '1', '2', '_', 'S', 'P', 0,
|
||||
/* 1367 */ 's', 'b', 0,
|
||||
/* 1370 */ 'p', 'c', 0,
|
||||
/* 1373 */ 'f', 'p', 'e', 'x', 'c', 0,
|
||||
/* 1379 */ 'f', 'p', 's', 'i', 'd', 0,
|
||||
/* 1385 */ 'i', 't', 's', 't', 'a', 't', 'e', 0,
|
||||
/* 1393 */ 's', 'l', 0,
|
||||
/* 1396 */ 'f', 'p', 0,
|
||||
/* 1399 */ 'i', 'p', 0,
|
||||
/* 1402 */ 's', 'p', 0,
|
||||
/* 1405 */ 'f', 'p', 's', 'c', 'r', 0,
|
||||
/* 1411 */ 'l', 'r', 0,
|
||||
/* 1414 */ 'a', 'p', 's', 'r', 0,
|
||||
/* 1419 */ 'c', 'p', 's', 'r', 0,
|
||||
/* 1424 */ 's', 'p', 's', 'r', 0,
|
||||
/* 1429 */ 'f', 'p', 'i', 'n', 's', 't', 0,
|
||||
/* 1436 */ 'f', 'p', 's', 'c', 'r', '_', 'n', 'z', 'c', 'v', 0,
|
||||
/* 1447 */ 'a', 'p', 's', 'r', '_', 'n', 'z', 'c', 'v', 0,
|
||||
};
|
||||
|
||||
static const uint16_t RegAsmOffset[] = {
|
||||
1414, 1447, 1419, 1373, 1429, 1405, 1436, 1379, 1385, 1411, 1370, 1402, 1424, 131,
|
||||
288, 420, 566, 710, 849, 977, 1100, 1228, 1351, 39, 192, 347, 485, 625,
|
||||
765, 893, 1017, 1144, 1268, 83, 232, 391, 525, 669, 805, 933, 1053, 1184,
|
||||
1304, 123, 268, 435, 137, 294, 426, 134, 291, 423, 569, 713, 852, 980,
|
||||
1103, 1231, 1354, 43, 196, 351, 489, 629, 769, 140, 297, 429, 572, 716,
|
||||
855, 983, 1106, 1234, 1367, 1393, 1396, 1399, 143, 300, 432, 575, 719, 858,
|
||||
986, 1109, 1237, 1357, 47, 200, 355, 493, 633, 773, 897, 1021, 1148, 1272,
|
||||
87, 236, 395, 529, 673, 809, 937, 1057, 1188, 1308, 127, 272, 399, 533,
|
||||
680, 816, 947, 1067, 1198, 1318, 6, 163, 309, 449, 585, 729, 869, 997,
|
||||
1120, 1248, 59, 224, 367, 505, 645, 785, 909, 1033, 1160, 1284, 99, 260,
|
||||
276, 414, 554, 704, 837, 971, 1088, 1222, 1339, 32, 176, 339, 477, 617,
|
||||
757, 548, 698, 831, 965, 1082, 1216, 1333, 26, 170, 332, 469, 609, 749,
|
||||
1360, 282, 560, 843, 1094, 1345, 184, 405, 539, 689, 822, 956, 1073, 1207,
|
||||
1324, 16, 146, 320, 457, 597, 737, 881, 1005, 1132, 1256, 71, 204, 379,
|
||||
513, 657, 793, 921, 1041, 1172, 1292, 111, 240, 677, 813, 944, 1064, 1195,
|
||||
1315, 3, 160, 306, 446, 581, 725, 865, 993, 1116, 1244, 55, 220, 363,
|
||||
501, 641, 781, 905, 1029, 1156, 1280, 95, 256, 941, 1061, 1192, 1312, 0,
|
||||
157, 303, 443, 578, 722, 861, 989, 1112, 1240, 51, 216, 359, 497, 637,
|
||||
777, 901, 1025, 1152, 1276, 91, 252, 408, 692, 959, 1210, 19, 324, 601,
|
||||
885, 1136, 75, 383, 661, 925, 1176, 115, 686, 953, 1204, 13, 317, 593,
|
||||
877, 1128, 67, 375, 653, 917, 1168, 107,
|
||||
};
|
||||
|
||||
return AsmStrs+RegAsmOffset[RegNo-1];
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -97,6 +97,17 @@ typedef enum arm_sysreg {
|
|||
ARM_SYSREG_BASEPRI_MAX,
|
||||
ARM_SYSREG_FAULTMASK,
|
||||
ARM_SYSREG_CONTROL,
|
||||
ARM_SYSREG_MSPLIM,
|
||||
ARM_SYSREG_PSPLIM,
|
||||
ARM_SYSREG_MSP_NS,
|
||||
ARM_SYSREG_PSP_NS,
|
||||
ARM_SYSREG_MSPLIM_NS,
|
||||
ARM_SYSREG_PSPLIM_NS,
|
||||
ARM_SYSREG_PRIMASK_NS,
|
||||
ARM_SYSREG_BASEPRI_NS,
|
||||
ARM_SYSREG_FAULTMASK_NS,
|
||||
ARM_SYSREG_CONTROL_NS,
|
||||
ARM_SYSREG_SP_NS,
|
||||
|
||||
// Banked Registers
|
||||
ARM_SYSREG_R8_USR,
|
||||
|
|
@ -218,6 +229,7 @@ typedef enum arm_vectordata_type {
|
|||
ARM_VECTORDATA_P8,
|
||||
|
||||
// Floating type
|
||||
ARM_VECTORDATA_F16,
|
||||
ARM_VECTORDATA_F32,
|
||||
ARM_VECTORDATA_F64,
|
||||
|
||||
|
|
@ -246,6 +258,10 @@ typedef enum arm_vectordata_type {
|
|||
ARM_VECTORDATA_F64U16, // f64.u16
|
||||
ARM_VECTORDATA_F32U16, // f32.u16
|
||||
ARM_VECTORDATA_F64U32, // f64.u32
|
||||
ARM_VECTORDATA_F16U16, // f16.u16
|
||||
ARM_VECTORDATA_U16F16, // u16.f16
|
||||
ARM_VECTORDATA_F16U32, // f16.u32
|
||||
ARM_VECTORDATA_U32F16, // u32.f16
|
||||
} arm_vectordata_type;
|
||||
|
||||
/// ARM registers
|
||||
|
|
@ -445,21 +461,27 @@ typedef enum arm_insn {
|
|||
|
||||
ARM_INS_ADC,
|
||||
ARM_INS_ADD,
|
||||
ARM_INS_ADDW,
|
||||
ARM_INS_ADR,
|
||||
ARM_INS_AESD,
|
||||
ARM_INS_AESE,
|
||||
ARM_INS_AESIMC,
|
||||
ARM_INS_AESMC,
|
||||
ARM_INS_AND,
|
||||
ARM_INS_ASR,
|
||||
ARM_INS_B,
|
||||
ARM_INS_BFC,
|
||||
ARM_INS_BFI,
|
||||
ARM_INS_BIC,
|
||||
ARM_INS_BKPT,
|
||||
ARM_INS_BL,
|
||||
ARM_INS_BLX,
|
||||
ARM_INS_BLXNS,
|
||||
ARM_INS_BX,
|
||||
ARM_INS_BXJ,
|
||||
ARM_INS_B,
|
||||
ARM_INS_BXNS,
|
||||
ARM_INS_CBNZ,
|
||||
ARM_INS_CBZ,
|
||||
ARM_INS_CDP,
|
||||
ARM_INS_CDP2,
|
||||
ARM_INS_CLREX,
|
||||
|
|
@ -473,21 +495,37 @@ typedef enum arm_insn {
|
|||
ARM_INS_CRC32CW,
|
||||
ARM_INS_CRC32H,
|
||||
ARM_INS_CRC32W,
|
||||
ARM_INS_CSDB,
|
||||
ARM_INS_DBG,
|
||||
ARM_INS_DCPS1,
|
||||
ARM_INS_DCPS2,
|
||||
ARM_INS_DCPS3,
|
||||
ARM_INS_DFB,
|
||||
ARM_INS_DMB,
|
||||
ARM_INS_DSB,
|
||||
ARM_INS_EOR,
|
||||
ARM_INS_ERET,
|
||||
ARM_INS_VMOV,
|
||||
ARM_INS_ESB,
|
||||
ARM_INS_FADDD,
|
||||
ARM_INS_FADDS,
|
||||
ARM_INS_FCMPZD,
|
||||
ARM_INS_FCMPZS,
|
||||
ARM_INS_FCONSTD,
|
||||
ARM_INS_FCONSTS,
|
||||
ARM_INS_FLDMDBX,
|
||||
ARM_INS_FLDMIAX,
|
||||
ARM_INS_VMRS,
|
||||
ARM_INS_FMDHR,
|
||||
ARM_INS_FMDLR,
|
||||
ARM_INS_FMSTAT,
|
||||
ARM_INS_FSTMDBX,
|
||||
ARM_INS_FSTMIAX,
|
||||
ARM_INS_FSUBD,
|
||||
ARM_INS_FSUBS,
|
||||
ARM_INS_HINT,
|
||||
ARM_INS_HLT,
|
||||
ARM_INS_HVC,
|
||||
ARM_INS_ISB,
|
||||
ARM_INS_IT,
|
||||
ARM_INS_LDA,
|
||||
ARM_INS_LDAB,
|
||||
ARM_INS_LDAEX,
|
||||
|
|
@ -495,16 +533,17 @@ typedef enum arm_insn {
|
|||
ARM_INS_LDAEXD,
|
||||
ARM_INS_LDAEXH,
|
||||
ARM_INS_LDAH,
|
||||
ARM_INS_LDC2L,
|
||||
ARM_INS_LDC2,
|
||||
ARM_INS_LDCL,
|
||||
ARM_INS_LDC,
|
||||
ARM_INS_LDC2,
|
||||
ARM_INS_LDC2L,
|
||||
ARM_INS_LDCL,
|
||||
ARM_INS_LDM,
|
||||
ARM_INS_LDMDA,
|
||||
ARM_INS_LDMDB,
|
||||
ARM_INS_LDM,
|
||||
ARM_INS_LDMIB,
|
||||
ARM_INS_LDRBT,
|
||||
ARM_INS_LDR,
|
||||
ARM_INS_LDRB,
|
||||
ARM_INS_LDRBT,
|
||||
ARM_INS_LDRD,
|
||||
ARM_INS_LDREX,
|
||||
ARM_INS_LDREXB,
|
||||
|
|
@ -517,7 +556,8 @@ typedef enum arm_insn {
|
|||
ARM_INS_LDRSH,
|
||||
ARM_INS_LDRSHT,
|
||||
ARM_INS_LDRT,
|
||||
ARM_INS_LDR,
|
||||
ARM_INS_LSL,
|
||||
ARM_INS_LSR,
|
||||
ARM_INS_MCR,
|
||||
ARM_INS_MCR2,
|
||||
ARM_INS_MCRR,
|
||||
|
|
@ -525,6 +565,7 @@ typedef enum arm_insn {
|
|||
ARM_INS_MLA,
|
||||
ARM_INS_MLS,
|
||||
ARM_INS_MOV,
|
||||
ARM_INS_MOVS,
|
||||
ARM_INS_MOVT,
|
||||
ARM_INS_MOVW,
|
||||
ARM_INS_MRC,
|
||||
|
|
@ -535,12 +576,17 @@ typedef enum arm_insn {
|
|||
ARM_INS_MSR,
|
||||
ARM_INS_MUL,
|
||||
ARM_INS_MVN,
|
||||
ARM_INS_NEG,
|
||||
ARM_INS_NOP,
|
||||
ARM_INS_ORN,
|
||||
ARM_INS_ORR,
|
||||
ARM_INS_PKHBT,
|
||||
ARM_INS_PKHTB,
|
||||
ARM_INS_PLDW,
|
||||
ARM_INS_PLD,
|
||||
ARM_INS_PLDW,
|
||||
ARM_INS_PLI,
|
||||
ARM_INS_POP,
|
||||
ARM_INS_PUSH,
|
||||
ARM_INS_QADD,
|
||||
ARM_INS_QADD16,
|
||||
ARM_INS_QADD8,
|
||||
|
|
@ -559,6 +605,8 @@ typedef enum arm_insn {
|
|||
ARM_INS_RFEDB,
|
||||
ARM_INS_RFEIA,
|
||||
ARM_INS_RFEIB,
|
||||
ARM_INS_ROR,
|
||||
ARM_INS_RRX,
|
||||
ARM_INS_RSB,
|
||||
ARM_INS_RSC,
|
||||
ARM_INS_SADD16,
|
||||
|
|
@ -569,6 +617,10 @@ typedef enum arm_insn {
|
|||
ARM_INS_SDIV,
|
||||
ARM_INS_SEL,
|
||||
ARM_INS_SETEND,
|
||||
ARM_INS_SETPAN,
|
||||
ARM_INS_SEV,
|
||||
ARM_INS_SEVL,
|
||||
ARM_INS_SG,
|
||||
ARM_INS_SHA1C,
|
||||
ARM_INS_SHA1H,
|
||||
ARM_INS_SHA1M,
|
||||
|
|
@ -631,10 +683,10 @@ typedef enum arm_insn {
|
|||
ARM_INS_SSAX,
|
||||
ARM_INS_SSUB16,
|
||||
ARM_INS_SSUB8,
|
||||
ARM_INS_STC2L,
|
||||
ARM_INS_STC2,
|
||||
ARM_INS_STCL,
|
||||
ARM_INS_STC,
|
||||
ARM_INS_STC2,
|
||||
ARM_INS_STC2L,
|
||||
ARM_INS_STCL,
|
||||
ARM_INS_STL,
|
||||
ARM_INS_STLB,
|
||||
ARM_INS_STLEX,
|
||||
|
|
@ -642,12 +694,13 @@ typedef enum arm_insn {
|
|||
ARM_INS_STLEXD,
|
||||
ARM_INS_STLEXH,
|
||||
ARM_INS_STLH,
|
||||
ARM_INS_STM,
|
||||
ARM_INS_STMDA,
|
||||
ARM_INS_STMDB,
|
||||
ARM_INS_STM,
|
||||
ARM_INS_STMIB,
|
||||
ARM_INS_STRBT,
|
||||
ARM_INS_STR,
|
||||
ARM_INS_STRB,
|
||||
ARM_INS_STRBT,
|
||||
ARM_INS_STRD,
|
||||
ARM_INS_STREX,
|
||||
ARM_INS_STREXB,
|
||||
|
|
@ -656,8 +709,9 @@ typedef enum arm_insn {
|
|||
ARM_INS_STRH,
|
||||
ARM_INS_STRHT,
|
||||
ARM_INS_STRT,
|
||||
ARM_INS_STR,
|
||||
ARM_INS_SUB,
|
||||
ARM_INS_SUBS,
|
||||
ARM_INS_SUBW,
|
||||
ARM_INS_SVC,
|
||||
ARM_INS_SWP,
|
||||
ARM_INS_SWPB,
|
||||
|
|
@ -667,9 +721,16 @@ typedef enum arm_insn {
|
|||
ARM_INS_SXTB,
|
||||
ARM_INS_SXTB16,
|
||||
ARM_INS_SXTH,
|
||||
ARM_INS_TBB,
|
||||
ARM_INS_TBH,
|
||||
ARM_INS_TEQ,
|
||||
ARM_INS_TRAP,
|
||||
ARM_INS_TSB,
|
||||
ARM_INS_TST,
|
||||
ARM_INS_TT,
|
||||
ARM_INS_TTA,
|
||||
ARM_INS_TTAT,
|
||||
ARM_INS_TTT,
|
||||
ARM_INS_UADD16,
|
||||
ARM_INS_UADD8,
|
||||
ARM_INS_UASX,
|
||||
|
|
@ -704,13 +765,15 @@ typedef enum arm_insn {
|
|||
ARM_INS_UXTB,
|
||||
ARM_INS_UXTB16,
|
||||
ARM_INS_UXTH,
|
||||
ARM_INS_VABAL,
|
||||
ARM_INS_VABA,
|
||||
ARM_INS_VABDL,
|
||||
ARM_INS_VABAL,
|
||||
ARM_INS_VABD,
|
||||
ARM_INS_VABDL,
|
||||
ARM_INS_VABS,
|
||||
ARM_INS_VACGE,
|
||||
ARM_INS_VACGT,
|
||||
ARM_INS_VACLE,
|
||||
ARM_INS_VACLT,
|
||||
ARM_INS_VADD,
|
||||
ARM_INS_VADDHN,
|
||||
ARM_INS_VADDL,
|
||||
|
|
@ -720,6 +783,7 @@ typedef enum arm_insn {
|
|||
ARM_INS_VBIF,
|
||||
ARM_INS_VBIT,
|
||||
ARM_INS_VBSL,
|
||||
ARM_INS_VCADD,
|
||||
ARM_INS_VCEQ,
|
||||
ARM_INS_VCGE,
|
||||
ARM_INS_VCGT,
|
||||
|
|
@ -727,15 +791,17 @@ typedef enum arm_insn {
|
|||
ARM_INS_VCLS,
|
||||
ARM_INS_VCLT,
|
||||
ARM_INS_VCLZ,
|
||||
ARM_INS_VCMLA,
|
||||
ARM_INS_VCMP,
|
||||
ARM_INS_VCMPE,
|
||||
ARM_INS_VCNT,
|
||||
ARM_INS_VCVT,
|
||||
ARM_INS_VCVTA,
|
||||
ARM_INS_VCVTB,
|
||||
ARM_INS_VCVT,
|
||||
ARM_INS_VCVTM,
|
||||
ARM_INS_VCVTN,
|
||||
ARM_INS_VCVTP,
|
||||
ARM_INS_VCVTR,
|
||||
ARM_INS_VCVTT,
|
||||
ARM_INS_VDIV,
|
||||
ARM_INS_VDUP,
|
||||
|
|
@ -747,6 +813,8 @@ typedef enum arm_insn {
|
|||
ARM_INS_VFNMS,
|
||||
ARM_INS_VHADD,
|
||||
ARM_INS_VHSUB,
|
||||
ARM_INS_VINS,
|
||||
ARM_INS_VJCVT,
|
||||
ARM_INS_VLD1,
|
||||
ARM_INS_VLD2,
|
||||
ARM_INS_VLD3,
|
||||
|
|
@ -754,16 +822,21 @@ typedef enum arm_insn {
|
|||
ARM_INS_VLDMDB,
|
||||
ARM_INS_VLDMIA,
|
||||
ARM_INS_VLDR,
|
||||
ARM_INS_VMAXNM,
|
||||
ARM_INS_VLLDM,
|
||||
ARM_INS_VLSTM,
|
||||
ARM_INS_VMAX,
|
||||
ARM_INS_VMINNM,
|
||||
ARM_INS_VMAXNM,
|
||||
ARM_INS_VMIN,
|
||||
ARM_INS_VMINNM,
|
||||
ARM_INS_VMLA,
|
||||
ARM_INS_VMLAL,
|
||||
ARM_INS_VMLS,
|
||||
ARM_INS_VMLSL,
|
||||
ARM_INS_VMOV,
|
||||
ARM_INS_VMOVL,
|
||||
ARM_INS_VMOVN,
|
||||
ARM_INS_VMOVX,
|
||||
ARM_INS_VMRS,
|
||||
ARM_INS_VMSR,
|
||||
ARM_INS_VMUL,
|
||||
ARM_INS_VMULL,
|
||||
|
|
@ -775,19 +848,23 @@ typedef enum arm_insn {
|
|||
ARM_INS_VORN,
|
||||
ARM_INS_VORR,
|
||||
ARM_INS_VPADAL,
|
||||
ARM_INS_VPADDL,
|
||||
ARM_INS_VPADD,
|
||||
ARM_INS_VPADDL,
|
||||
ARM_INS_VPMAX,
|
||||
ARM_INS_VPMIN,
|
||||
ARM_INS_VPOP,
|
||||
ARM_INS_VPUSH,
|
||||
ARM_INS_VQABS,
|
||||
ARM_INS_VQADD,
|
||||
ARM_INS_VQDMLAL,
|
||||
ARM_INS_VQDMLSL,
|
||||
ARM_INS_VQDMULH,
|
||||
ARM_INS_VQDMULL,
|
||||
ARM_INS_VQMOVUN,
|
||||
ARM_INS_VQMOVN,
|
||||
ARM_INS_VQMOVUN,
|
||||
ARM_INS_VQNEG,
|
||||
ARM_INS_VQRDMLAH,
|
||||
ARM_INS_VQRDMLSH,
|
||||
ARM_INS_VQRDMULH,
|
||||
ARM_INS_VQRSHL,
|
||||
ARM_INS_VQRSHRN,
|
||||
|
|
@ -812,20 +889,21 @@ typedef enum arm_insn {
|
|||
ARM_INS_VRINTX,
|
||||
ARM_INS_VRINTZ,
|
||||
ARM_INS_VRSHL,
|
||||
ARM_INS_VRSHRN,
|
||||
ARM_INS_VRSHR,
|
||||
ARM_INS_VRSHRN,
|
||||
ARM_INS_VRSQRTE,
|
||||
ARM_INS_VRSQRTS,
|
||||
ARM_INS_VRSRA,
|
||||
ARM_INS_VRSUBHN,
|
||||
ARM_INS_VSDOT,
|
||||
ARM_INS_VSELEQ,
|
||||
ARM_INS_VSELGE,
|
||||
ARM_INS_VSELGT,
|
||||
ARM_INS_VSELVS,
|
||||
ARM_INS_VSHLL,
|
||||
ARM_INS_VSHL,
|
||||
ARM_INS_VSHRN,
|
||||
ARM_INS_VSHLL,
|
||||
ARM_INS_VSHR,
|
||||
ARM_INS_VSHRN,
|
||||
ARM_INS_VSLI,
|
||||
ARM_INS_VSQRT,
|
||||
ARM_INS_VSRA,
|
||||
|
|
@ -844,39 +922,14 @@ typedef enum arm_insn {
|
|||
ARM_INS_VSWP,
|
||||
ARM_INS_VTBL,
|
||||
ARM_INS_VTBX,
|
||||
ARM_INS_VCVTR,
|
||||
ARM_INS_VTRN,
|
||||
ARM_INS_VTST,
|
||||
ARM_INS_VUDOT,
|
||||
ARM_INS_VUZP,
|
||||
ARM_INS_VZIP,
|
||||
ARM_INS_ADDW,
|
||||
ARM_INS_ASR,
|
||||
ARM_INS_DCPS1,
|
||||
ARM_INS_DCPS2,
|
||||
ARM_INS_DCPS3,
|
||||
ARM_INS_IT,
|
||||
ARM_INS_LSL,
|
||||
ARM_INS_LSR,
|
||||
ARM_INS_ORN,
|
||||
ARM_INS_ROR,
|
||||
ARM_INS_RRX,
|
||||
ARM_INS_SUBW,
|
||||
ARM_INS_TBB,
|
||||
ARM_INS_TBH,
|
||||
ARM_INS_CBNZ,
|
||||
ARM_INS_CBZ,
|
||||
ARM_INS_POP,
|
||||
ARM_INS_PUSH,
|
||||
|
||||
// special instructions
|
||||
ARM_INS_NOP,
|
||||
ARM_INS_YIELD,
|
||||
ARM_INS_WFE,
|
||||
ARM_INS_WFI,
|
||||
ARM_INS_SEV,
|
||||
ARM_INS_SEVL,
|
||||
ARM_INS_VPUSH,
|
||||
ARM_INS_VPOP,
|
||||
ARM_INS_YIELD,
|
||||
|
||||
ARM_INS_ENDING, // <-- mark the end of the list of instructions
|
||||
} arm_insn;
|
||||
|
|
|
|||
|
|
@ -45,7 +45,7 @@
|
|||
0xb0,0x30,0xd4,0xe1 = ldrh r3, [r4]
|
||||
0xb4,0x20,0xd7,0xe1 = ldrh r2, [r7, #4]
|
||||
0xb0,0x14,0xf8,0xe1 = ldrh r1, [r8, #64]!
|
||||
0xb4,0xc0,0xdd,0xe0 = ldrh r12, [sp], #4
|
||||
0xb4,0xc0,0xdd,0xe0 = ldrh ip, [sp], #4
|
||||
0xb4,0x60,0x95,0xe1 = ldrh r6, [r5, r4]
|
||||
0xbb,0x30,0xb8,0xe1 = ldrh r3, [r8, r11]!
|
||||
0xb1,0x10,0x32,0xe1 = ldrh r1, [r2, -r1]!
|
||||
|
|
@ -58,7 +58,7 @@
|
|||
0xd0,0x30,0xd4,0xe1 = ldrsb r3, [r4]
|
||||
0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #17]
|
||||
0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #255]!
|
||||
0xd9,0xc0,0xdd,0xe0 = ldrsb r12, [sp], #9
|
||||
0xd9,0xc0,0xdd,0xe0 = ldrsb ip, [sp], #9
|
||||
0xd4,0x60,0x95,0xe1 = ldrsb r6, [r5, r4]
|
||||
0xdb,0x30,0xb8,0xe1 = ldrsb r3, [r8, r11]!
|
||||
0xd1,0x10,0x32,0xe1 = ldrsb r1, [r2, -r1]!
|
||||
|
|
@ -84,7 +84,7 @@
|
|||
0x00,0x80,0x8c,0xe5 = str r8, [r12]
|
||||
0x0c,0x70,0x81,0xe5 = str r7, [r1, #12]
|
||||
0x28,0x30,0xa5,0xe5 = str r3, [r5, #40]!
|
||||
0xff,0x9f,0x8d,0xe4 = str r9, [sp], #4095
|
||||
0xff,0x9f,0x8d,0xe4 = str sb, [sp], #4095
|
||||
0x80,0x10,0x07,0xe4 = str r1, [r7], #-128
|
||||
0x00,0x10,0x00,0xe4 = str r1, [r0], #-0
|
||||
0x03,0x90,0x86,0xe7 = str r9, [r6, r3]
|
||||
|
|
@ -126,7 +126,7 @@
|
|||
0xb0,0x30,0xc4,0xe1 = strh r3, [r4]
|
||||
0xb4,0x20,0xc7,0xe1 = strh r2, [r7, #4]
|
||||
0xb0,0x14,0xe8,0xe1 = strh r1, [r8, #64]!
|
||||
0xb4,0xc0,0xcd,0xe0 = strh r12, [sp], #4
|
||||
0xb4,0xc0,0xcd,0xe0 = strh ip, [sp], #4
|
||||
0xb4,0x60,0x85,0xe1 = strh r6, [r5, r4]
|
||||
0xbb,0x30,0xa8,0xe1 = strh r3, [r8, r11]!
|
||||
0xb1,0x10,0x22,0xe1 = strh r1, [r2, -r1]!
|
||||
|
|
|
|||
|
|
@ -216,7 +216,6 @@
|
|||
0x4f,0xf0,0x7f,0xf5 = dsb sy
|
||||
0x4e,0xf0,0x7f,0xf5 = dsb st
|
||||
0x4d,0xf0,0x7f,0xf5 = dsb #0xd
|
||||
0x4c,0xf0,0x7f,0xf5 = dsb #0xc
|
||||
0x4b,0xf0,0x7f,0xf5 = dsb ish
|
||||
0x4a,0xf0,0x7f,0xf5 = dsb ishst
|
||||
0x49,0xf0,0x7f,0xf5 = dsb #0x9
|
||||
|
|
@ -483,7 +482,7 @@
|
|||
0x13,0x20,0x82,0xe6 = pkhbt r2, r2, r3
|
||||
0xd3,0x2f,0x82,0xe6 = pkhtb r2, r2, r3, asr #31
|
||||
0xd3,0x27,0x82,0xe6 = pkhtb r2, r2, r3, asr #15
|
||||
0x04,0x70,0x9d,0xe4 = pop {r7}
|
||||
// 0x04,0x70,0x9d,0xe4 = pop {r7}
|
||||
0x80,0x07,0xbd,0xe8 = pop {r7, r8, r9, r10}
|
||||
#0x04,0x70,0x2d,0xe5 = push {r7}
|
||||
0x80,0x07,0x2d,0xe9 = push {r7, r8, r9, r10}
|
||||
|
|
@ -805,7 +804,7 @@
|
|||
0x7a,0x01,0x06,0xe9 = stmdb r6, {r1, r3, r4, r5, r6, r8}
|
||||
0x7a,0x20,0x0d,0xe9 = stmdb sp, {r1, r3, r4, r5, r6, sp}
|
||||
0x7a,0x20,0xa8,0xe8 = stm r8!, {r1, r3, r4, r5, r6, sp}
|
||||
0x7a,0x20,0xa9,0xe9 = stmib r9!, {r1, r3, r4, r5, r6, sp}
|
||||
0x7a,0x20,0xa9,0xe9 = stmib sb!, {r1, r3, r4, r5, r6, sp}
|
||||
0x7a,0x00,0x2d,0xe8 = stmda sp!, {r1, r3, r4, r5, r6}
|
||||
0xa2,0x20,0x20,0xe9 = stmdb r0!, {r1, r5, r7, sp}
|
||||
0x93,0x1f,0xc4,0xe1 = strexb r1, r3, [r4]
|
||||
|
|
|
|||
|
|
@ -16,7 +16,7 @@
|
|||
0x51,0xeb,0xc3,0x10 = adcs.w r0, r1, r3, lsl #7
|
||||
0x41,0xeb,0xd3,0x70 = adc.w r0, r1, r3, lsr #31
|
||||
0x51,0xeb,0x23,0x00 = adcs.w r0, r1, r3, asr #32
|
||||
0x0d,0xeb,0x0c,0x02 = add.w r2, sp, r12
|
||||
0x0d,0xeb,0x0c,0x02 = add.w r2, sp, ip
|
||||
0x0a,0xbf = itet eq
|
||||
// 0x03,0xf2,0xff,0x35 = addwne r5, r3, #1023
|
||||
// 0x05,0xf2,0x25,0x14 = addweq r4, r5, #293
|
||||
|
|
@ -171,7 +171,6 @@
|
|||
0xbf,0xf3,0x4f,0x8f = dsb sy
|
||||
0xbf,0xf3,0x4e,0x8f = dsb st
|
||||
0xbf,0xf3,0x4d,0x8f = dsb #0xd
|
||||
0xbf,0xf3,0x4c,0x8f = dsb #0xc
|
||||
0xbf,0xf3,0x4b,0x8f = dsb ish
|
||||
0xbf,0xf3,0x4a,0x8f = dsb ishst
|
||||
0xbf,0xf3,0x49,0x8f = dsb #0x9
|
||||
|
|
@ -529,7 +528,7 @@
|
|||
// 0xda,0x43 = mvneq r2, r3
|
||||
0xc2,0xf1,0x00,0x05 = rsb.w r5, r2, #0
|
||||
0xc8,0xf1,0x00,0x05 = rsb.w r5, r8, #0
|
||||
0xaf,0xf3,0x00,0x80 = nop.w
|
||||
0xaf,0xf3,0x00,0x80 = nop.ww
|
||||
0x65,0xf4,0x70,0x44 = orn r4, r5, #61440
|
||||
0x65,0xea,0x06,0x04 = orn r4, r5, r6
|
||||
0x75,0xea,0x06,0x04 = orns r4, r5, r6
|
||||
|
|
@ -931,7 +930,7 @@
|
|||
0x62,0xe8,0x00,0x01 = strd r0, r1, [r2], #-0
|
||||
0x44,0xe8,0x00,0x81 = strex r1, r8, [r4]
|
||||
0x44,0xe8,0x00,0x28 = strex r8, r2, [r4]
|
||||
0x4d,0xe8,0x20,0xc2 = strex r2, r12, [sp, #128]
|
||||
0x4d,0xe8,0x20,0xc2 = strex r2, ip, [sp, #128]
|
||||
0xc7,0xe8,0x45,0x1f = strexb r5, r1, [r7]
|
||||
0xcc,0xe8,0x59,0x7f = strexh r9, r7, [r12]
|
||||
0xc4,0xe8,0x79,0x36 = strexd r9, r3, r6, [r4]
|
||||
|
|
@ -982,12 +981,10 @@
|
|||
0xa5,0xeb,0x66,0x14 = sub.w r4, r5, r6, asr #5
|
||||
0xa5,0xeb,0x76,0x14 = sub.w r4, r5, r6, ror #5
|
||||
0xa2,0xeb,0x3c,0x05 = sub.w r5, r2, r12, rrx
|
||||
0xad,0xeb,0x0c,0x02 = sub.w r2, sp, r12
|
||||
0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
|
||||
0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
|
||||
0xad,0xeb,0x0c,0x02 = sub.w r2, sp, r12
|
||||
0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
|
||||
0xad,0xeb,0x0c,0x0d = sub.w sp, sp, r12
|
||||
0xad,0xeb,0x0c,0x02 = sub.w r2, sp, ip
|
||||
0xad,0xeb,0x0c,0x0d = sub.w sp, sp, ip
|
||||
0xad,0xeb,0x0c,0x02 = sub.w r2, sp, ip
|
||||
0xad,0xeb,0x0c,0x0d = sub.w sp, sp, ip
|
||||
0x00,0xdf = svc #0
|
||||
0x0c,0xbf = ite eq
|
||||
// 0xff,0xdf = svceq #255
|
||||
|
|
@ -1204,10 +1201,10 @@
|
|||
// 0x30,0xbf = wfige
|
||||
// 0x10,0xbf = yieldlt
|
||||
// 0xaf,0xf3,0x04,0x80 = sev.w
|
||||
0xaf,0xf3,0x03,0x80 = wfi.w
|
||||
0xaf,0xf3,0x02,0x80 = wfe.w
|
||||
0xaf,0xf3,0x01,0x80 = yield.w
|
||||
0xaf,0xf3,0x00,0x80 = nop.w
|
||||
0xaf,0xf3,0x03,0x80 = wfi.ww
|
||||
0xaf,0xf3,0x02,0x80 = wfe.ww
|
||||
0xaf,0xf3,0x01,0x80 = yield.ww
|
||||
0xaf,0xf3,0x00,0x80 = nop.ww
|
||||
0x40,0xbf = sev
|
||||
// 0x30,0xbf = wfi
|
||||
// 0x20,0xbf = wfe
|
||||
|
|
|
|||
|
|
@ -0,0 +1,36 @@
|
|||
# CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8, None
|
||||
0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
|
||||
0xe0,0x0b,0x71,0xee = vsub.f64 d16, d17, d16
|
||||
0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16
|
||||
0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7
|
||||
0xa0,0x0b,0x61,0xee = vmul.f64 d16, d17, d16
|
||||
0xa1,0x4b,0x64,0xee = vmul.f64 d20, d20, d17
|
||||
0xe0,0x0b,0x61,0xee = vnmul.f64 d16, d17, d16
|
||||
0xe0,0x1b,0xf4,0xee = vcmpe.f64 d17, d16
|
||||
0xc0,0x0b,0xf5,0xee = vcmpe.f64 d16, #0
|
||||
0xe0,0x0b,0xf0,0xee = vabs.f64 d16, d16
|
||||
0xe0,0x0b,0xb7,0xee = vcvt.f32.f64 s0, d16
|
||||
0xc0,0x0a,0xf7,0xee = vcvt.f64.f32 d16, s0
|
||||
0x60,0x0b,0xf1,0xee = vneg.f64 d16, d16
|
||||
0xe0,0x0b,0xf1,0xee = vsqrt.f64 d16, d16
|
||||
0xc0,0x0b,0xf8,0xee = vcvt.f64.s32 d16, s0
|
||||
0x40,0x0b,0xf8,0xee = vcvt.f64.u32 d16, s0
|
||||
0xe0,0x0b,0xbd,0xee = vcvt.s32.f64 s0, d16
|
||||
0xe0,0x0b,0xbc,0xee = vcvt.u32.f64 s0, d16
|
||||
0xa1,0x0b,0x42,0xee = vmla.f64 d16, d18, d17
|
||||
0xe1,0x0b,0x42,0xee = vmls.f64 d16, d18, d17
|
||||
0xe1,0x0b,0x52,0xee = vnmla.f64 d16, d18, d17
|
||||
0xa1,0x0b,0x52,0xee = vnmls.f64 d16, d18, d17
|
||||
0x60,0x0b,0xf1,0x1e = vnegne.f64 d16, d16
|
||||
0x08,0x0b,0xf0,0xee = vmov.f64 d16, #3.000000e+00
|
||||
0x08,0x0b,0xf8,0xee = vmov.f64 d16, #-3.000000e+00
|
||||
0x40,0x0b,0xbd,0xee = vcvtr.s32.f64 s0, d0
|
||||
0x40,0x0b,0xbc,0xee = vcvtr.u32.f64 s0, d0
|
||||
0xc0,0x0b,0xba,0xee = vcvt.f64.s32 d0, d0, #32
|
||||
0x40,0x0b,0xba,0xee = vcvt.f64.s16 d0, d0, #16
|
||||
0xc0,0x4b,0xfb,0xee = vcvt.f64.u32 d20, d20, #32
|
||||
0x40,0x7b,0xfb,0xee = vcvt.f64.u16 d23, d23, #16
|
||||
0xc0,0x2b,0xbe,0xee = vcvt.s32.f64 d2, d2, #32
|
||||
0x40,0xfb,0xbe,0xee = vcvt.s16.f64 d15, d15, #16
|
||||
0xc0,0x4b,0xff,0xee = vcvt.u32.f64 d20, d20, #32
|
||||
0x40,0x7b,0xff,0xee = vcvt.u16.f64 d23, d23, #16
|
||||
|
|
@ -1,45 +1,23 @@
|
|||
# CS_ARCH_ARM, CS_MODE_ARM, None
|
||||
0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
|
||||
0x80,0x0a,0x30,0xee = vadd.f32 s0, s1, s0
|
||||
0xe0,0x0b,0x71,0xee = vsub.f64 d16, d17, d16
|
||||
0xc0,0x0a,0x30,0xee = vsub.f32 s0, s1, s0
|
||||
0xa0,0x0b,0xc1,0xee = vdiv.f64 d16, d17, d16
|
||||
0x80,0x0a,0x80,0xee = vdiv.f32 s0, s1, s0
|
||||
0xa3,0x2a,0xc2,0xee = vdiv.f32 s5, s5, s7
|
||||
0x07,0x5b,0x85,0xee = vdiv.f64 d5, d5, d7
|
||||
0xa0,0x0b,0x61,0xee = vmul.f64 d16, d17, d16
|
||||
0xa1,0x4b,0x64,0xee = vmul.f64 d20, d20, d17
|
||||
0x80,0x0a,0x20,0xee = vmul.f32 s0, s1, s0
|
||||
0xaa,0x5a,0x65,0xee = vmul.f32 s11, s11, s21
|
||||
0xe0,0x0b,0x61,0xee = vnmul.f64 d16, d17, d16
|
||||
0xc0,0x0a,0x20,0xee = vnmul.f32 s0, s1, s0
|
||||
0xe0,0x1b,0xf4,0xee = vcmpe.f64 d17, d16
|
||||
0xc0,0x0a,0xf4,0xee = vcmpe.f32 s1, s0
|
||||
0xc0,0x0b,0xf5,0xee = vcmpe.f64 d16, #0
|
||||
0xc0,0x0a,0xb5,0xee = vcmpe.f32 s0, #0
|
||||
0xe0,0x0b,0xf0,0xee = vabs.f64 d16, d16
|
||||
0xc0,0x0a,0xb0,0xee = vabs.f32 s0, s0
|
||||
0xe0,0x0b,0xb7,0xee = vcvt.f32.f64 s0, d16
|
||||
0xc0,0x0a,0xf7,0xee = vcvt.f64.f32 d16, s0
|
||||
0x60,0x0b,0xf1,0xee = vneg.f64 d16, d16
|
||||
0x40,0x0a,0xb1,0xee = vneg.f32 s0, s0
|
||||
0xe0,0x0b,0xf1,0xee = vsqrt.f64 d16, d16
|
||||
0xc0,0x0a,0xb1,0xee = vsqrt.f32 s0, s0
|
||||
0xc0,0x0b,0xf8,0xee = vcvt.f64.s32 d16, s0
|
||||
0xc0,0x0a,0xb8,0xee = vcvt.f32.s32 s0, s0
|
||||
0x40,0x0b,0xf8,0xee = vcvt.f64.u32 d16, s0
|
||||
0x40,0x0a,0xb8,0xee = vcvt.f32.u32 s0, s0
|
||||
0xe0,0x0b,0xbd,0xee = vcvt.s32.f64 s0, d16
|
||||
0xc0,0x0a,0xbd,0xee = vcvt.s32.f32 s0, s0
|
||||
0xe0,0x0b,0xbc,0xee = vcvt.u32.f64 s0, d16
|
||||
0xc0,0x0a,0xbc,0xee = vcvt.u32.f32 s0, s0
|
||||
0xa1,0x0b,0x42,0xee = vmla.f64 d16, d18, d17
|
||||
0x00,0x0a,0x41,0xee = vmla.f32 s1, s2, s0
|
||||
0xe1,0x0b,0x42,0xee = vmls.f64 d16, d18, d17
|
||||
0x40,0x0a,0x41,0xee = vmls.f32 s1, s2, s0
|
||||
0xe1,0x0b,0x52,0xee = vnmla.f64 d16, d18, d17
|
||||
0x40,0x0a,0x51,0xee = vnmla.f32 s1, s2, s0
|
||||
0xa1,0x0b,0x52,0xee = vnmls.f64 d16, d18, d17
|
||||
0x00,0x0a,0x51,0xee = vnmls.f32 s1, s2, s0
|
||||
0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr
|
||||
0x10,0xfa,0xf1,0xee = vmrs APSR_nzcv, fpscr
|
||||
|
|
@ -48,7 +26,6 @@
|
|||
0x10,0x3a,0xf0,0xee = vmrs r3, fpsid
|
||||
0x10,0x4a,0xf7,0xee = vmrs r4, mvfr0
|
||||
0x10,0x5a,0xf6,0xee = vmrs r5, mvfr1
|
||||
0x60,0x0b,0xf1,0x1e = vnegne.f64 d16, d16
|
||||
0x10,0x0a,0x00,0x1e = vmovne s0, r0
|
||||
0x10,0x1a,0x00,0x0e = vmoveq s0, r1
|
||||
0x10,0x1a,0x11,0xee = vmov r1, s2
|
||||
|
|
@ -65,9 +42,7 @@
|
|||
0x10,0x0a,0xe0,0xee = vmsr fpsid, r0
|
||||
0x10,0x3a,0xe9,0xee = vmsr fpinst, r3
|
||||
0x10,0x4a,0xea,0xee = vmsr fpinst2, r4
|
||||
0x08,0x0b,0xf0,0xee = vmov.f64 d16, #3.000000e+00
|
||||
0x08,0x0a,0xb0,0xee = vmov.f32 s0, #3.000000e+00
|
||||
0x08,0x0b,0xf8,0xee = vmov.f64 d16, #-3.000000e+00
|
||||
0x08,0x0a,0xb8,0xee = vmov.f32 s0, #-3.000000e+00
|
||||
0x10,0x0a,0x00,0xee = vmov s0, r0
|
||||
0x90,0x1a,0x00,0xee = vmov s1, r1
|
||||
|
|
@ -121,9 +96,7 @@
|
|||
0x11,0x0b,0xa5,0xec = fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7}
|
||||
0x05,0x8b,0x84,0x0c = fstmiaxeq r4, {d8, d9}
|
||||
0x07,0x2b,0x27,0x1d = fstmdbxne r7!, {d2, d3, d4}
|
||||
0x40,0x0b,0xbd,0xee = vcvtr.s32.f64 s0, d0
|
||||
0x60,0x0a,0xbd,0xee = vcvtr.s32.f32 s0, s1
|
||||
0x40,0x0b,0xbc,0xee = vcvtr.u32.f64 s0, d0
|
||||
0x60,0x0a,0xbc,0xee = vcvtr.u32.f32 s0, s1
|
||||
0x90,0x8a,0x00,0xee = vmov s1, r8
|
||||
0x10,0x4a,0x01,0xee = vmov s2, r4
|
||||
|
|
@ -138,20 +111,12 @@
|
|||
0x10,0x5a,0x11,0xee = vmov r5, s2
|
||||
0x90,0x6a,0x11,0xee = vmov r6, s3
|
||||
0xc6,0x0a,0xbb,0xee = vcvt.f32.u32 s0, s0, #20
|
||||
0xc0,0x0b,0xba,0xee = vcvt.f64.s32 d0, d0, #32
|
||||
0x67,0x0a,0xbb,0xee = vcvt.f32.u16 s0, s0, #1
|
||||
0x40,0x0b,0xba,0xee = vcvt.f64.s16 d0, d0, #16
|
||||
0xc6,0x0a,0xfa,0xee = vcvt.f32.s32 s1, s1, #20
|
||||
0xc0,0x4b,0xfb,0xee = vcvt.f64.u32 d20, d20, #32
|
||||
0x67,0x8a,0xfa,0xee = vcvt.f32.s16 s17, s17, #1
|
||||
0x40,0x7b,0xfb,0xee = vcvt.f64.u16 d23, d23, #16
|
||||
0xc6,0x6a,0xbf,0xee = vcvt.u32.f32 s12, s12, #20
|
||||
0xc0,0x2b,0xbe,0xee = vcvt.s32.f64 d2, d2, #32
|
||||
0x67,0xea,0xbf,0xee = vcvt.u16.f32 s28, s28, #1
|
||||
0x40,0xfb,0xbe,0xee = vcvt.s16.f64 d15, d15, #16
|
||||
0xc6,0x0a,0xfe,0xee = vcvt.s32.f32 s1, s1, #20
|
||||
0xc0,0x4b,0xff,0xee = vcvt.u32.f64 d20, d20, #32
|
||||
0x67,0x8a,0xfe,0xee = vcvt.s16.f32 s17, s17, #1
|
||||
0x40,0x7b,0xff,0xee = vcvt.u16.f64 d23, d23, #16
|
||||
0x10,0x40,0x80,0xf2 = vmov.i32 d4, #0x0
|
||||
0x12,0x46,0x84,0xf2 = vmov.i32 d4, #0x42000000
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# CS_ARCH_ARM, CS_MODE_THUMB, None
|
||||
0x6e,0xeb,0x00,0x0c = sbc.w r12, lr, r0
|
||||
0x6e,0xeb,0x00,0x0c = sbc.w ip, lr, r0
|
||||
0x68,0xeb,0x19,0x01 = sbc.w r1, r8, r9, lsr #32
|
||||
0x67,0xeb,0x1f,0x42 = sbc.w r2, r7, pc, lsr #16
|
||||
0x66,0xeb,0x0a,0x03 = sbc.w r3, r6, r10
|
||||
|
|
@ -8,7 +8,7 @@
|
|||
0x63,0xeb,0x2d,0x46 = sbc.w r6, r3, sp, asr #16
|
||||
0x62,0xeb,0x3c,0x07 = sbc.w r7, r2, r12, rrx
|
||||
0x61,0xeb,0x30,0x48 = sbc.w r8, r1, r0, ror #16
|
||||
0x0e,0xea,0x00,0x0c = and.w r12, lr, r0
|
||||
0x0e,0xea,0x00,0x0c = and.w ip, lr, r0
|
||||
0x08,0xea,0x19,0x01 = and.w r1, r8, r9, lsr #32
|
||||
0x07,0xea,0x1f,0x42 = and.w r2, r7, pc, lsr #16
|
||||
0x06,0xea,0x0a,0x03 = and.w r3, r6, r10
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
# CS_ARCH_ARM, CS_MODE_THUMB, None
|
||||
0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17
|
||||
// 0xe2,0xee,0xa1,0x0b = vfma.f64 d16, d18, d17
|
||||
0xa2,0xee,0x00,0x1a = vfma.f32 s2, s4, s0
|
||||
0x42,0xef,0xb1,0x0c = vfma.f32 d16, d18, d17
|
||||
0x08,0xef,0x50,0x4c = vfma.f32 q2, q4, q0
|
||||
0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17
|
||||
// 0xd2,0xee,0xe1,0x0b = vfnma.f64 d16, d18, d17
|
||||
0x92,0xee,0x40,0x1a = vfnma.f32 s2, s4, s0
|
||||
0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17
|
||||
// 0xe2,0xee,0xe1,0x0b = vfms.f64 d16, d18, d17
|
||||
0xa2,0xee,0x40,0x1a = vfms.f32 s2, s4, s0
|
||||
0x62,0xef,0xb1,0x0c = vfms.f32 d16, d18, d17
|
||||
0x28,0xef,0x50,0x4c = vfms.f32 q2, q4, q0
|
||||
0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17
|
||||
// 0xd2,0xee,0xa1,0x0b = vfnms.f64 d16, d18, d17
|
||||
0x92,0xee,0x00,0x1a = vfnms.f32 s2, s4, s0
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
# CS_ARCH_ARM, CS_MODE_ARM, None
|
||||
0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17
|
||||
// 0xa1,0x0b,0xe2,0xee = vfma.f64 d16, d18, d17
|
||||
0x00,0x1a,0xa2,0xee = vfma.f32 s2, s4, s0
|
||||
0xb1,0x0c,0x42,0xf2 = vfma.f32 d16, d18, d17
|
||||
0x50,0x4c,0x08,0xf2 = vfma.f32 q2, q4, q0
|
||||
0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17
|
||||
// 0xe1,0x0b,0xd2,0xee = vfnma.f64 d16, d18, d17
|
||||
0x40,0x1a,0x92,0xee = vfnma.f32 s2, s4, s0
|
||||
0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17
|
||||
// 0xe1,0x0b,0xe2,0xee = vfms.f64 d16, d18, d17
|
||||
0x40,0x1a,0xa2,0xee = vfms.f32 s2, s4, s0
|
||||
0xb1,0x0c,0x62,0xf2 = vfms.f32 d16, d18, d17
|
||||
0x50,0x4c,0x28,0xf2 = vfms.f32 q2, q4, q0
|
||||
0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17
|
||||
// 0xa1,0x0b,0xd2,0xee = vfnms.f64 d16, d18, d17
|
||||
0x00,0x1a,0x92,0xee = vfnms.f32 s2, s4, s0
|
||||
|
|
|
|||
Loading…
Reference in New Issue