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ppc: add new groups to group_name_maps[]

This commit is contained in:
Nguyen Anh Quynh 2014-08-15 16:35:12 +08:00
parent ee98e408ca
commit 159ddbd99f
8 changed files with 6027 additions and 1535 deletions
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5
arch/PowerPC/PPCMapping.c
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@ -7731,6 +7731,11 @@ static name_map group_name_maps[] = {
{ PPC_GRP_MODE64, "mode64" },
{ PPC_GRP_BOOKE, "booke" },
{ PPC_GRP_NOTBOOKE, "notbooke" },
{ PPC_GRP_SPE, "spe" },
{ PPC_GRP_VSX, "vsx" },
{ PPC_GRP_E500, "e500" },
{ PPC_GRP_PPC4XX, "ppc4xx" },
{ PPC_GRP_PPC6XX, "ppc6xx" },
{ PPC_GRP_JUMP, "jump" },
};

4433
arch/Sparc/SparcGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

2100
arch/Sparc/SparcGenDisassemblerTables.inc
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File diff suppressed because it is too large Load Diff

947
arch/Sparc/SparcGenInstrInfo.inc
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@ -33,479 +33,480 @@ enum {
SP_LIFETIME_END = 16,
SP_STACKMAP = 17,
SP_PATCHPOINT = 18,
SP_ADDCCri = 19,
SP_ADDCCrr = 20,
SP_ADDCri = 21,
SP_ADDCrr = 22,
SP_ADDEri = 23,
SP_ADDErr = 24,
SP_ADDXC = 25,
SP_ADDXCCC = 26,
SP_ADDXri = 27,
SP_ADDXrr = 28,
SP_ADDri = 29,
SP_ADDrr = 30,
SP_ADJCALLSTACKDOWN = 31,
SP_ADJCALLSTACKUP = 32,
SP_ALIGNADDR = 33,
SP_ALIGNADDRL = 34,
SP_ANDCCri = 35,
SP_ANDCCrr = 36,
SP_ANDNCCri = 37,
SP_ANDNCCrr = 38,
SP_ANDNri = 39,
SP_ANDNrr = 40,
SP_ANDXNrr = 41,
SP_ANDXri = 42,
SP_ANDXrr = 43,
SP_ANDri = 44,
SP_ANDrr = 45,
SP_ARRAY16 = 46,
SP_ARRAY32 = 47,
SP_ARRAY8 = 48,
SP_ATOMIC_LOAD_ADD_32 = 49,
SP_ATOMIC_LOAD_ADD_64 = 50,
SP_ATOMIC_LOAD_AND_32 = 51,
SP_ATOMIC_LOAD_AND_64 = 52,
SP_ATOMIC_LOAD_MAX_32 = 53,
SP_ATOMIC_LOAD_MAX_64 = 54,
SP_ATOMIC_LOAD_MIN_32 = 55,
SP_ATOMIC_LOAD_MIN_64 = 56,
SP_ATOMIC_LOAD_NAND_32 = 57,
SP_ATOMIC_LOAD_NAND_64 = 58,
SP_ATOMIC_LOAD_OR_32 = 59,
SP_ATOMIC_LOAD_OR_64 = 60,
SP_ATOMIC_LOAD_SUB_32 = 61,
SP_ATOMIC_LOAD_SUB_64 = 62,
SP_ATOMIC_LOAD_UMAX_32 = 63,
SP_ATOMIC_LOAD_UMAX_64 = 64,
SP_ATOMIC_LOAD_UMIN_32 = 65,
SP_ATOMIC_LOAD_UMIN_64 = 66,
SP_ATOMIC_LOAD_XOR_32 = 67,
SP_ATOMIC_LOAD_XOR_64 = 68,
SP_ATOMIC_SWAP_64 = 69,
SP_BA = 70,
SP_BCOND = 71,
SP_BCONDA = 72,
SP_BINDri = 73,
SP_BINDrr = 74,
SP_BMASK = 75,
SP_BPFCC = 76,
SP_BPFCCA = 77,
SP_BPFCCANT = 78,
SP_BPFCCNT = 79,
SP_BPGEZapn = 80,
SP_BPGEZapt = 81,
SP_BPGEZnapn = 82,
SP_BPGEZnapt = 83,
SP_BPGZapn = 84,
SP_BPGZapt = 85,
SP_BPGZnapn = 86,
SP_BPGZnapt = 87,
SP_BPICC = 88,
SP_BPICCA = 89,
SP_BPICCANT = 90,
SP_BPICCNT = 91,
SP_BPLEZapn = 92,
SP_BPLEZapt = 93,
SP_BPLEZnapn = 94,
SP_BPLEZnapt = 95,
SP_BPLZapn = 96,
SP_BPLZapt = 97,
SP_BPLZnapn = 98,
SP_BPLZnapt = 99,
SP_BPNZapn = 100,
SP_BPNZapt = 101,
SP_BPNZnapn = 102,
SP_BPNZnapt = 103,
SP_BPXCC = 104,
SP_BPXCCA = 105,
SP_BPXCCANT = 106,
SP_BPXCCNT = 107,
SP_BPZapn = 108,
SP_BPZapt = 109,
SP_BPZnapn = 110,
SP_BPZnapt = 111,
SP_BSHUFFLE = 112,
SP_CALL = 113,
SP_CALLri = 114,
SP_CALLrr = 115,
SP_CASXrr = 116,
SP_CASrr = 117,
SP_CMASK16 = 118,
SP_CMASK32 = 119,
SP_CMASK8 = 120,
SP_CMPri = 121,
SP_CMPrr = 122,
SP_EDGE16 = 123,
SP_EDGE16L = 124,
SP_EDGE16LN = 125,
SP_EDGE16N = 126,
SP_EDGE32 = 127,
SP_EDGE32L = 128,
SP_EDGE32LN = 129,
SP_EDGE32N = 130,
SP_EDGE8 = 131,
SP_EDGE8L = 132,
SP_EDGE8LN = 133,
SP_EDGE8N = 134,
SP_FABSD = 135,
SP_FABSQ = 136,
SP_FABSS = 137,
SP_FADDD = 138,
SP_FADDQ = 139,
SP_FADDS = 140,
SP_FALIGNADATA = 141,
SP_FAND = 142,
SP_FANDNOT1 = 143,
SP_FANDNOT1S = 144,
SP_FANDNOT2 = 145,
SP_FANDNOT2S = 146,
SP_FANDS = 147,
SP_FBCOND = 148,
SP_FBCONDA = 149,
SP_FCHKSM16 = 150,
SP_FCMPD = 151,
SP_FCMPEQ16 = 152,
SP_FCMPEQ32 = 153,
SP_FCMPGT16 = 154,
SP_FCMPGT32 = 155,
SP_FCMPLE16 = 156,
SP_FCMPLE32 = 157,
SP_FCMPNE16 = 158,
SP_FCMPNE32 = 159,
SP_FCMPQ = 160,
SP_FCMPS = 161,
SP_FDIVD = 162,
SP_FDIVQ = 163,
SP_FDIVS = 164,
SP_FDMULQ = 165,
SP_FDTOI = 166,
SP_FDTOQ = 167,
SP_FDTOS = 168,
SP_FDTOX = 169,
SP_FEXPAND = 170,
SP_FHADDD = 171,
SP_FHADDS = 172,
SP_FHSUBD = 173,
SP_FHSUBS = 174,
SP_FITOD = 175,
SP_FITOQ = 176,
SP_FITOS = 177,
SP_FLCMPD = 178,
SP_FLCMPS = 179,
SP_FLUSHW = 180,
SP_FMEAN16 = 181,
SP_FMOVD = 182,
SP_FMOVD_FCC = 183,
SP_FMOVD_ICC = 184,
SP_FMOVD_XCC = 185,
SP_FMOVQ = 186,
SP_FMOVQ_FCC = 187,
SP_FMOVQ_ICC = 188,
SP_FMOVQ_XCC = 189,
SP_FMOVRGEZD = 190,
SP_FMOVRGEZQ = 191,
SP_FMOVRGEZS = 192,
SP_FMOVRGZD = 193,
SP_FMOVRGZQ = 194,
SP_FMOVRGZS = 195,
SP_FMOVRLEZD = 196,
SP_FMOVRLEZQ = 197,
SP_FMOVRLEZS = 198,
SP_FMOVRLZD = 199,
SP_FMOVRLZQ = 200,
SP_FMOVRLZS = 201,
SP_FMOVRNZD = 202,
SP_FMOVRNZQ = 203,
SP_FMOVRNZS = 204,
SP_FMOVRZD = 205,
SP_FMOVRZQ = 206,
SP_FMOVRZS = 207,
SP_FMOVS = 208,
SP_FMOVS_FCC = 209,
SP_FMOVS_ICC = 210,
SP_FMOVS_XCC = 211,
SP_FMUL8SUX16 = 212,
SP_FMUL8ULX16 = 213,
SP_FMUL8X16 = 214,
SP_FMUL8X16AL = 215,
SP_FMUL8X16AU = 216,
SP_FMULD = 217,
SP_FMULD8SUX16 = 218,
SP_FMULD8ULX16 = 219,
SP_FMULQ = 220,
SP_FMULS = 221,
SP_FNADDD = 222,
SP_FNADDS = 223,
SP_FNAND = 224,
SP_FNANDS = 225,
SP_FNEGD = 226,
SP_FNEGQ = 227,
SP_FNEGS = 228,
SP_FNHADDD = 229,
SP_FNHADDS = 230,
SP_FNMULD = 231,
SP_FNMULS = 232,
SP_FNOR = 233,
SP_FNORS = 234,
SP_FNOT1 = 235,
SP_FNOT1S = 236,
SP_FNOT2 = 237,
SP_FNOT2S = 238,
SP_FNSMULD = 239,
SP_FONE = 240,
SP_FONES = 241,
SP_FOR = 242,
SP_FORNOT1 = 243,
SP_FORNOT1S = 244,
SP_FORNOT2 = 245,
SP_FORNOT2S = 246,
SP_FORS = 247,
SP_FPACK16 = 248,
SP_FPACK32 = 249,
SP_FPACKFIX = 250,
SP_FPADD16 = 251,
SP_FPADD16S = 252,
SP_FPADD32 = 253,
SP_FPADD32S = 254,
SP_FPADD64 = 255,
SP_FPMERGE = 256,
SP_FPSUB16 = 257,
SP_FPSUB16S = 258,
SP_FPSUB32 = 259,
SP_FPSUB32S = 260,
SP_FQTOD = 261,
SP_FQTOI = 262,
SP_FQTOS = 263,
SP_FQTOX = 264,
SP_FSLAS16 = 265,
SP_FSLAS32 = 266,
SP_FSLL16 = 267,
SP_FSLL32 = 268,
SP_FSMULD = 269,
SP_FSQRTD = 270,
SP_FSQRTQ = 271,
SP_FSQRTS = 272,
SP_FSRA16 = 273,
SP_FSRA32 = 274,
SP_FSRC1 = 275,
SP_FSRC1S = 276,
SP_FSRC2 = 277,
SP_FSRC2S = 278,
SP_FSRL16 = 279,
SP_FSRL32 = 280,
SP_FSTOD = 281,
SP_FSTOI = 282,
SP_FSTOQ = 283,
SP_FSTOX = 284,
SP_FSUBD = 285,
SP_FSUBQ = 286,
SP_FSUBS = 287,
SP_FXNOR = 288,
SP_FXNORS = 289,
SP_FXOR = 290,
SP_FXORS = 291,
SP_FXTOD = 292,
SP_FXTOQ = 293,
SP_FXTOS = 294,
SP_FZERO = 295,
SP_FZEROS = 296,
SP_GETPCX = 297,
SP_JMPLri = 298,
SP_JMPLrr = 299,
SP_LDDFri = 300,
SP_LDDFrr = 301,
SP_LDFri = 302,
SP_LDFrr = 303,
SP_LDQFri = 304,
SP_LDQFrr = 305,
SP_LDSBri = 306,
SP_LDSBrr = 307,
SP_LDSHri = 308,
SP_LDSHrr = 309,
SP_LDSWri = 310,
SP_LDSWrr = 311,
SP_LDUBri = 312,
SP_LDUBrr = 313,
SP_LDUHri = 314,
SP_LDUHrr = 315,
SP_LDXri = 316,
SP_LDXrr = 317,
SP_LDri = 318,
SP_LDrr = 319,
SP_LEAX_ADDri = 320,
SP_LEA_ADDri = 321,
SP_LZCNT = 322,
SP_MEMBARi = 323,
SP_MOVDTOX = 324,
SP_MOVFCCri = 325,
SP_MOVFCCrr = 326,
SP_MOVICCri = 327,
SP_MOVICCrr = 328,
SP_MOVRGEZri = 329,
SP_MOVRGEZrr = 330,
SP_MOVRGZri = 331,
SP_MOVRGZrr = 332,
SP_MOVRLEZri = 333,
SP_MOVRLEZrr = 334,
SP_MOVRLZri = 335,
SP_MOVRLZrr = 336,
SP_MOVRNZri = 337,
SP_MOVRNZrr = 338,
SP_MOVRRZri = 339,
SP_MOVRRZrr = 340,
SP_MOVSTOSW = 341,
SP_MOVSTOUW = 342,
SP_MOVWTOS = 343,
SP_MOVXCCri = 344,
SP_MOVXCCrr = 345,
SP_MOVXTOD = 346,
SP_MULXri = 347,
SP_MULXrr = 348,
SP_NOP = 349,
SP_ORCCri = 350,
SP_ORCCrr = 351,
SP_ORNCCri = 352,
SP_ORNCCrr = 353,
SP_ORNri = 354,
SP_ORNrr = 355,
SP_ORXNrr = 356,
SP_ORXri = 357,
SP_ORXrr = 358,
SP_ORri = 359,
SP_ORrr = 360,
SP_PDIST = 361,
SP_PDISTN = 362,
SP_POPCrr = 363,
SP_RDY = 364,
SP_RESTOREri = 365,
SP_RESTORErr = 366,
SP_RET = 367,
SP_RETL = 368,
SP_RETTri = 369,
SP_RETTrr = 370,
SP_SAVEri = 371,
SP_SAVErr = 372,
SP_SDIVCCri = 373,
SP_SDIVCCrr = 374,
SP_SDIVXri = 375,
SP_SDIVXrr = 376,
SP_SDIVri = 377,
SP_SDIVrr = 378,
SP_SELECT_CC_DFP_FCC = 379,
SP_SELECT_CC_DFP_ICC = 380,
SP_SELECT_CC_FP_FCC = 381,
SP_SELECT_CC_FP_ICC = 382,
SP_SELECT_CC_Int_FCC = 383,
SP_SELECT_CC_Int_ICC = 384,
SP_SELECT_CC_QFP_FCC = 385,
SP_SELECT_CC_QFP_ICC = 386,
SP_SETHIXi = 387,
SP_SETHIi = 388,
SP_SHUTDOWN = 389,
SP_SIAM = 390,
SP_SLLXri = 391,
SP_SLLXrr = 392,
SP_SLLri = 393,
SP_SLLrr = 394,
SP_SMULCCri = 395,
SP_SMULCCrr = 396,
SP_SMULri = 397,
SP_SMULrr = 398,
SP_SRAXri = 399,
SP_SRAXrr = 400,
SP_SRAri = 401,
SP_SRArr = 402,
SP_SRLXri = 403,
SP_SRLXrr = 404,
SP_SRLri = 405,
SP_SRLrr = 406,
SP_STBAR = 407,
SP_STBri = 408,
SP_STBrr = 409,
SP_STDFri = 410,
SP_STDFrr = 411,
SP_STFri = 412,
SP_STFrr = 413,
SP_STHri = 414,
SP_STHrr = 415,
SP_STQFri = 416,
SP_STQFrr = 417,
SP_STXri = 418,
SP_STXrr = 419,
SP_STri = 420,
SP_STrr = 421,
SP_SUBCCri = 422,
SP_SUBCCrr = 423,
SP_SUBCri = 424,
SP_SUBCrr = 425,
SP_SUBEri = 426,
SP_SUBErr = 427,
SP_SUBXri = 428,
SP_SUBXrr = 429,
SP_SUBri = 430,
SP_SUBrr = 431,
SP_SWAPri = 432,
SP_SWAPrr = 433,
SP_TA3 = 434,
SP_TA5 = 435,
SP_TADDCCTVri = 436,
SP_TADDCCTVrr = 437,
SP_TADDCCri = 438,
SP_TADDCCrr = 439,
SP_TICCri = 440,
SP_TICCrr = 441,
SP_TLS_ADDXrr = 442,
SP_TLS_ADDrr = 443,
SP_TLS_CALL = 444,
SP_TLS_LDXrr = 445,
SP_TLS_LDrr = 446,
SP_TSUBCCTVri = 447,
SP_TSUBCCTVrr = 448,
SP_TSUBCCri = 449,
SP_TSUBCCrr = 450,
SP_TXCCri = 451,
SP_TXCCrr = 452,
SP_UDIVCCri = 453,
SP_UDIVCCrr = 454,
SP_UDIVXri = 455,
SP_UDIVXrr = 456,
SP_UDIVri = 457,
SP_UDIVrr = 458,
SP_UMULCCri = 459,
SP_UMULCCrr = 460,
SP_UMULXHI = 461,
SP_UMULri = 462,
SP_UMULrr = 463,
SP_UNIMP = 464,
SP_V9FCMPD = 465,
SP_V9FCMPED = 466,
SP_V9FCMPEQ = 467,
SP_V9FCMPES = 468,
SP_V9FCMPQ = 469,
SP_V9FCMPS = 470,
SP_V9FMOVD_FCC = 471,
SP_V9FMOVQ_FCC = 472,
SP_V9FMOVS_FCC = 473,
SP_V9MOVFCCri = 474,
SP_V9MOVFCCrr = 475,
SP_WRYri = 476,
SP_WRYrr = 477,
SP_XMULX = 478,
SP_XMULXHI = 479,
SP_XNORCCri = 480,
SP_XNORCCrr = 481,
SP_XNORXrr = 482,
SP_XNORri = 483,
SP_XNORrr = 484,
SP_XORCCri = 485,
SP_XORCCrr = 486,
SP_XORXri = 487,
SP_XORXrr = 488,
SP_XORri = 489,
SP_XORrr = 490,
SP_INSTRUCTION_LIST_END = 491
SP_LOAD_STACK_GUARD = 19,
SP_ADDCCri = 20,
SP_ADDCCrr = 21,
SP_ADDCri = 22,
SP_ADDCrr = 23,
SP_ADDEri = 24,
SP_ADDErr = 25,
SP_ADDXC = 26,
SP_ADDXCCC = 27,
SP_ADDXri = 28,
SP_ADDXrr = 29,
SP_ADDri = 30,
SP_ADDrr = 31,
SP_ADJCALLSTACKDOWN = 32,
SP_ADJCALLSTACKUP = 33,
SP_ALIGNADDR = 34,
SP_ALIGNADDRL = 35,
SP_ANDCCri = 36,
SP_ANDCCrr = 37,
SP_ANDNCCri = 38,
SP_ANDNCCrr = 39,
SP_ANDNri = 40,
SP_ANDNrr = 41,
SP_ANDXNrr = 42,
SP_ANDXri = 43,
SP_ANDXrr = 44,
SP_ANDri = 45,
SP_ANDrr = 46,
SP_ARRAY16 = 47,
SP_ARRAY32 = 48,
SP_ARRAY8 = 49,
SP_ATOMIC_LOAD_ADD_32 = 50,
SP_ATOMIC_LOAD_ADD_64 = 51,
SP_ATOMIC_LOAD_AND_32 = 52,
SP_ATOMIC_LOAD_AND_64 = 53,
SP_ATOMIC_LOAD_MAX_32 = 54,
SP_ATOMIC_LOAD_MAX_64 = 55,
SP_ATOMIC_LOAD_MIN_32 = 56,
SP_ATOMIC_LOAD_MIN_64 = 57,
SP_ATOMIC_LOAD_NAND_32 = 58,
SP_ATOMIC_LOAD_NAND_64 = 59,
SP_ATOMIC_LOAD_OR_32 = 60,
SP_ATOMIC_LOAD_OR_64 = 61,
SP_ATOMIC_LOAD_SUB_32 = 62,
SP_ATOMIC_LOAD_SUB_64 = 63,
SP_ATOMIC_LOAD_UMAX_32 = 64,
SP_ATOMIC_LOAD_UMAX_64 = 65,
SP_ATOMIC_LOAD_UMIN_32 = 66,
SP_ATOMIC_LOAD_UMIN_64 = 67,
SP_ATOMIC_LOAD_XOR_32 = 68,
SP_ATOMIC_LOAD_XOR_64 = 69,
SP_ATOMIC_SWAP_64 = 70,
SP_BA = 71,
SP_BCOND = 72,
SP_BCONDA = 73,
SP_BINDri = 74,
SP_BINDrr = 75,
SP_BMASK = 76,
SP_BPFCC = 77,
SP_BPFCCA = 78,
SP_BPFCCANT = 79,
SP_BPFCCNT = 80,
SP_BPGEZapn = 81,
SP_BPGEZapt = 82,
SP_BPGEZnapn = 83,
SP_BPGEZnapt = 84,
SP_BPGZapn = 85,
SP_BPGZapt = 86,
SP_BPGZnapn = 87,
SP_BPGZnapt = 88,
SP_BPICC = 89,
SP_BPICCA = 90,
SP_BPICCANT = 91,
SP_BPICCNT = 92,
SP_BPLEZapn = 93,
SP_BPLEZapt = 94,
SP_BPLEZnapn = 95,
SP_BPLEZnapt = 96,
SP_BPLZapn = 97,
SP_BPLZapt = 98,
SP_BPLZnapn = 99,
SP_BPLZnapt = 100,
SP_BPNZapn = 101,
SP_BPNZapt = 102,
SP_BPNZnapn = 103,
SP_BPNZnapt = 104,
SP_BPXCC = 105,
SP_BPXCCA = 106,
SP_BPXCCANT = 107,
SP_BPXCCNT = 108,
SP_BPZapn = 109,
SP_BPZapt = 110,
SP_BPZnapn = 111,
SP_BPZnapt = 112,
SP_BSHUFFLE = 113,
SP_CALL = 114,
SP_CALLri = 115,
SP_CALLrr = 116,
SP_CASXrr = 117,
SP_CASrr = 118,
SP_CMASK16 = 119,
SP_CMASK32 = 120,
SP_CMASK8 = 121,
SP_CMPri = 122,
SP_CMPrr = 123,
SP_EDGE16 = 124,
SP_EDGE16L = 125,
SP_EDGE16LN = 126,
SP_EDGE16N = 127,
SP_EDGE32 = 128,
SP_EDGE32L = 129,
SP_EDGE32LN = 130,
SP_EDGE32N = 131,
SP_EDGE8 = 132,
SP_EDGE8L = 133,
SP_EDGE8LN = 134,
SP_EDGE8N = 135,
SP_FABSD = 136,
SP_FABSQ = 137,
SP_FABSS = 138,
SP_FADDD = 139,
SP_FADDQ = 140,
SP_FADDS = 141,
SP_FALIGNADATA = 142,
SP_FAND = 143,
SP_FANDNOT1 = 144,
SP_FANDNOT1S = 145,
SP_FANDNOT2 = 146,
SP_FANDNOT2S = 147,
SP_FANDS = 148,
SP_FBCOND = 149,
SP_FBCONDA = 150,
SP_FCHKSM16 = 151,
SP_FCMPD = 152,
SP_FCMPEQ16 = 153,
SP_FCMPEQ32 = 154,
SP_FCMPGT16 = 155,
SP_FCMPGT32 = 156,
SP_FCMPLE16 = 157,
SP_FCMPLE32 = 158,
SP_FCMPNE16 = 159,
SP_FCMPNE32 = 160,
SP_FCMPQ = 161,
SP_FCMPS = 162,
SP_FDIVD = 163,
SP_FDIVQ = 164,
SP_FDIVS = 165,
SP_FDMULQ = 166,
SP_FDTOI = 167,
SP_FDTOQ = 168,
SP_FDTOS = 169,
SP_FDTOX = 170,
SP_FEXPAND = 171,
SP_FHADDD = 172,
SP_FHADDS = 173,
SP_FHSUBD = 174,
SP_FHSUBS = 175,
SP_FITOD = 176,
SP_FITOQ = 177,
SP_FITOS = 178,
SP_FLCMPD = 179,
SP_FLCMPS = 180,
SP_FLUSHW = 181,
SP_FMEAN16 = 182,
SP_FMOVD = 183,
SP_FMOVD_FCC = 184,
SP_FMOVD_ICC = 185,
SP_FMOVD_XCC = 186,
SP_FMOVQ = 187,
SP_FMOVQ_FCC = 188,
SP_FMOVQ_ICC = 189,
SP_FMOVQ_XCC = 190,
SP_FMOVRGEZD = 191,
SP_FMOVRGEZQ = 192,
SP_FMOVRGEZS = 193,
SP_FMOVRGZD = 194,
SP_FMOVRGZQ = 195,
SP_FMOVRGZS = 196,
SP_FMOVRLEZD = 197,
SP_FMOVRLEZQ = 198,
SP_FMOVRLEZS = 199,
SP_FMOVRLZD = 200,
SP_FMOVRLZQ = 201,
SP_FMOVRLZS = 202,
SP_FMOVRNZD = 203,
SP_FMOVRNZQ = 204,
SP_FMOVRNZS = 205,
SP_FMOVRZD = 206,
SP_FMOVRZQ = 207,
SP_FMOVRZS = 208,
SP_FMOVS = 209,
SP_FMOVS_FCC = 210,
SP_FMOVS_ICC = 211,
SP_FMOVS_XCC = 212,
SP_FMUL8SUX16 = 213,
SP_FMUL8ULX16 = 214,
SP_FMUL8X16 = 215,
SP_FMUL8X16AL = 216,
SP_FMUL8X16AU = 217,
SP_FMULD = 218,
SP_FMULD8SUX16 = 219,
SP_FMULD8ULX16 = 220,
SP_FMULQ = 221,
SP_FMULS = 222,
SP_FNADDD = 223,
SP_FNADDS = 224,
SP_FNAND = 225,
SP_FNANDS = 226,
SP_FNEGD = 227,
SP_FNEGQ = 228,
SP_FNEGS = 229,
SP_FNHADDD = 230,
SP_FNHADDS = 231,
SP_FNMULD = 232,
SP_FNMULS = 233,
SP_FNOR = 234,
SP_FNORS = 235,
SP_FNOT1 = 236,
SP_FNOT1S = 237,
SP_FNOT2 = 238,
SP_FNOT2S = 239,
SP_FNSMULD = 240,
SP_FONE = 241,
SP_FONES = 242,
SP_FOR = 243,
SP_FORNOT1 = 244,
SP_FORNOT1S = 245,
SP_FORNOT2 = 246,
SP_FORNOT2S = 247,
SP_FORS = 248,
SP_FPACK16 = 249,
SP_FPACK32 = 250,
SP_FPACKFIX = 251,
SP_FPADD16 = 252,
SP_FPADD16S = 253,
SP_FPADD32 = 254,
SP_FPADD32S = 255,
SP_FPADD64 = 256,
SP_FPMERGE = 257,
SP_FPSUB16 = 258,
SP_FPSUB16S = 259,
SP_FPSUB32 = 260,
SP_FPSUB32S = 261,
SP_FQTOD = 262,
SP_FQTOI = 263,
SP_FQTOS = 264,
SP_FQTOX = 265,
SP_FSLAS16 = 266,
SP_FSLAS32 = 267,
SP_FSLL16 = 268,
SP_FSLL32 = 269,
SP_FSMULD = 270,
SP_FSQRTD = 271,
SP_FSQRTQ = 272,
SP_FSQRTS = 273,
SP_FSRA16 = 274,
SP_FSRA32 = 275,
SP_FSRC1 = 276,
SP_FSRC1S = 277,
SP_FSRC2 = 278,
SP_FSRC2S = 279,
SP_FSRL16 = 280,
SP_FSRL32 = 281,
SP_FSTOD = 282,
SP_FSTOI = 283,
SP_FSTOQ = 284,
SP_FSTOX = 285,
SP_FSUBD = 286,
SP_FSUBQ = 287,
SP_FSUBS = 288,
SP_FXNOR = 289,
SP_FXNORS = 290,
SP_FXOR = 291,
SP_FXORS = 292,
SP_FXTOD = 293,
SP_FXTOQ = 294,
SP_FXTOS = 295,
SP_FZERO = 296,
SP_FZEROS = 297,
SP_GETPCX = 298,
SP_JMPLri = 299,
SP_JMPLrr = 300,
SP_LDDFri = 301,
SP_LDDFrr = 302,
SP_LDFri = 303,
SP_LDFrr = 304,
SP_LDQFri = 305,
SP_LDQFrr = 306,
SP_LDSBri = 307,
SP_LDSBrr = 308,
SP_LDSHri = 309,
SP_LDSHrr = 310,
SP_LDSWri = 311,
SP_LDSWrr = 312,
SP_LDUBri = 313,
SP_LDUBrr = 314,
SP_LDUHri = 315,
SP_LDUHrr = 316,
SP_LDXri = 317,
SP_LDXrr = 318,
SP_LDri = 319,
SP_LDrr = 320,
SP_LEAX_ADDri = 321,
SP_LEA_ADDri = 322,
SP_LZCNT = 323,
SP_MEMBARi = 324,
SP_MOVDTOX = 325,
SP_MOVFCCri = 326,
SP_MOVFCCrr = 327,
SP_MOVICCri = 328,
SP_MOVICCrr = 329,
SP_MOVRGEZri = 330,
SP_MOVRGEZrr = 331,
SP_MOVRGZri = 332,
SP_MOVRGZrr = 333,
SP_MOVRLEZri = 334,
SP_MOVRLEZrr = 335,
SP_MOVRLZri = 336,
SP_MOVRLZrr = 337,
SP_MOVRNZri = 338,
SP_MOVRNZrr = 339,
SP_MOVRRZri = 340,
SP_MOVRRZrr = 341,
SP_MOVSTOSW = 342,
SP_MOVSTOUW = 343,
SP_MOVWTOS = 344,
SP_MOVXCCri = 345,
SP_MOVXCCrr = 346,
SP_MOVXTOD = 347,
SP_MULXri = 348,
SP_MULXrr = 349,
SP_NOP = 350,
SP_ORCCri = 351,
SP_ORCCrr = 352,
SP_ORNCCri = 353,
SP_ORNCCrr = 354,
SP_ORNri = 355,
SP_ORNrr = 356,
SP_ORXNrr = 357,
SP_ORXri = 358,
SP_ORXrr = 359,
SP_ORri = 360,
SP_ORrr = 361,
SP_PDIST = 362,
SP_PDISTN = 363,
SP_POPCrr = 364,
SP_RDY = 365,
SP_RESTOREri = 366,
SP_RESTORErr = 367,
SP_RET = 368,
SP_RETL = 369,
SP_RETTri = 370,
SP_RETTrr = 371,
SP_SAVEri = 372,
SP_SAVErr = 373,
SP_SDIVCCri = 374,
SP_SDIVCCrr = 375,
SP_SDIVXri = 376,
SP_SDIVXrr = 377,
SP_SDIVri = 378,
SP_SDIVrr = 379,
SP_SELECT_CC_DFP_FCC = 380,
SP_SELECT_CC_DFP_ICC = 381,
SP_SELECT_CC_FP_FCC = 382,
SP_SELECT_CC_FP_ICC = 383,
SP_SELECT_CC_Int_FCC = 384,
SP_SELECT_CC_Int_ICC = 385,
SP_SELECT_CC_QFP_FCC = 386,
SP_SELECT_CC_QFP_ICC = 387,
SP_SETHIXi = 388,
SP_SETHIi = 389,
SP_SHUTDOWN = 390,
SP_SIAM = 391,
SP_SLLXri = 392,
SP_SLLXrr = 393,
SP_SLLri = 394,
SP_SLLrr = 395,
SP_SMULCCri = 396,
SP_SMULCCrr = 397,
SP_SMULri = 398,
SP_SMULrr = 399,
SP_SRAXri = 400,
SP_SRAXrr = 401,
SP_SRAri = 402,
SP_SRArr = 403,
SP_SRLXri = 404,
SP_SRLXrr = 405,
SP_SRLri = 406,
SP_SRLrr = 407,
SP_STBAR = 408,
SP_STBri = 409,
SP_STBrr = 410,
SP_STDFri = 411,
SP_STDFrr = 412,
SP_STFri = 413,
SP_STFrr = 414,
SP_STHri = 415,
SP_STHrr = 416,
SP_STQFri = 417,
SP_STQFrr = 418,
SP_STXri = 419,
SP_STXrr = 420,
SP_STri = 421,
SP_STrr = 422,
SP_SUBCCri = 423,
SP_SUBCCrr = 424,
SP_SUBCri = 425,
SP_SUBCrr = 426,
SP_SUBEri = 427,
SP_SUBErr = 428,
SP_SUBXri = 429,
SP_SUBXrr = 430,
SP_SUBri = 431,
SP_SUBrr = 432,
SP_SWAPri = 433,
SP_SWAPrr = 434,
SP_TA3 = 435,
SP_TA5 = 436,
SP_TADDCCTVri = 437,
SP_TADDCCTVrr = 438,
SP_TADDCCri = 439,
SP_TADDCCrr = 440,
SP_TICCri = 441,
SP_TICCrr = 442,
SP_TLS_ADDXrr = 443,
SP_TLS_ADDrr = 444,
SP_TLS_CALL = 445,
SP_TLS_LDXrr = 446,
SP_TLS_LDrr = 447,
SP_TSUBCCTVri = 448,
SP_TSUBCCTVrr = 449,
SP_TSUBCCri = 450,
SP_TSUBCCrr = 451,
SP_TXCCri = 452,
SP_TXCCrr = 453,
SP_UDIVCCri = 454,
SP_UDIVCCrr = 455,
SP_UDIVXri = 456,
SP_UDIVXrr = 457,
SP_UDIVri = 458,
SP_UDIVrr = 459,
SP_UMULCCri = 460,
SP_UMULCCrr = 461,
SP_UMULXHI = 462,
SP_UMULri = 463,
SP_UMULrr = 464,
SP_UNIMP = 465,
SP_V9FCMPD = 466,
SP_V9FCMPED = 467,
SP_V9FCMPEQ = 468,
SP_V9FCMPES = 469,
SP_V9FCMPQ = 470,
SP_V9FCMPS = 471,
SP_V9FMOVD_FCC = 472,
SP_V9FMOVQ_FCC = 473,
SP_V9FMOVS_FCC = 474,
SP_V9MOVFCCri = 475,
SP_V9MOVFCCrr = 476,
SP_WRYri = 477,
SP_WRYrr = 478,
SP_XMULX = 479,
SP_XMULXHI = 480,
SP_XNORCCri = 481,
SP_XNORCCrr = 482,
SP_XNORXrr = 483,
SP_XNORri = 484,
SP_XNORrr = 485,
SP_XORCCri = 486,
SP_XORCCrr = 487,
SP_XORXri = 488,
SP_XORXrr = 489,
SP_XORri = 490,
SP_XORrr = 491,
SP_INSTRUCTION_LIST_END = 492
};
#endif // GET_INSTRINFO_ENUM

16
arch/Sparc/SparcGenRegisterInfo.inc
View File

@ -369,7 +369,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// FCCRegs Register Class...
static uint16_t FCCRegs[] = {
static MCPhysReg FCCRegs[] = {
SP_FCC0, SP_FCC1, SP_FCC2, SP_FCC3,
};
@ -379,7 +379,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// FPRegs Register Class...
static uint16_t FPRegs[] = {
static MCPhysReg FPRegs[] = {
SP_F0, SP_F1, SP_F2, SP_F3, SP_F4, SP_F5, SP_F6, SP_F7, SP_F8, SP_F9, SP_F10, SP_F11, SP_F12, SP_F13, SP_F14, SP_F15, SP_F16, SP_F17, SP_F18, SP_F19, SP_F20, SP_F21, SP_F22, SP_F23, SP_F24, SP_F25, SP_F26, SP_F27, SP_F28, SP_F29, SP_F30, SP_F31,
};
@ -389,7 +389,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// IntRegs Register Class...
static uint16_t IntRegs[] = {
static MCPhysReg IntRegs[] = {
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
};
@ -399,7 +399,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// DFPRegs Register Class...
static uint16_t DFPRegs[] = {
static MCPhysReg DFPRegs[] = {
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15, SP_D16, SP_D17, SP_D18, SP_D19, SP_D20, SP_D21, SP_D22, SP_D23, SP_D24, SP_D25, SP_D26, SP_D27, SP_D28, SP_D29, SP_D30, SP_D31,
};
@ -409,7 +409,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// I64Regs Register Class...
static uint16_t I64Regs[] = {
static MCPhysReg I64Regs[] = {
SP_I0, SP_I1, SP_I2, SP_I3, SP_I4, SP_I5, SP_I6, SP_I7, SP_G0, SP_G1, SP_G2, SP_G3, SP_G4, SP_G5, SP_G6, SP_G7, SP_L0, SP_L1, SP_L2, SP_L3, SP_L4, SP_L5, SP_L6, SP_L7, SP_O0, SP_O1, SP_O2, SP_O3, SP_O4, SP_O5, SP_O6, SP_O7,
};
@ -419,7 +419,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// DFPRegs_with_sub_even Register Class...
static uint16_t DFPRegs_with_sub_even[] = {
static MCPhysReg DFPRegs_with_sub_even[] = {
SP_D0, SP_D1, SP_D2, SP_D3, SP_D4, SP_D5, SP_D6, SP_D7, SP_D8, SP_D9, SP_D10, SP_D11, SP_D12, SP_D13, SP_D14, SP_D15,
};
@ -429,7 +429,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// QFPRegs Register Class...
static uint16_t QFPRegs[] = {
static MCPhysReg QFPRegs[] = {
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7, SP_Q8, SP_Q9, SP_Q10, SP_Q11, SP_Q12, SP_Q13, SP_Q14, SP_Q15,
};
@ -439,7 +439,7 @@ static MCRegisterDesc SparcRegDesc[] = { // Descriptors
};
// QFPRegs_with_sub_even Register Class...
static uint16_t QFPRegs_with_sub_even[] = {
static MCPhysReg QFPRegs_with_sub_even[] = {
SP_Q0, SP_Q1, SP_Q2, SP_Q3, SP_Q4, SP_Q5, SP_Q6, SP_Q7,
};

6
arch/Sparc/SparcInstPrinter.c
View File

@ -267,9 +267,11 @@ void Sparc_printInst(MCInst *MI, SStream *O, void *Info)
char *mnem;
mnem = printAliasInstr(MI, O, Info);
if (mnem)
if (mnem) {
// fixup instruction id due to the change in alias instruction
MCInst_setOpcodePub(MI, Sparc_map_insn(mnem));
cs_mem_free(mnem);
else {
} else {
if (!printSparcAliasInstr(MI, O))
printInstruction(MI, O, NULL);
}

49
arch/Sparc/SparcMapping.c
View File

@ -3204,4 +3204,53 @@ sparc_reg Sparc_map_register(unsigned int r)
return 0;
}
// map instruction name to instruction ID (public)
sparc_reg Sparc_map_insn(const char *name)
{
unsigned int i;
// NOTE: skip first NULL name in insn_name_maps
i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
return (i != -1)? i : SPARC_REG_INVALID;
}
static name_map alias_icc_maps[] = {
{ SPARC_CC_ICC_A, "a" },
{ SPARC_CC_ICC_N, "n" },
{ SPARC_CC_ICC_NE, "ne" },
{ SPARC_CC_ICC_E, "e" },
{ SPARC_CC_ICC_G, "g" },
{ SPARC_CC_ICC_LE, "le" },
{ SPARC_CC_ICC_GE, "ge" },
{ SPARC_CC_ICC_L, "l" },
{ SPARC_CC_ICC_GU, "gu" },
{ SPARC_CC_ICC_LEU, "leu" },
{ SPARC_CC_ICC_CC, "cc" },
{ SPARC_CC_ICC_CS, "cs" },
{ SPARC_CC_ICC_POS, "pos" },
{ SPARC_CC_ICC_NEG, "neg" },
{ SPARC_CC_ICC_VC, "vc" },
{ SPARC_CC_ICC_VS, "vs" },
};
static name_map alias_fcc_maps[] = {
{ SPARC_CC_FCC_A, "a" },
{ SPARC_CC_FCC_N, "n" },
{ SPARC_CC_FCC_U, "u" },
{ SPARC_CC_FCC_G, "g" },
{ SPARC_CC_FCC_UG, "ug" },
{ SPARC_CC_FCC_L, "l" },
{ SPARC_CC_FCC_UL, "ul" },
{ SPARC_CC_FCC_LG, "lg" },
{ SPARC_CC_FCC_NE, "ne" },
{ SPARC_CC_FCC_E, "e" },
{ SPARC_CC_FCC_UE, "ue" },
{ SPARC_CC_FCC_GE, "ge" },
{ SPARC_CC_FCC_UGE, "uge" },
{ SPARC_CC_FCC_LE, "le" },
{ SPARC_CC_FCC_ULE, "ule" },
{ SPARC_CC_FCC_O, "o" },
};
#endif

4
arch/Sparc/SparcMapping.h
View File

@ -19,5 +19,9 @@ const char *Sparc_group_name(csh handle, unsigned int id);
// map internal raw register to 'public' register
sparc_reg Sparc_map_register(unsigned int r);
// map instruction name to instruction ID (public)
// this is for alias instructions only
sparc_reg Sparc_map_insn(const char *name);
#endif