Fix python test output, same as core test
This commit is contained in:
danghvu
parent
f3ef69673a
commit
1a7c449a72
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@ -8,7 +8,7 @@ TEST_ARM64 = $(TMPDIR)/test_arm64
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TEST_MIPS = $(TMPDIR)/test_mips
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TEST_X86 = $(TMPDIR)/test_x86
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all: expected python_test java_test #oclma_test ruby_test
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all: expected python java #oclma ruby
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expected:
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$(MAKE) -C ../tests
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@ -25,6 +25,7 @@ python: FORCE
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python python/test_arm64.py > $(TEST_ARM64)_o
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python python/test_mips.py > $(TEST_MIPS)_o
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python python/test_x86.py > $(TEST_X86)_o
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$(MAKE) test
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java: FORCE
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$(MAKE) -C java
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@ -33,15 +34,13 @@ java: FORCE
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cd java; ./run.sh arm64 > $(TEST_ARM64)_o
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cd java; ./run.sh mips > $(TEST_MIPS)_o
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cd java; ./run.sh x86 > $(TEST_X86)_o
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$(MAKE) test
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test:
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test: FORCE
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$(DIFF) $(TEST)_e $(TEST)_o
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$(DIFF) $(TEST_ARM)_e $(TEST_ARM)_o
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$(DIFF) $(TEST_ARM64)_e $(TEST_ARM64)_o
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$(DIFF) $(TEST_MIPS)_e $(TEST_MIPS)_o
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$(DIFF) $(TEST_X86)_e $(TEST_X86)_o
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python_test: python test
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java_test: java test
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FORCE:
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@ -203,7 +203,7 @@ class cs_insn:
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elif arch == CS_ARCH_X86:
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(self.prefix, self.segment, self.opcode, self.op_size, self.addr_size, \
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self.disp_size, self.imm_size, self.modrm, self.sib, self.disp, \
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self.sib_index, self.sib_scale, self.operands) = x86.get_arch_info(all_info.arch.x86)
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self.sib_index, self.sib_scale, self.sib_base, self.operands) = x86.get_arch_info(all_info.arch.x86)
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elif arch == CS_ARCH_MIPS:
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self.operands = mips.get_arch_info(all_info.arch.mips)
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@ -57,7 +57,7 @@ def get_arch_info(a):
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if i.type == 0:
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break
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op_info.append(i)
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return (a.prefix, a.segment, a.opcode, a.op_size, a.addr_size, a.disp_size, a.imm_size, a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, op_info)
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return (a.prefix, a.segment, a.opcode, a.op_size, a.addr_size, a.disp_size, a.imm_size, a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, a.sib_base, op_info)
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# all Intel reigsters
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X86_REG_INVALID = 0
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@ -10,7 +10,7 @@ X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00"
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ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
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ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
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THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
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THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88"
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THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
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MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
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MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00"
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ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
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@ -21,18 +21,17 @@ all_tests = (
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(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
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(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
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(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM"),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
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(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON"),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB"),
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
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(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
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(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
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(CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
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(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
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)
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def to_hex(s):
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# print " ".join("{0:x}".format(ord(c)) for c in s) # <-- Python 3 is OK
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return ' '.join(x.encode('hex') for x in s) # <-- fails for Python 3
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return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
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### Test cs_disasm_quick()
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@ -50,15 +49,18 @@ def test_cs_disasm_quick():
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### Test class cs
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def test_class():
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for (arch, mode, code, comment) in all_tests:
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print('*' * 40)
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print('*' * 16)
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print("Platform: %s" %comment)
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print("Disasm:"),
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print to_hex(code)
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print("Code: %s" % to_hex(code))
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print("Disasm:")
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try:
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md = cs(arch, mode)
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for insn in md.disasm(code, 0x1000):
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all_ins = list(md.disasm(code, 0x1000))
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for insn in all_ins:
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print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
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print("0x%x:" % (all_ins[-1].address + all_ins[-1].size))
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print
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except:
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print("ERROR: Arch or mode unsupported!")
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@ -17,6 +17,15 @@ all_tests = (
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(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2"),
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)
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def to_hex(s):
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return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
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def to_x(s):
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from struct import pack
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if not s: return '0'
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x = pack(">q", s).encode('hex')
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while x[0] == '0': x = x[1:]
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return x
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### Test class cs
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def test_class():
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@ -24,24 +33,14 @@ def test_class():
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# print address, mnemonic and operands
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print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
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if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
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print("\tCode condition: %u" %insn.cc)
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if insn.update_flags:
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print("\tUpdate-flags: True")
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if insn.writeback:
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print("\tWriteback: True")
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if len(insn.operands) > 0:
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print("\top_count: %u" %len(insn.operands))
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c = 0
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for i in insn.operands:
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c += 1
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if i.type == ARM_OP_REG:
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print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
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if i.type == ARM_OP_IMM:
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print("\t\toperands[%u].type: IMM = %x" %(c, i.value.imm))
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print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
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if i.type == ARM_OP_PIMM:
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print("\t\toperands[%u].type: P-IMM = %u" %(c, i.value.imm))
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if i.type == ARM_OP_CIMM:
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@ -60,24 +59,35 @@ def test_class():
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print("\t\t\toperands[%u].mem.scale: %u" \
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%(c, i.value.mem.scale))
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if i.value.mem.disp != 0:
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print("\t\t\toperands[%u].mem.disp: %x" \
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%(c, i.value.mem.disp))
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print("\t\t\toperands[%u].mem.disp: 0x%s" \
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%(c, to_x(i.value.mem.disp)))
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if i.shift.type != ARM_SFT_INVALID and i.shift.value:
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print("\t\t\tShift: type = %u, value = %u\n" \
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%(i.shift.type, i.shift.value))
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c+=1
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if insn.update_flags:
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print("\tUpdate-flags: True")
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if insn.writeback:
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print("\tWrite-back: True")
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if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
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print("\tCode condition: %u" %insn.cc)
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for (arch, mode, code, comment) in all_tests:
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print("*" * 30)
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print("*" * 16)
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print("Platform: %s" %comment)
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print("Code: %s" % to_hex(code))
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print("Disasm:")
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try:
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md = cs(arch, mode)
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last = None
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for insn in md.disasm(code, 0x1000):
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print_insn_detail(insn)
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last = insn
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print
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print "0x%x:\n" % (last.address + last.size)
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except:
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print("ERROR: Arch or mode unsupported!")
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@ -11,6 +11,15 @@ all_tests = (
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(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
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)
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def to_hex(s):
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return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
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def to_x(s):
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from struct import pack
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if not s: return '0'
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x = pack(">q", s).encode('hex')
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while x[0] == '0': x = x[1:]
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return x
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### Test class cs
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def test_class():
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@ -18,24 +27,15 @@ def test_class():
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# print address, mnemonic and operands
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print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
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if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
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print("\tCode condition: %u" %insn.cc)
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if insn.update_flags:
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print("\tUpdate-flags: True")
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if insn.writeback:
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print("\tWrite-back: True")
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if len(insn.operands) > 0:
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print("\top_count: %u" %len(insn.operands))
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c = 0
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c = -1
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for i in insn.operands:
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c += 1
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if i.type == ARM64_OP_REG:
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print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
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if i.type == ARM64_OP_IMM:
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print("\t\toperands[%u].type: IMM = %x" %(c, i.value.imm))
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print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
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if i.type == ARM64_OP_CIMM:
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print("\t\toperands[%u].type: C-IMM = %u" %(c, i.value.imm))
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if i.type == ARM64_OP_FP:
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@ -49,8 +49,8 @@ def test_class():
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print("\t\t\toperands[%u].mem.index: REG = %s" \
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%(c, insn.reg_name(i.value.mem.index)))
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if i.value.mem.disp != 0:
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print("\t\t\toperands[%u].mem.disp: %x" \
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%(c, i.value.mem.disp))
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print("\t\t\toperands[%u].mem.disp: 0x%s" \
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%(c, to_x(i.value.mem.disp)))
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if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
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print("\t\t\tShift: type = %u, value = %u" \
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@ -59,17 +59,27 @@ def test_class():
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if i.ext != ARM64_EXT_INVALID:
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print("\t\t\tExt: %u" %i.ext)
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if insn.writeback:
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print("\tWrite-back: True")
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if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
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print("\tCode condition: %u" %insn.cc)
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if insn.update_flags:
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print("\tUpdate-flags: True")
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for (arch, mode, code, comment) in all_tests:
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print("*" * 30)
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print("*" * 16)
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print("Platform: %s" %comment)
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print("Code: %s" % to_hex(code))
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print("Disasm:")
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try:
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md = cs(arch, mode)
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for insn in md.disasm(code, 0x1000):
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last = None
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for insn in md.disasm(code, 0x2c):
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print_insn_detail(insn)
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last = insn
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print
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print "0x%x:\n" % (last.address + last.size)
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except:
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print("ERROR: Arch or mode unsupported!")
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@ -13,6 +13,15 @@ all_tests = (
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(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
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)
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def to_hex(s):
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return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
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def to_x(s):
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from struct import pack
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if not s: return '0'
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x = pack(">q", s).encode('hex')
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while x[0] == '0': x = x[1:]
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return x
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### Test class cs
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def test_class():
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@ -22,33 +31,38 @@ def test_class():
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if len(insn.operands) > 0:
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print("\top_count: %u" %len(insn.operands))
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c = 0
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c = -1
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for i in insn.operands:
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c += 1
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if i.type == MIPS_OP_REG:
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print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
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if i.type == MIPS_OP_IMM:
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print("\t\toperands[%u].type: IMM = %x" %(c, i.value.imm))
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print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
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if i.type == MIPS_OP_MEM:
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print("\t\toperands[%u].type: MEM" %c)
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if i.value.mem.base != 0:
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print("\t\t\toperands[%u].mem.base: REG = %s" \
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%(c, insn.reg_name(i.value.mem.base)))
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if i.value.mem.disp != 0:
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print("\t\t\toperands[%u].mem.disp: %x" \
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%(c, i.value.mem.disp))
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print("\t\t\toperands[%u].mem.disp: 0x%s" \
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%(c, to_x(i.value.mem.disp)))
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for (arch, mode, code, comment) in all_tests:
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print("*" * 30)
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print("*" * 16)
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print("Platform: %s" %comment)
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print("Code: %s" % to_hex(code))
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print("Disasm:")
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try:
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md = cs(arch, mode)
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last = None
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for insn in md.disasm(code, 0x1000):
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print_insn_detail(insn)
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last = insn
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print
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print "0x%x:\n" %(insn.address + insn.size)
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except:
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print("ERROR: Arch or mode unsupported!")
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@ -5,18 +5,33 @@
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from capstone import *
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from capstone.x86 import *
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X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\xa1\x13\x48\x6d\x3a"
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X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\xa1\x13\x48\x6d\x3a"
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X86_CODE32 += "\x8d\x05\x34\x12\x00\x00"
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X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00"
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X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
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all_tests = (
|
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(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
|
||||
(CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32bit (ATT syntax)"),
|
||||
(CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32 (AT&T syntax)"),
|
||||
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
|
||||
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
|
||||
)
|
||||
|
||||
def to_hex(s):
|
||||
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
|
||||
|
||||
def to_x(s):
|
||||
from struct import pack
|
||||
if not s: return '0'
|
||||
x = pack(">q", s).encode('hex')
|
||||
while x[0] == '0': x = x[1:]
|
||||
return x
|
||||
|
||||
def to_x_32(s):
|
||||
from struct import pack
|
||||
if not s: return '0'
|
||||
x = pack(">i", s).encode('hex')
|
||||
while x[0] == '0': x = x[1:]
|
||||
return x
|
||||
|
||||
### Test class cs
|
||||
def test_class():
|
||||
|
|
@ -48,29 +63,31 @@ def test_class():
|
|||
print("\tmodrm: 0x%x" %(insn.modrm))
|
||||
|
||||
# print displacement value
|
||||
print("\tdisp: 0x%x" %(insn.disp))
|
||||
print("\tdisp: 0x%s" %to_x_32(insn.disp))
|
||||
|
||||
# SIB is not available in 16-bit mode
|
||||
if (mode & CS_MODE_16 == 0):
|
||||
# print SIB byte
|
||||
print("\tsib: 0x%x" %(insn.sib))
|
||||
if (insn.sib):
|
||||
print("\tsib_index: %s, sib_scale: %d, sib_base: %s" % (insn.reg_name(insn.sib_index), insn.sib_scale, insn.reg_name(insn.sib_base)))
|
||||
|
||||
count = insn.op_count(X86_OP_IMM)
|
||||
if count > 0:
|
||||
print("\timm_count: %u" %count)
|
||||
for i in xrange(count):
|
||||
index = insn.op_index(X86_OP_IMM, i + 1)
|
||||
print("\t\timms[%u] = 0x%x" %(i+1, (insn.operands[index].value.imm)))
|
||||
print("\t\timms[%u]: 0x%s" %(i+1, to_x(insn.operands[index].value.imm)))
|
||||
|
||||
if len(insn.operands) > 0:
|
||||
print("\top_count: %u" %len(insn.operands))
|
||||
c = 0
|
||||
c = -1
|
||||
for i in insn.operands:
|
||||
c += 1
|
||||
if i.type == X86_OP_REG:
|
||||
print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
|
||||
if i.type == X86_OP_IMM:
|
||||
print("\t\toperands[%u].type: IMM = 0x%x" %(c, i.value.imm))
|
||||
print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
|
||||
if i.type == X86_OP_FP:
|
||||
print("\t\toperands[%u].type: FP = %f" %(c, i.value.fp))
|
||||
if i.type == X86_OP_MEM:
|
||||
|
|
@ -82,21 +99,22 @@ def test_class():
|
|||
if i.value.mem.scale != 1:
|
||||
print("\t\t\toperands[%u].mem.scale: %u" %(c, i.value.mem.scale))
|
||||
if i.value.mem.disp != 0:
|
||||
print("\t\t\toperands[%u].mem.disp: 0x%x" %(c, i.value.mem.disp))
|
||||
print("\t\t\toperands[%u].mem.disp: 0x%s" %(c, to_x(i.value.mem.disp)))
|
||||
|
||||
|
||||
for (arch, mode, code, comment) in all_tests:
|
||||
print("*" * 30)
|
||||
print("*" * 16)
|
||||
print("Platform: %s" %comment)
|
||||
print("Code: %s" % to_hex(code))
|
||||
print("Disasm:")
|
||||
|
||||
try:
|
||||
md = cs(arch, mode)
|
||||
for insn in md.disasm(code, 0x1000):
|
||||
print_insn_detail(mode, insn)
|
||||
print
|
||||
except:
|
||||
print("ERROR: Arch or mode unsupported!")
|
||||
|
||||
md = cs(arch, mode)
|
||||
last = None
|
||||
for insn in md.disasm(code, 0x1000):
|
||||
print_insn_detail(mode, insn)
|
||||
last = insn
|
||||
print
|
||||
print ("0x%x:\n" % (last.address + last.size))
|
||||
|
||||
|
||||
test_class()
|
||||
|
|
|
|||
Loading…
Reference in New Issue