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move insn_cache into cs_struct to gurantee thread-safe

This commit is contained in:
Nguyen Anh Quynh 2014-01-06 10:56:59 +08:00
parent 8f7ab4981d
commit 1acfd0b883
19 changed files with 61 additions and 74 deletions
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17
arch/AArch64/mapping.c
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@ -2991,18 +2991,16 @@ static insn_map alias_insns[] = {
// { AArch64_SUBSxxx_lsl, ARM64_INS_NEGS, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } }, // { AArch64_SUBSxxx_lsl, ARM64_INS_NEGS, { 0 }, { ARM64_REG_NZCV, 0 }, { 0 } },
}; };
static unsigned short *insn_cache = NULL;
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void AArch64_get_insn_id(cs_insn *insn, unsigned int id, int detail) void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{ {
int i = insn_find(insns, ARR_SIZE(insns), id, &insn_cache); int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) { if (i != 0) {
insn->id = insns[i].mapid; insn->id = insns[i].mapid;
if (detail) { if (h->detail) {
cs_struct handle; cs_struct handle;
handle.detail = detail; handle.detail = h->detail;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = count_positive(insns[i].regs_use); insn->detail->regs_read_count = count_positive(insns[i].regs_use);
@ -3527,9 +3525,8 @@ arm64_reg AArch64_map_insn(const char *name)
return (i != -1)? i : ARM64_REG_INVALID; return (i != -1)? i : ARM64_REG_INVALID;
} }
void AArch64_free_cache(void) void AArch64_free_cache(cs_struct *h)
{ {
my_free(insn_cache); my_free(h->insn_cache);
h->insn_cache = NULL;
insn_cache = NULL;
} }

4
arch/AArch64/mapping.h
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@ -11,7 +11,7 @@
const char *AArch64_reg_name(csh handle, unsigned int reg); const char *AArch64_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void AArch64_get_insn_id(cs_insn *insn, unsigned int id, int detail); void AArch64_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal instruction ID // given public insn id, return internal instruction ID
unsigned int AArch64_get_insn_id2(unsigned int id); unsigned int AArch64_get_insn_id2(unsigned int id);
@ -22,6 +22,6 @@ const char *AArch64_insn_name(csh handle, unsigned int id);
arm64_reg AArch64_map_insn(const char *name); arm64_reg AArch64_map_insn(const char *name);
// free insn cache // free insn cache
void AArch64_free_cache(void); void AArch64_free_cache(cs_struct *h);
#endif #endif

2
arch/AArch64/module.c
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@ -32,7 +32,7 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
static void destroy(cs_struct *handle) static void destroy(cs_struct *handle)
{ {
AArch64_free_cache(); AArch64_free_cache(handle);
} }
static void __attribute__ ((constructor)) __init_arm64__() static void __attribute__ ((constructor)) __init_arm64__()

2
arch/ARM/ARMInstPrinter.c
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@ -563,7 +563,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
// to reflect absolute address. // to reflect absolute address.
// Note: in ARM, PC is always 2 instructions ahead, so we have to // Note: in ARM, PC is always 2 instructions ahead, so we have to
// add 8 in ARM mode, or 4 in Thumb mode // add 8 in ARM mode, or 4 in Thumb mode
if (ARM_rel_branch(MCInst_getOpcode(MI))) { if (ARM_rel_branch(MI->csh, MCInst_getOpcode(MI))) {
// only do this for relative branch // only do this for relative branch
if (MI->csh->mode & CS_MODE_THUMB) if (MI->csh->mode & CS_MODE_THUMB)
imm += MI->address + 4; imm += MI->address + 4;

21
arch/ARM/mapping.c
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@ -2301,17 +2301,15 @@ static insn_map insns[] = {
}; };
static unsigned short *insn_cache = NULL; void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
void ARM_get_insn_id(cs_insn *insn, unsigned int id, int detail)
{ {
int i = insn_find(insns, ARR_SIZE(insns), id, &insn_cache); int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) { if (i != 0) {
insn->id = insns[i].mapid; insn->id = insns[i].mapid;
if (detail) { if (h->detail) {
cs_struct handle; cs_struct handle;
handle.detail = detail; handle.detail = h->detail;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = count_positive(insns[i].regs_use); insn->detail->regs_read_count = count_positive(insns[i].regs_use);
@ -2791,9 +2789,9 @@ arm_reg ARM_map_insn(const char *name)
return (i != -1)? i : ARM_REG_INVALID; return (i != -1)? i : ARM_REG_INVALID;
} }
bool ARM_rel_branch(unsigned int id) bool ARM_rel_branch(cs_struct *h, unsigned int id)
{ {
int i = insn_find(insns, ARR_SIZE(insns), id, &insn_cache); int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) if (i != 0)
return (insns[i].branch && !insns[i].indirect_branch); return (insns[i].branch && !insns[i].indirect_branch);
else { else {
@ -2802,9 +2800,8 @@ bool ARM_rel_branch(unsigned int id)
} }
} }
void ARM_free_cache(void) void ARM_free_cache(cs_struct *h)
{ {
my_free(insn_cache); my_free(h->insn_cache);
h->insn_cache = NULL;
insn_cache = NULL;
} }

6
arch/ARM/mapping.h
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@ -12,7 +12,7 @@
const char *ARM_reg_name(csh handle, unsigned int reg); const char *ARM_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction ID // given internal insn id, return public instruction ID
void ARM_get_insn_id(cs_insn *insn, unsigned int id, int detail); void ARM_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal instruction info // given public insn id, return internal instruction info
unsigned int ARM_get_insn_id2(unsigned int id); unsigned int ARM_get_insn_id2(unsigned int id);
@ -23,9 +23,9 @@ const char *ARM_insn_name(csh handle, unsigned int id);
arm_reg ARM_map_insn(const char *name); arm_reg ARM_map_insn(const char *name);
// check if this insn is relative branch // check if this insn is relative branch
bool ARM_rel_branch(unsigned int insn_id); bool ARM_rel_branch(cs_struct *h, unsigned int insn_id);
// free insn cache // free insn cache
void ARM_free_cache(void); void ARM_free_cache(cs_struct *h);
#endif #endif

2
arch/ARM/module.c
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@ -45,7 +45,7 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
static void destroy(cs_struct *handle) static void destroy(cs_struct *handle)
{ {
ARM_free_cache(); ARM_free_cache(handle);
} }
static void __attribute__ ((constructor)) __init_arm__() static void __attribute__ ((constructor)) __init_arm__()

17
arch/Mips/mapping.c
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@ -1388,10 +1388,8 @@ static insn_map alias_insns[] = {
{ Mips_SUBu, MIPS_INS_NEGU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 }, { Mips_SUBu, MIPS_INS_NEGU, { 0 }, { 0 }, { MIPS_GRP_STDENC, 0 }, 0, 0 },
}; };
static unsigned short *insn_cache = NULL;
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void Mips_get_insn_id(cs_insn *insn, unsigned int id, int detail) void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{ {
int i; int i;
@ -1400,7 +1398,7 @@ void Mips_get_insn_id(cs_insn *insn, unsigned int id, int detail)
if (alias_insns[i].id == id) { if (alias_insns[i].id == id) {
insn->id = alias_insns[i].mapid; insn->id = alias_insns[i].mapid;
if (detail) { if (h->detail) {
memcpy(insn->detail->regs_read, alias_insns[i].regs_use, sizeof(alias_insns[i].regs_use)); memcpy(insn->detail->regs_read, alias_insns[i].regs_use, sizeof(alias_insns[i].regs_use));
insn->detail->regs_read_count = count_positive(alias_insns[i].regs_use); insn->detail->regs_read_count = count_positive(alias_insns[i].regs_use);
@ -1421,11 +1419,11 @@ void Mips_get_insn_id(cs_insn *insn, unsigned int id, int detail)
} }
} }
i = insn_find(insns, ARR_SIZE(insns), id, &insn_cache); i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) { if (i != 0) {
insn->id = insns[i].mapid; insn->id = insns[i].mapid;
if (detail) { if (h->detail) {
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = count_positive(insns[i].regs_use); insn->detail->regs_read_count = count_positive(insns[i].regs_use);
@ -2035,9 +2033,8 @@ mips_reg Mips_map_register(unsigned int r)
return 0; return 0;
} }
void Mips_free_cache(void) void Mips_free_cache(cs_struct *h)
{ {
my_free(insn_cache); my_free(h->insn_cache);
h->insn_cache = NULL;
insn_cache = NULL;
} }

4
arch/Mips/mapping.h
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@ -11,7 +11,7 @@
const char *Mips_reg_name(csh handle, unsigned int reg); const char *Mips_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void Mips_get_insn_id(cs_insn *insn, unsigned int id, int detail); void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal insn id // given public insn id, return internal insn id
unsigned int Mips_get_insn_id2(unsigned int id); unsigned int Mips_get_insn_id2(unsigned int id);
@ -26,6 +26,6 @@ mips_reg Mips_map_insn(const char *name);
mips_reg Mips_map_register(unsigned int r); mips_reg Mips_map_register(unsigned int r);
// free insn cache // free insn cache
void Mips_free_cache(void); void Mips_free_cache(cs_struct *h);
#endif #endif

2
arch/Mips/module.c
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@ -43,7 +43,7 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
static void destroy(cs_struct *handle) static void destroy(cs_struct *handle)
{ {
Mips_free_cache(); Mips_free_cache(handle);
} }
static void __attribute__ ((constructor)) __init_mips__() static void __attribute__ ((constructor)) __init_mips__()

21
arch/PowerPC/mapping.c
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@ -917,10 +917,8 @@ static insn_map insns[] = {
static insn_map alias_insns[] = { static insn_map alias_insns[] = {
}; };
static unsigned short *insn_cache = NULL;
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void PPC_get_insn_id(cs_insn *insn, unsigned int id, int detail) void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{ {
int i; int i;
@ -929,9 +927,9 @@ void PPC_get_insn_id(cs_insn *insn, unsigned int id, int detail)
if (alias_insns[i].id == id) { if (alias_insns[i].id == id) {
insn->id = alias_insns[i].mapid; insn->id = alias_insns[i].mapid;
if (detail) { if (h->detail) {
cs_struct handle; cs_struct handle;
handle.detail = detail; handle.detail = h->detail;
memcpy(insn->detail->regs_read, alias_insns[i].regs_use, sizeof(alias_insns[i].regs_use)); memcpy(insn->detail->regs_read, alias_insns[i].regs_use, sizeof(alias_insns[i].regs_use));
insn->detail->regs_read_count = count_positive(alias_insns[i].regs_use); insn->detail->regs_read_count = count_positive(alias_insns[i].regs_use);
@ -954,13 +952,13 @@ void PPC_get_insn_id(cs_insn *insn, unsigned int id, int detail)
} }
} }
i = insn_find(insns, ARR_SIZE(insns), id, &insn_cache); i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) { if (i != 0) {
insn->id = insns[i].mapid; insn->id = insns[i].mapid;
if (detail) { if (h->detail) {
cs_struct handle; cs_struct handle;
handle.detail = detail; handle.detail = h->detail;
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = count_positive(insns[i].regs_use); insn->detail->regs_read_count = count_positive(insns[i].regs_use);
@ -1516,9 +1514,8 @@ ppc_reg PPC_map_register(unsigned int r)
return 0; return 0;
} }
void PPC_free_cache(void) void PPC_free_cache(cs_struct *h)
{ {
my_free(insn_cache); my_free(h->insn_cache);
h->insn_cache = NULL;
insn_cache = NULL;
} }

4
arch/PowerPC/mapping.h
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@ -11,7 +11,7 @@
const char *PPC_reg_name(csh handle, unsigned int reg); const char *PPC_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void PPC_get_insn_id(cs_insn *insn, unsigned int id, int detail); void PPC_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// given public insn id, return internal insn id // given public insn id, return internal insn id
unsigned int PPC_get_insn_id2(unsigned int id); unsigned int PPC_get_insn_id2(unsigned int id);
@ -26,7 +26,7 @@ ppc_reg PPC_map_insn(const char *name);
ppc_reg PPC_map_register(unsigned int r); ppc_reg PPC_map_register(unsigned int r);
// free insn cache // free insn cache
void PPC_free_cache(void); void PPC_free_cache(cs_struct *);
#endif #endif

2
arch/PowerPC/module.c
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@ -36,7 +36,7 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
static void destroy(cs_struct *handle) static void destroy(cs_struct *handle)
{ {
PPC_free_cache(); PPC_free_cache(handle);
} }
static void __attribute__ ((constructor)) __init_mips__() static void __attribute__ ((constructor)) __init_mips__()

14
arch/X86/mapping.c
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@ -6605,16 +6605,14 @@ void X86_post_printer(csh handle, cs_insn *insn, char *insn_asm)
} }
} }
static unsigned short *insn_cache = NULL;
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void X86_get_insn_id(cs_insn *insn, unsigned int id, int detail) void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{ {
int i = insn_find(insns, ARR_SIZE(insns), id, &insn_cache); int i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) { if (i != 0) {
insn->id = insns[i].mapid; insn->id = insns[i].mapid;
if (detail) { if (h->detail) {
memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = count_positive(insns[i].regs_use); insn->detail->regs_read_count = count_positive(insns[i].regs_use);
@ -6639,8 +6637,8 @@ unsigned int X86_get_insn_id2(unsigned int id)
return insn_reverse_id(insns, ARR_SIZE(insns), id); return insn_reverse_id(insns, ARR_SIZE(insns), id);
} }
void X86_free_cache(void) void X86_free_cache(cs_struct *h)
{ {
my_free(insn_cache); my_free(h->insn_cache);
insn_cache = NULL; h->insn_cache = NULL;
} }

5
arch/X86/mapping.h
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@ -6,6 +6,7 @@
#include "../../include/capstone.h" #include "../../include/capstone.h"
#include "../../include/x86.h" #include "../../include/x86.h"
#include "../../cs_priv.h"
// map sib_base to x86_reg // map sib_base to x86_reg
x86_reg x86_map_sib_base(int r); x86_reg x86_map_sib_base(int r);
@ -23,7 +24,7 @@ x86_reg x86_map_regname(const char *reg);
const char *X86_reg_name(csh handle, unsigned int reg); const char *X86_reg_name(csh handle, unsigned int reg);
// given internal insn id, return public instruction info // given internal insn id, return public instruction info
void X86_get_insn_id(cs_insn *insn, unsigned int id, int detail); void X86_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
// return insn name, given insn id // return insn name, given insn id
const char *X86_insn_name(csh handle, unsigned int id); const char *X86_insn_name(csh handle, unsigned int id);
@ -38,6 +39,6 @@ unsigned int X86_get_insn_id2(unsigned int insn_id);
void X86_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm); void X86_post_printer(csh handle, cs_insn *pub_insn, char *insn_asm);
// free insn cache // free insn cache
void X86_free_cache(void); void X86_free_cache(cs_struct *h);
#endif #endif

2
arch/X86/module.c
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@ -46,7 +46,7 @@ static cs_err option(cs_struct *handle, cs_opt_type type, size_t value)
static void destroy(cs_struct *handle) static void destroy(cs_struct *handle)
{ {
X86_free_cache(); X86_free_cache(handle);
} }
static void __attribute__ ((constructor)) __init_x86__() static void __attribute__ ((constructor)) __init_x86__()

3
cs.c
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@ -138,7 +138,6 @@ cs_err cs_close(csh handle)
return CS_ERR_HANDLE; return CS_ERR_HANDLE;
} }
if (arch_destroy[ud->arch])
arch_destroy[ud->arch](ud); arch_destroy[ud->arch](ud);
memset(ud, 0, sizeof(*ud)); memset(ud, 0, sizeof(*ud));
@ -174,7 +173,7 @@ static void fill_insn(cs_struct *handle, cs_insn *insn, char *buffer, MCInst *mc
// map internal instruction opcode to public insn ID // map internal instruction opcode to public insn ID
if (handle->insn_id) if (handle->insn_id)
handle->insn_id(insn, MCInst_getOpcode(mci), handle->detail); handle->insn_id(handle, insn, MCInst_getOpcode(mci));
// alias instruction might have ID saved in OpcodePub // alias instruction might have ID saved in OpcodePub
if (MCInst_getOpcodePub(mci)) if (MCInst_getOpcodePub(mci))

3
cs_priv.h
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@ -19,7 +19,7 @@ typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCIns
typedef const char *(*GetName_t)(csh handle, unsigned int reg); typedef const char *(*GetName_t)(csh handle, unsigned int reg);
typedef void (*GetID_t)(cs_insn *insn, unsigned int id, int detail); typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
// for ARM only // for ARM only
typedef struct ARM_ITStatus { typedef struct ARM_ITStatus {
@ -44,6 +44,7 @@ struct cs_struct {
cs_opt_value detail; cs_opt_value detail;
int syntax; // asm syntax for simple printer such as PPC int syntax; // asm syntax for simple printer such as PPC
bool doing_mem; // handling memory operand in InstPrinter code bool doing_mem; // handling memory operand in InstPrinter code
unsigned short *insn_cache; // index caching for mapping.c
}; };
#define MAX_ARCH 8 #define MAX_ARCH 8