Virtualization
/
capstone
mirror of https://gitlab.com/qemu-project/capstone.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix python binding tests

This commit is contained in:
danghvu 2014-09-27 17:59:42 -05:00
parent ef92cdb918
commit 2412069453
6 changed files with 19 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
bindings/python/test_arm.py
View File

@ -47,9 +47,9 @@ def print_insn_detail(insn):
print("\t\toperands[%u].type: SYSREG = %u" % (c, i.reg))
if i.type == ARM_OP_SETEND:
if i.setend == ARM_SETEND_BE:
print("\t\toperands[%u].type: SETEND = be")
print("\t\toperands[%u].type: SETEND = be" % c)
else:
print("\t\toperands[%u].type: SETEND = le")
print("\t\toperands[%u].type: SETEND = le" % c)
if i.type == ARM_OP_MEM:
print("\t\toperands[%u].type: MEM" % c)
if i.mem.base != 0:
@ -66,7 +66,7 @@ def print_insn_detail(insn):
% (c, to_x_32(i.mem.disp)))
if i.shift.type != ARM_SFT_INVALID and i.shift.value:
print("\t\t\tShift: type = %u, value = %u\n" \
print("\t\t\tShift: %u = %u" \
% (i.shift.type, i.shift.value))
if i.vector_index != -1:
print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index))

2
bindings/python/test_arm64.py
View File

@ -78,7 +78,7 @@ def print_insn_detail(insn):
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
print("\tCode condition: %u" % insn.cc)
print("\tCode-condition: %u" % insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")

2
bindings/python/test_ppc.py
View File

@ -5,7 +5,7 @@ from __future__ import print_function
from capstone import *
from capstone.ppc import *
from xprint import to_x, to_hex, to_x_32
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
all_tests = (
(CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64"),

5
bindings/python/test_sparc.py
View File

@ -38,6 +38,9 @@ def print_insn_detail(insn):
if i.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
% (c, insn.reg_name(i.mem.base)))
if i.mem.index != 0:
print("\t\t\toperands[%u].mem.index: REG = %s" \
% (c, insn.reg_name(i.mem.index)))
if i.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x_32(i.mem.disp)))
@ -46,7 +49,7 @@ def print_insn_detail(insn):
if insn.cc:
print("\tCode condition: %u" % insn.cc)
if insn.hint:
print("\tBranch hint: %u" % insn.hint)
print("\tHint code: %u" % insn.hint)
# ## Test class Cs

2
bindings/python/test_xcore.py
View File

@ -43,7 +43,7 @@ def print_insn_detail(insn):
print("\t\t\toperands[%u].mem.disp: 0x%s" \
% (c, to_x(i.mem.disp)))
if i.mem.direct != 1:
print("\t\t\toperands[%u].mem.direct: -1")
print("\t\t\toperands[%u].mem.direct: -1" % c)
c += 1

18
bindings/python/xprint.py
View File

@ -12,24 +12,24 @@ def to_hex(s):
else:
return " ".join("0x{0:02x}".format(ord(c)) for c in s)
def to_hex2(s):
if _python3:
r = "".join("{0:02x}".format(c) for c in s) # <-- Python 3 is OK
else:
r = "".join("{0:02x}".format(ord(c)) for c in s)
while r[0] == '0': r = r[1:]
return r
def to_x(s):
from struct import pack
if not s: return '0'
x = pack(">q", s)
while x[0] in ('\0', 0): x = x[1:]
if _python3:
return "".join("{0:02x}".format(c) for c in x) # <-- Python 3 is OK
else:
return "".join("{0:02x}".format(ord(c)) for c in x)
return to_hex2(x)
def to_x_32(s):
from struct import pack
if not s: return '0'
x = pack(">i", s)
while x[0] in ('\0', 0): x = x[1:]
if _python3:
return "".join("{0:02x}".format(c) for c in x) # <-- Python 3 is OK
else:
return "".join("{0:02x}".format(ord(c)) for c in x)
return to_hex2(x)