From 2785d31399a30283e9f70991ac8edb7c4e0f665c Mon Sep 17 00:00:00 2001 From: billow Date: Thu, 20 Apr 2023 21:55:37 +0800 Subject: [PATCH] Format all .(c|h) code --- arch/TriCore/TriCoreDisassembler.c | 609 +++++++++++++++++------------ arch/TriCore/TriCoreDisassembler.h | 4 +- arch/TriCore/TriCoreInstPrinter.c | 506 +++++++++++++----------- arch/TriCore/TriCoreMapping.c | 57 +-- arch/TriCore/TriCoreMapping.h | 1 - arch/TriCore/TriCoreModule.c | 2 +- cstool/cstool_tricore.c | 108 ++--- include/capstone/tricore.h | 26 +- suite/cstest/src/tricore_detail.c | 119 +++--- tests/test_tricore.c | 66 ++-- 10 files changed, 840 insertions(+), 658 deletions(-) diff --git a/arch/TriCore/TriCoreDisassembler.c b/arch/TriCore/TriCoreDisassembler.c index a4fcf49a..91ccdbdc 100644 --- a/arch/TriCore/TriCoreDisassembler.c +++ b/arch/TriCore/TriCoreDisassembler.c @@ -12,7 +12,7 @@ #ifdef CAPSTONE_HAS_TRICORE -#include // DEBUG +#include // DEBUG #include #include @@ -26,7 +26,9 @@ #include "../../MCDisassembler.h" #include "../../MathExtras.h" -static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *insn) { +static bool readInstruction16(const uint8_t *code, size_t code_len, + uint16_t *insn) +{ if (code_len < 2) // insufficient data return false; @@ -36,158 +38,182 @@ static bool readInstruction16(const uint8_t *code, size_t code_len, uint16_t *in return true; } -static bool readInstruction32(const uint8_t *code, size_t code_len, uint32_t *insn) { +static bool readInstruction32(const uint8_t *code, size_t code_len, + uint32_t *insn) +{ if (code_len < 4) // insufficient data return false; // Encoded as a little-endian 32-bit word in the stream. - *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | (code[3] << 24); + *insn = (code[0] << 0) | (code[1] << 8) | (code[2] << 16) | + (code[3] << 24); return true; } -static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) { +static unsigned getReg(MCRegisterInfo *MRI, unsigned RC, unsigned RegNo) +{ const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC); return rc->RegsBegin[RegNo]; } -#define tryDecodeReg(i, x) \ - status = DecodeRegisterClass(Inst, (x), &desc->OpInfo[(i)], Decoder); \ - if (status != MCDisassembler_Success) \ - return status; +#define tryDecodeReg(i, x) \ + status = DecodeRegisterClass(Inst, (x), &desc->OpInfo[(i)], Decoder); \ + if (status != MCDisassembler_Success) \ + return status; -#define decodeImm(x) \ - MCOperand_CreateImm0(Inst, (x)); +#define decodeImm(x) MCOperand_CreateImm0(Inst, (x)); static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder); + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); -static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); - -static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder); +static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); +static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder); #define GET_SUBTARGETINFO_ENUM #include "TriCoreGenSubtargetInfo.inc" - -bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature) { +bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature) +{ switch (mode) { - case CS_MODE_TRICORE_110: { - return feature == TriCore_HasV110Ops; - } - case CS_MODE_TRICORE_120: { - return feature == TriCore_HasV120Ops; - } - case CS_MODE_TRICORE_130: { - return feature == TriCore_HasV130Ops; - } - case CS_MODE_TRICORE_131: { - return feature == TriCore_HasV131Ops; - } - case CS_MODE_TRICORE_160: { - return feature == TriCore_HasV160Ops; - } - case CS_MODE_TRICORE_161: { - return feature == TriCore_HasV161Ops; - } - case CS_MODE_TRICORE_162: { - return feature == TriCore_HasV162Ops; - } - default: - return false; + case CS_MODE_TRICORE_110: { + return feature == TriCore_HasV110Ops; + } + case CS_MODE_TRICORE_120: { + return feature == TriCore_HasV120Ops; + } + case CS_MODE_TRICORE_130: { + return feature == TriCore_HasV130Ops; + } + case CS_MODE_TRICORE_131: { + return feature == TriCore_HasV131Ops; + } + case CS_MODE_TRICORE_160: { + return feature == TriCore_HasV160Ops; + } + case CS_MODE_TRICORE_161: { + return feature == TriCore_HasV161Ops; + } + case CS_MODE_TRICORE_162: { + return feature == TriCore_HasV162Ops; + } + default: + return false; } } - #include "TriCoreGenDisassemblerTables.inc" #define GET_REGINFO_ENUM @@ -195,8 +221,10 @@ bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature) { #include "TriCoreGenRegisterInfo.inc" -static DecodeStatus -DecodeRegisterClass(MCInst *Inst, unsigned RegNo, const MCOperandInfo *MCOI, void *Decoder) { +static DecodeStatus DecodeRegisterClass(MCInst *Inst, unsigned RegNo, + const MCOperandInfo *MCOI, + void *Decoder) +{ unsigned Reg; unsigned RegHalfNo = RegNo / 2; @@ -224,7 +252,8 @@ DecodeRegisterClass(MCInst *Inst, unsigned RegNo, const MCOperandInfo *MCOI, voi #include "TriCoreGenInstrInfo.inc" static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ unsigned disp8 = fieldFromInstruction_2(Insn, 8, 8); unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1); @@ -238,7 +267,8 @@ static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned s2 = fieldFromInstruction_2(Insn, 12, 4); unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4); @@ -259,7 +289,8 @@ static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ unsigned const8 = fieldFromInstruction_2(Insn, 8, 8); unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1); @@ -273,7 +304,8 @@ static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4); unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1); @@ -283,13 +315,15 @@ static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn, const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; if (desc->NumOperands > 0) { - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], + Decoder); if (status != MCDisassembler_Success) return status; } if (desc->NumOperands > 1) { - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], Decoder); + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], + Decoder); if (status != MCDisassembler_Success) return status; } @@ -298,7 +332,8 @@ static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned const4 = fieldFromInstruction_2(Insn, 12, 4); unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4); @@ -321,7 +356,8 @@ static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned s2 = fieldFromInstruction_2(Insn, 12, 4); unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4); @@ -336,7 +372,6 @@ static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn, if (status != MCDisassembler_Success) return status; - // Decode s2. status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder); if (status != MCDisassembler_Success) @@ -346,15 +381,15 @@ static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { - + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned off18_0 = fieldFromInstruction_4(Insn, 16, 6); unsigned off18_1 = fieldFromInstruction_4(Insn, 28, 4); unsigned off18_2 = fieldFromInstruction_4(Insn, 22, 4); unsigned off18_3 = fieldFromInstruction_4(Insn, 12, 4); - unsigned off18 = (off18_0 << 0) | (off18_1 << 6) | - (off18_2 << 10) | (off18_3 << 14); + unsigned off18 = (off18_0 << 0) | (off18_1 << 6) | (off18_2 << 10) | + (off18_3 << 14); unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4); unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1); @@ -366,14 +401,16 @@ static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn, if (desc->NumOperands > 1) { if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) { - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s1_d, + &desc->OpInfo[0], Decoder); if (status != MCDisassembler_Success) return status; MCOperand_CreateImm0(Inst, off18); } else { MCOperand_CreateImm0(Inst, off18); - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s1_d, + &desc->OpInfo[0], Decoder); if (status != MCDisassembler_Success) return status; } @@ -385,7 +422,8 @@ static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ unsigned disp24_0 = fieldFromInstruction_4(Insn, 16, 16); unsigned disp24_1 = fieldFromInstruction_4(Insn, 8, 8); unsigned disp24 = (disp24_0 << 0) | (disp24_1 << 16); @@ -402,7 +440,8 @@ static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned off10_0 = fieldFromInstruction_4(Insn, 16, 6); unsigned off10_1 = fieldFromInstruction_4(Insn, 28, 4); @@ -423,12 +462,14 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, } if (desc->NumOperands == 2) { - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], + Decoder); if (status != MCDisassembler_Success) return status; if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) { - return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], Decoder); + return DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], + Decoder); } else { MCOperand_CreateImm0(Inst, off10); } @@ -436,11 +477,13 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, } if (desc->NumOperands > 2) { - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], + Decoder); if (status != MCDisassembler_Success) return status; - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder); + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], + Decoder); if (status != MCDisassembler_Success) return status; @@ -451,7 +494,8 @@ static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned off16_0 = fieldFromInstruction_4(Insn, 16, 6); unsigned off16_1 = fieldFromInstruction_4(Insn, 22, 6); @@ -468,41 +512,45 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn, const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; switch (MCInst_getOpcode(Inst)) { - case TriCore_LD_A_bol: - case TriCore_LD_B_bol: - case TriCore_LD_BU_bol: - case TriCore_LD_H_bol: - case TriCore_LD_HU_bol: - case TriCore_LD_W_bol: - case TriCore_LEA_bol: { - // Decode s1_d. - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder); - if (status != MCDisassembler_Success) - return status; + case TriCore_LD_A_bol: + case TriCore_LD_B_bol: + case TriCore_LD_BU_bol: + case TriCore_LD_H_bol: + case TriCore_LD_HU_bol: + case TriCore_LD_W_bol: + case TriCore_LEA_bol: { + // Decode s1_d. + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; - // Decode s2. - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder); - if (status != MCDisassembler_Success) - return status; - break; - } - case TriCore_ST_A_bol: - case TriCore_ST_B_bol: - case TriCore_ST_H_bol: - case TriCore_ST_W_bol: { - // Decode s2. - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder); - if (status != MCDisassembler_Success) - return status; + // Decode s2. + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], + Decoder); + if (status != MCDisassembler_Success) + return status; + break; + } + case TriCore_ST_A_bol: + case TriCore_ST_B_bol: + case TriCore_ST_H_bol: + case TriCore_ST_W_bol: { + // Decode s2. + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], + Decoder); + if (status != MCDisassembler_Success) + return status; - // Decode s1_d. - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], Decoder); - if (status != MCDisassembler_Success) - return status; - break; - } - default: - return MCDisassembler_Fail; + // Decode s1_d. + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1], + Decoder); + if (status != MCDisassembler_Success) + return status; + break; + } + default: + return MCDisassembler_Fail; } // Decode off16. @@ -512,7 +560,8 @@ static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned d = fieldFromInstruction_4(Insn, 28, 4); unsigned const9 = fieldFromInstruction_4(Insn, 12, 9); @@ -526,12 +575,14 @@ static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn, const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; if (desc->NumOperands > 1) { // Decode d. - status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); + status = + DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); if (status != MCDisassembler_Success) return status; // Decode s1. - status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder); + status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], + Decoder); if (status != MCDisassembler_Success) return status; } @@ -543,7 +594,8 @@ static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned d = fieldFromInstruction_4(Insn, 28, 4); unsigned pos = fieldFromInstruction_4(Insn, 23, 5); @@ -580,7 +632,8 @@ static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned d = fieldFromInstruction_4(Insn, 28, 4); unsigned const16 = fieldFromInstruction_4(Insn, 12, 16); @@ -593,11 +646,13 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn, const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; if (desc->NumOperands == 3) { - status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); + status = + DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); if (status != MCDisassembler_Success) return status; - status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder); + status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], + Decoder); if (status != MCDisassembler_Success) return status; @@ -607,14 +662,16 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn, } if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) { - status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); + status = + DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); if (status != MCDisassembler_Success) return status; MCOperand_CreateImm0(Inst, const16); } else { MCOperand_CreateImm0(Inst, const16); - status = DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder); + status = + DecodeRegisterClass(Inst, d, &desc->OpInfo[1], Decoder); if (status != MCDisassembler_Success) return status; } @@ -622,7 +679,8 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned d = fieldFromInstruction_4(Insn, 28, 4); unsigned n = fieldFromInstruction_4(Insn, 16, 2); @@ -640,12 +698,14 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn, if (desc->NumOperands == 1) { if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) { switch (MCInst_getOpcode(Inst)) { - case TriCore_CALLI_rr_v110: { - return DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder); - } - default: { - return DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], Decoder); - } + case TriCore_CALLI_rr_v110: { + return DecodeRegisterClass( + Inst, s2, &desc->OpInfo[0], Decoder); + } + default: { + return DecodeRegisterClass( + Inst, s1, &desc->OpInfo[0], Decoder); + } } } return MCDisassembler_Fail; @@ -653,30 +713,36 @@ static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn, if (desc->NumOperands > 0) { // Decode d. - status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); + status = + DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); if (status != MCDisassembler_Success) return status; } if (desc->NumOperands > 1) { - status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], Decoder); + status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1], + Decoder); if (status != MCDisassembler_Success) return status; } if (desc->NumOperands > 2) { - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], Decoder); + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2], + Decoder); if (status != MCDisassembler_Success) return status; } - if (desc->NumOperands > 3) { MCOperand_CreateImm0(Inst, n); } + if (desc->NumOperands > 3) { + MCOperand_CreateImm0(Inst, n); + } return MCDisassembler_Success; } static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned d = fieldFromInstruction_4(Insn, 28, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -707,7 +773,8 @@ static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn, } static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn, - uint64_t Address, void *Decoder) { + uint64_t Address, void *Decoder) +{ DecodeStatus status; unsigned d = fieldFromInstruction_4(Insn, 28, 4); unsigned pos = fieldFromInstruction_4(Insn, 23, 5); @@ -721,16 +788,15 @@ static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn, return MCDisassembler_Fail; const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; - tryDecodeReg(0, d) - tryDecodeReg(1, s1) - tryDecodeReg(2, s2) - decodeImm(pos) - decodeImm(width) + tryDecodeReg(0, d) tryDecodeReg(1, s1) tryDecodeReg(2, s2) + decodeImm(pos) decodeImm(width) - return MCDisassembler_Success; + return MCDisassembler_Success; } -static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned d = fieldFromInstruction_2(Insn, 8, 4); unsigned s2 = fieldFromInstruction_2(Insn, 12, 4); @@ -752,7 +818,9 @@ static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned d = fieldFromInstruction_2(Insn, 8, 4); unsigned off4 = fieldFromInstruction_2(Insn, 12, 4); @@ -772,7 +840,9 @@ static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned off4 = fieldFromInstruction_2(Insn, 8, 4); unsigned s2 = fieldFromInstruction_2(Insn, 12, 4); @@ -792,7 +862,9 @@ static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned n = fieldFromInstruction_2(Insn, 6, 2); unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4); @@ -819,7 +891,9 @@ static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4); unsigned const4 = fieldFromInstruction_2(Insn, 12, 4); unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1); @@ -840,7 +914,9 @@ static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4); unsigned n = fieldFromInstruction_2(Insn, 12, 4); unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1); @@ -855,7 +931,9 @@ static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_2(Insn, 8, 4); unsigned s2 = fieldFromInstruction_2(Insn, 12, 4); @@ -878,7 +956,9 @@ static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_2(Insn, 8, 4); unsigned off4 = fieldFromInstruction_2(Insn, 12, 4); @@ -899,7 +979,9 @@ static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t /// 32-bit Opcode Format -static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4); @@ -909,7 +991,8 @@ static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t A const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; if (desc->NumOperands > 0) { - status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0], + Decoder); if (status != MCDisassembler_Success) return status; } @@ -917,7 +1000,9 @@ static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -951,7 +1036,9 @@ static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -989,7 +1076,9 @@ static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -1025,7 +1114,9 @@ static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -1057,7 +1148,9 @@ static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned const9 = fieldFromInstruction_4(Insn, 12, 9); @@ -1089,7 +1182,9 @@ static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -1127,7 +1222,9 @@ static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned const4 = fieldFromInstruction_4(Insn, 12, 4); @@ -1138,7 +1235,6 @@ static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t if (!is32Bit) // This instruction is 32-bit return MCDisassembler_Fail; - const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0], Decoder); if (status != MCDisassembler_Success) @@ -1160,7 +1256,9 @@ static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -1197,7 +1295,9 @@ static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Success; } -static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); @@ -1209,7 +1309,8 @@ static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; if (MCInst_getOpcode(Inst) == TriCore_LOOP_brr) { - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0], + Decoder); if (status != MCDisassembler_Success) return status; @@ -1218,12 +1319,14 @@ static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A } if (desc->NumOperands >= 2) { - status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], Decoder); + status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0], + Decoder); if (status != MCDisassembler_Success) return status; if (desc->NumOperands >= 3) { - status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], Decoder); + status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1], + Decoder); if (status != MCDisassembler_Success) return status; } @@ -1235,7 +1338,9 @@ static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned const4 = fieldFromInstruction_4(Insn, 12, 4); @@ -1259,11 +1364,13 @@ static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned s2 = fieldFromInstruction_4(Insn, 12, 4); -// unsigned n = fieldFromInstruction_4(Insn, 16, 2); + // unsigned n = fieldFromInstruction_4(Insn, 16, 2); unsigned s3 = fieldFromInstruction_4(Insn, 24, 4); unsigned d = fieldFromInstruction_4(Insn, 28, 4); @@ -1294,7 +1401,9 @@ static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A return MCDisassembler_Success; } -static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ unsigned bpos3 = fieldFromInstruction_4(Insn, 8, 3); unsigned b = fieldFromInstruction_4(Insn, 12, 1); @@ -1303,20 +1412,20 @@ static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t unsigned off18_10_13 = fieldFromInstruction_4(Insn, 22, 4); unsigned off18_14_17 = fieldFromInstruction_4(Insn, 12, 4); unsigned off18 = (off18_0_5 << 0) | (off18_6_9 << 6) | - (off18_10_13 << 10) | (off18_14_17 << 14); + (off18_10_13 << 10) | (off18_14_17 << 14); unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1); if (!is32Bit) // This instruction is 32-bit return MCDisassembler_Fail; - decodeImm(off18) - decodeImm(bpos3) - decodeImm(b) + decodeImm(off18) decodeImm(bpos3) decodeImm(b) - return MCDisassembler_Success; + return MCDisassembler_Success; } -static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); unsigned const4 = fieldFromInstruction_4(Insn, 12, 4); @@ -1329,16 +1438,15 @@ static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t return MCDisassembler_Fail; const MCInstrDesc *desc = &TriCoreInsts[MCInst_getOpcode(Inst)]; - tryDecodeReg(0, d) - tryDecodeReg(1, s1) - tryDecodeReg(2, s3) - decodeImm(const4) - decodeImm(width) + tryDecodeReg(0, d) tryDecodeReg(1, s1) tryDecodeReg(2, s3) + decodeImm(const4) decodeImm(width) - return MCDisassembler_Success; + return MCDisassembler_Success; } -static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder) { +static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, + uint64_t Address, void *Decoder) +{ DecodeStatus status = MCDisassembler_Fail; unsigned s1 = fieldFromInstruction_4(Insn, 8, 4); @@ -1370,16 +1478,19 @@ static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t A #include "TriCoreGenInstrInfo.inc" -static inline bool tryGetInstruction16(const uint8_t *code, size_t code_len, MCInst *MI, - uint16_t *size, uint64_t address, void *info, - const uint8_t *decoderTable16) { +static inline bool tryGetInstruction16(const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, + uint64_t address, void *info, + const uint8_t *decoderTable16) +{ uint16_t insn16; DecodeStatus Result; if (!readInstruction16(code, code_len, &insn16)) { return false; } // Calling the auto-generated decoder function. - Result = decodeInstruction_2(decoderTable16, MI, insn16, address, info, 0); + Result = decodeInstruction_2(decoderTable16, MI, insn16, address, info, + 0); if (Result != MCDisassembler_Fail) { *size = 2; return true; @@ -1387,16 +1498,19 @@ static inline bool tryGetInstruction16(const uint8_t *code, size_t code_len, MCI return false; } -static inline bool tryGetInstruction32(const uint8_t *code, size_t code_len, MCInst *MI, - uint16_t *size, uint64_t address, void *info, - const uint8_t *decoderTable32) { +static inline bool tryGetInstruction32(const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, + uint64_t address, void *info, + const uint8_t *decoderTable32) +{ uint32_t insn32; DecodeStatus Result; if (!readInstruction32(code, code_len, &insn32)) { return false; } // Calling the auto-generated decoder function. - Result = decodeInstruction_4(decoderTable32, MI, insn32, address, info, 0); + Result = decodeInstruction_4(decoderTable32, MI, insn32, address, info, + 0); if (Result != MCDisassembler_Fail) { *size = 4; return true; @@ -1404,49 +1518,57 @@ static inline bool tryGetInstruction32(const uint8_t *code, size_t code_len, MCI return false; } -bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI, - uint16_t *size, uint64_t address, void *info) { - - +bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *MI, uint16_t *size, uint64_t address, + void *info) +{ if (!ud) { return false; } - struct cs_struct *cs = (struct cs_struct *) ud; + struct cs_struct *cs = (struct cs_struct *)ud; if (MI->flat_insn->detail) { memset(MI->flat_insn->detail, 0, sizeof(cs_detail)); } switch (cs->mode) { - case CS_MODE_TRICORE_110: { - if (tryGetInstruction16(code, code_len, MI, size, address, info, DecoderTablev11016) || - tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTablev11032)) { - return true; - } - break; + case CS_MODE_TRICORE_110: { + if (tryGetInstruction16(code, code_len, MI, size, address, info, + DecoderTablev11016) || + tryGetInstruction32(code, code_len, MI, size, address, info, + DecoderTablev11032)) { + return true; } - case CS_MODE_TRICORE_161: { - if (tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTablev16132)) { - return true; - } - break; + break; + } + case CS_MODE_TRICORE_161: { + if (tryGetInstruction32(code, code_len, MI, size, address, info, + DecoderTablev16132)) { + return true; } - case CS_MODE_TRICORE_162: { - if (tryGetInstruction16(code, code_len, MI, size, address, info, DecoderTablev16216) || - tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTablev16232)) { - return true; - } - break; + break; + } + case CS_MODE_TRICORE_162: { + if (tryGetInstruction16(code, code_len, MI, size, address, info, + DecoderTablev16216) || + tryGetInstruction32(code, code_len, MI, size, address, info, + DecoderTablev16232)) { + return true; } - default: - break; + break; + } + default: + break; } - return tryGetInstruction16(code, code_len, MI, size, address, info, DecoderTable16) || - tryGetInstruction32(code, code_len, MI, size, address, info, DecoderTable32); + return tryGetInstruction16(code, code_len, MI, size, address, info, + DecoderTable16) || + tryGetInstruction32(code, code_len, MI, size, address, info, + DecoderTable32); } -void TriCore_init(MCRegisterInfo *MRI) { +void TriCore_init(MCRegisterInfo *MRI) +{ /* InitMCRegisterInfo(TriCoreRegDesc, 45, RA, PC, TriCoreMCRegisterClasses, 4, @@ -1460,15 +1582,10 @@ void TriCore_init(MCRegisterInfo *MRI) { TriCoreRegEncodingTable); */ - - MCRegisterInfo_InitMCRegisterInfo(MRI, TriCoreRegDesc, ARR_SIZE(TriCoreRegDesc), - 0, 0, - TriCoreMCRegisterClasses, ARR_SIZE(TriCoreMCRegisterClasses), - 0, 0, - TriCoreRegDiffLists, - 0, - TriCoreSubRegIdxLists, 1, - 0); + MCRegisterInfo_InitMCRegisterInfo( + MRI, TriCoreRegDesc, ARR_SIZE(TriCoreRegDesc), 0, 0, + TriCoreMCRegisterClasses, ARR_SIZE(TriCoreMCRegisterClasses), 0, + 0, TriCoreRegDiffLists, 0, TriCoreSubRegIdxLists, 1, 0); } #endif diff --git a/arch/TriCore/TriCoreDisassembler.h b/arch/TriCore/TriCoreDisassembler.h index c5951bfd..30bb4d12 100644 --- a/arch/TriCore/TriCoreDisassembler.h +++ b/arch/TriCore/TriCoreDisassembler.h @@ -15,7 +15,7 @@ void TriCore_init(MCRegisterInfo *MRI); bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, - MCInst *instr, uint16_t *size, uint64_t address, void *info); + MCInst *instr, uint16_t *size, uint64_t address, + void *info); #endif - diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c index c2d3ab9c..f09f8609 100644 --- a/arch/TriCore/TriCoreInstPrinter.c +++ b/arch/TriCore/TriCoreInstPrinter.c @@ -35,7 +35,8 @@ static void printInstruction(MCInst *, uint64_t, SStream *); static void printOperand(MCInst *MI, int OpNum, SStream *O); -void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) { +void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) +{ /* if (((cs_struct *)ud)->detail != CS_OPT_ON) return; @@ -54,106 +55,113 @@ static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp); static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp); -static inline void fill_tricore_register(MCInst *MI, uint32_t reg) { - if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) return; +static inline void fill_tricore_register(MCInst *MI, uint32_t reg) +{ + if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) + return; cs_tricore *tricore = &MI->flat_insn->detail->tricore; - tricore->operands[tricore->op_count] - .type = TRICORE_OP_REG; - tricore->operands[tricore->op_count] - .reg = reg; + tricore->operands[tricore->op_count].type = TRICORE_OP_REG; + tricore->operands[tricore->op_count].reg = reg; tricore->op_count++; } -static inline void fill_tricore_imm(MCInst *MI, int32_t imm) { - if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) return; +static inline void fill_tricore_imm(MCInst *MI, int32_t imm) +{ + if (!(MI->csh->detail == CS_OPT_ON && MI->flat_insn->detail)) + return; cs_tricore *tricore = &MI->flat_insn->detail->tricore; - if (tricore->op_count >= 1 && tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG && - fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg, imm)) { return; } - tricore->operands[tricore->op_count] - .type = TRICORE_OP_IMM; - tricore->operands[tricore->op_count] - .imm = imm; + if (tricore->op_count >= 1 && + tricore->operands[tricore->op_count - 1].type == TRICORE_OP_REG && + fixup_op_mem(MI, tricore->operands[tricore->op_count - 1].reg, + imm)) { + return; + } + tricore->operands[tricore->op_count].type = TRICORE_OP_IMM; + tricore->operands[tricore->op_count].imm = imm; tricore->op_count++; } -static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp) { +static bool fixup_op_mem(MCInst *pInst, unsigned int reg, int32_t disp) +{ switch (TriCore_map_insn_id(pInst->csh, pInst->Opcode)) { - case TriCore_INS_LDMST: - case TriCore_INS_LDLCX: - case TriCore_INS_LD_A: - case TriCore_INS_LD_B: - case TriCore_INS_LD_BU: - case TriCore_INS_LD_H: - case TriCore_INS_LD_HU: - case TriCore_INS_LD_D: - case TriCore_INS_LD_DA: - case TriCore_INS_LD_W: - case TriCore_INS_LD_Q: - case TriCore_INS_STLCX: - case TriCore_INS_STUCX: - case TriCore_INS_ST_A: - case TriCore_INS_ST_B: - case TriCore_INS_ST_H: - case TriCore_INS_ST_D: - case TriCore_INS_ST_DA: - case TriCore_INS_ST_W: - case TriCore_INS_ST_Q: - case TriCore_INS_CACHEI_I: - case TriCore_INS_CACHEI_W: - case TriCore_INS_CACHEI_WI: - case TriCore_INS_CACHEA_I: - case TriCore_INS_CACHEA_W: - case TriCore_INS_CACHEA_WI: - case TriCore_INS_CMPSWAP_W: - case TriCore_INS_SWAP_A: - case TriCore_INS_SWAP_W: - case TriCore_INS_SWAPMSK_W: - case TriCore_INS_LEA: - case TriCore_INS_LHA: { - switch (MCInst_getOpcode(pInst)) { - case TriCore_LDMST_abs: - case TriCore_LDLCX_abs: - case TriCore_LD_A_abs: - case TriCore_LD_B_abs: - case TriCore_LD_BU_abs: - case TriCore_LD_H_abs: - case TriCore_LD_HU_abs: - case TriCore_LD_D_abs: - case TriCore_LD_DA_abs: - case TriCore_LD_W_abs: - case TriCore_LD_Q_abs: - case TriCore_STLCX_abs: - case TriCore_STUCX_abs: - case TriCore_ST_A_abs: - case TriCore_ST_B_abs: - case TriCore_ST_H_abs: - case TriCore_ST_D_abs: - case TriCore_ST_DA_abs: - case TriCore_ST_W_abs: - case TriCore_ST_Q_abs: - case TriCore_SWAP_A_abs: - case TriCore_SWAP_W_abs: - case TriCore_LEA_abs: - case TriCore_LHA_abs: { - return false; - } - } - cs_tricore *tc = &pInst->flat_insn->detail->tricore; - fill_mem(tc, reg, disp); - return true; + case TriCore_INS_LDMST: + case TriCore_INS_LDLCX: + case TriCore_INS_LD_A: + case TriCore_INS_LD_B: + case TriCore_INS_LD_BU: + case TriCore_INS_LD_H: + case TriCore_INS_LD_HU: + case TriCore_INS_LD_D: + case TriCore_INS_LD_DA: + case TriCore_INS_LD_W: + case TriCore_INS_LD_Q: + case TriCore_INS_STLCX: + case TriCore_INS_STUCX: + case TriCore_INS_ST_A: + case TriCore_INS_ST_B: + case TriCore_INS_ST_H: + case TriCore_INS_ST_D: + case TriCore_INS_ST_DA: + case TriCore_INS_ST_W: + case TriCore_INS_ST_Q: + case TriCore_INS_CACHEI_I: + case TriCore_INS_CACHEI_W: + case TriCore_INS_CACHEI_WI: + case TriCore_INS_CACHEA_I: + case TriCore_INS_CACHEA_W: + case TriCore_INS_CACHEA_WI: + case TriCore_INS_CMPSWAP_W: + case TriCore_INS_SWAP_A: + case TriCore_INS_SWAP_W: + case TriCore_INS_SWAPMSK_W: + case TriCore_INS_LEA: + case TriCore_INS_LHA: { + switch (MCInst_getOpcode(pInst)) { + case TriCore_LDMST_abs: + case TriCore_LDLCX_abs: + case TriCore_LD_A_abs: + case TriCore_LD_B_abs: + case TriCore_LD_BU_abs: + case TriCore_LD_H_abs: + case TriCore_LD_HU_abs: + case TriCore_LD_D_abs: + case TriCore_LD_DA_abs: + case TriCore_LD_W_abs: + case TriCore_LD_Q_abs: + case TriCore_STLCX_abs: + case TriCore_STUCX_abs: + case TriCore_ST_A_abs: + case TriCore_ST_B_abs: + case TriCore_ST_H_abs: + case TriCore_ST_D_abs: + case TriCore_ST_DA_abs: + case TriCore_ST_W_abs: + case TriCore_ST_Q_abs: + case TriCore_SWAP_A_abs: + case TriCore_SWAP_W_abs: + case TriCore_LEA_abs: + case TriCore_LHA_abs: { + return false; } + } + cs_tricore *tc = &pInst->flat_insn->detail->tricore; + fill_mem(tc, reg, disp); + return true; + } } return false; } -static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp) { +static inline void fill_mem(cs_tricore *tc, uint8_t base, int32_t disp) +{ cs_tricore_op *op = &tc->operands[tc->op_count - 1]; op->type = TRICORE_OP_MEM; op->mem.base = base; op->mem.disp = disp; } -static void printOperand(MCInst *MI, int OpNum, SStream *O) { +static void printOperand(MCInst *MI, int OpNum, SStream *O) +{ MCOperand *Op; if (OpNum >= MI->size) return; @@ -179,34 +187,38 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O) { SStream_concat(O, "-%" PRIu64, -Imm); } - fill_tricore_imm(MI, (int32_t) Imm); + fill_tricore_imm(MI, (int32_t)Imm); } } -static inline unsigned int get_msb(unsigned int value) { +static inline unsigned int get_msb(unsigned int value) +{ unsigned int msb = 0; while (value > 0) { value >>= 1; // Shift bits to the right - msb++; // Increment the position of the MSB + msb++; // Increment the position of the MSB } return msb; } -static inline int32_t sign_ext_n(int32_t imm, unsigned n) { +static inline int32_t sign_ext_n(int32_t imm, unsigned n) +{ n = get_msb(imm) > n ? get_msb(imm) : n; int32_t mask = 1 << (n - 1); int32_t sign_extended = (imm ^ mask) - mask; return sign_extended; } -static inline void SS_print_hex(SStream *O, int32_t imm) { +static inline void SS_print_hex(SStream *O, int32_t imm) +{ if (imm > HEX_THRESHOLD) SStream_concat(O, "0x%x", imm); else SStream_concat(O, "%u", imm); } -static inline void SS_print_sign_hex(SStream *O, int32_t imm) { +static inline void SS_print_sign_hex(SStream *O, int32_t imm) +{ if (imm >= 0) { SS_print_hex(O, imm); } else { @@ -217,10 +229,11 @@ static inline void SS_print_sign_hex(SStream *O, int32_t imm) { } } -static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) { +static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - int32_t imm = (int32_t) MCOperand_getImm(MO); + int32_t imm = (int32_t)MCOperand_getImm(MO); imm = sign_ext_n(imm, n); SS_print_sign_hex(O, imm); fill_tricore_imm(MI, imm); @@ -228,30 +241,32 @@ static void print_sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) { printOperand(MI, OpNum, O); } -static void off4_fixup(MCInst *MI, uint64_t *off4) { +static void off4_fixup(MCInst *MI, uint64_t *off4) +{ switch (MCInst_getOpcode(MI)) { - case TriCore_LD_A_slro: - case TriCore_LD_A_sro: - case TriCore_LD_W_slro: - case TriCore_LD_W_sro: - case TriCore_ST_A_sro: - case TriCore_ST_A_ssro: - case TriCore_ST_W_sro: - case TriCore_ST_W_ssro: { - *off4 *= 4; - break; - } - case TriCore_LD_H_sro: - case TriCore_LD_H_slro: - case TriCore_ST_H_sro: - case TriCore_ST_H_ssro: { - *off4 *= 2; - break; - } + case TriCore_LD_A_slro: + case TriCore_LD_A_sro: + case TriCore_LD_W_slro: + case TriCore_LD_W_sro: + case TriCore_ST_A_sro: + case TriCore_ST_A_ssro: + case TriCore_ST_W_sro: + case TriCore_ST_W_ssro: { + *off4 *= 4; + break; + } + case TriCore_LD_H_sro: + case TriCore_LD_H_slro: + case TriCore_ST_H_sro: + case TriCore_ST_H_ssro: { + *off4 *= 2; + break; + } } } -static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) { +static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { uint64_t imm = MCOperand_getImm(MO); @@ -278,47 +293,54 @@ static void print_zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) { printOperand(MI, OpNum, O); } -static void printOff18Imm(MCInst *MI, int OpNum, SStream *O) { +static void printOff18Imm(MCInst *MI, int OpNum, SStream *O) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - uint32_t imm = (uint32_t) MCOperand_getImm(MO); + uint32_t imm = (uint32_t)MCOperand_getImm(MO); imm = ((imm & 0x3C000) << 14) | (imm & 0x3fff); SStream_concat(O, "0x%x", imm); - fill_tricore_imm(MI, (int32_t) imm); + fill_tricore_imm(MI, (int32_t)imm); } else printOperand(MI, OpNum, O); } -static inline void fixup_tricore_disp(MCInst *MI, int OpNum, int32_t disp) { - if (MI->csh->detail != CS_OPT_ON) return; - if (OpNum <= 0) return; +static inline void fixup_tricore_disp(MCInst *MI, int OpNum, int32_t disp) +{ + if (MI->csh->detail != CS_OPT_ON) + return; + if (OpNum <= 0) + return; cs_tricore *tricore = &MI->flat_insn->detail->tricore; - if (tricore->operands[tricore->op_count - 1].type != TRICORE_OP_REG) return; + if (tricore->operands[tricore->op_count - 1].type != TRICORE_OP_REG) + return; fill_mem(tricore, tricore->operands[tricore->op_count - 1].reg, disp); } -static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) { +static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - int32_t disp = (int32_t) MCOperand_getImm(MO); + int32_t disp = (int32_t)MCOperand_getImm(MO); switch (MCInst_getOpcode(MI)) { - case TriCore_CALL_b: - case TriCore_FCALL_b: { - disp = (int32_t) MI->address + sign_ext_n(disp * 2, 24); - break; - } - case TriCore_CALLA_b: - case TriCore_FCALLA_b: - case TriCore_JA_b: - case TriCore_JLA_b: - // = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0}; - disp = ((disp & 0xf00000) << 28) | ((disp & 0xfffff) << 1); - break; - case TriCore_J_b: - case TriCore_JL_b: - disp = (int32_t) MI->address + sign_ext_n(disp, 24) * 2; - break; + case TriCore_CALL_b: + case TriCore_FCALL_b: { + disp = (int32_t)MI->address + sign_ext_n(disp * 2, 24); + break; + } + case TriCore_CALLA_b: + case TriCore_FCALLA_b: + case TriCore_JA_b: + case TriCore_JLA_b: + // = {disp24[23:20], 7’b0000000, disp24[19:0], 1’b0}; + disp = ((disp & 0xf00000) << 28) | + ((disp & 0xfffff) << 1); + break; + case TriCore_J_b: + case TriCore_JL_b: + disp = (int32_t)MI->address + sign_ext_n(disp, 24) * 2; + break; } SS_print_sign_hex(O, disp); @@ -327,42 +349,43 @@ static void printDisp24Imm(MCInst *MI, int OpNum, SStream *O) { printOperand(MI, OpNum, O); } -static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) { +static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - int32_t disp = (int32_t) MCOperand_getImm(MO); + int32_t disp = (int32_t)MCOperand_getImm(MO); switch (MCInst_getOpcode(MI)) { - case TriCore_JEQ_brc: - case TriCore_JEQ_brr: - case TriCore_JEQ_A_brr: - case TriCore_JGE_brc: - case TriCore_JGE_brr: - case TriCore_JGE_U_brc: - case TriCore_JGE_U_brr: - case TriCore_JLT_brc: - case TriCore_JLT_brr: - case TriCore_JLT_U_brc: - case TriCore_JLT_U_brr: - case TriCore_JNE_brc: - case TriCore_JNE_brr: - case TriCore_JNE_A_brr: - case TriCore_JNED_brc: - case TriCore_JNED_brr: - case TriCore_JNEI_brc: - case TriCore_JNEI_brr: - case TriCore_JNZ_A_brr: - case TriCore_JNZ_T_brn: - case TriCore_JZ_A_brr: - case TriCore_JZ_T_brn: - disp = (int32_t) MI->address + sign_ext_n(disp, 15) * 2; - break; - case TriCore_LOOP_brr: - case TriCore_LOOPU_brr: - disp = (int32_t) MI->address + sign_ext_n(disp * 2, 15); - break; - default: - // handle other cases, if any - break; + case TriCore_JEQ_brc: + case TriCore_JEQ_brr: + case TriCore_JEQ_A_brr: + case TriCore_JGE_brc: + case TriCore_JGE_brr: + case TriCore_JGE_U_brc: + case TriCore_JGE_U_brr: + case TriCore_JLT_brc: + case TriCore_JLT_brr: + case TriCore_JLT_U_brc: + case TriCore_JLT_U_brr: + case TriCore_JNE_brc: + case TriCore_JNE_brr: + case TriCore_JNE_A_brr: + case TriCore_JNED_brc: + case TriCore_JNED_brr: + case TriCore_JNEI_brc: + case TriCore_JNEI_brr: + case TriCore_JNZ_A_brr: + case TriCore_JNZ_T_brn: + case TriCore_JZ_A_brr: + case TriCore_JZ_T_brn: + disp = (int32_t)MI->address + sign_ext_n(disp, 15) * 2; + break; + case TriCore_LOOP_brr: + case TriCore_LOOPU_brr: + disp = (int32_t)MI->address + sign_ext_n(disp * 2, 15); + break; + default: + // handle other cases, if any + break; } SS_print_sign_hex(O, disp); @@ -371,22 +394,23 @@ static void printDisp15Imm(MCInst *MI, int OpNum, SStream *O) { printOperand(MI, OpNum, O); } -static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) { +static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - int32_t disp = (int32_t) MCOperand_getImm(MO); + int32_t disp = (int32_t)MCOperand_getImm(MO); switch (MCInst_getOpcode(MI)) { - case TriCore_CALL_sb: - disp = (int32_t) MI->address + sign_ext_n(2 * disp, 8); - break; - case TriCore_J_sb: - case TriCore_JNZ_sb: - case TriCore_JZ_sb: - disp = (int32_t) MI->address + sign_ext_n(disp, 8) * 2; - break; - default: - // handle other cases, if any - break; + case TriCore_CALL_sb: + disp = (int32_t)MI->address + sign_ext_n(2 * disp, 8); + break; + case TriCore_J_sb: + case TriCore_JNZ_sb: + case TriCore_JZ_sb: + disp = (int32_t)MI->address + sign_ext_n(disp, 8) * 2; + break; + default: + // handle other cases, if any + break; } SS_print_sign_hex(O, disp); @@ -395,40 +419,43 @@ static void printDisp8Imm(MCInst *MI, int OpNum, SStream *O) { printOperand(MI, OpNum, O); } -static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) { +static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { - int32_t disp = (int32_t) MCOperand_getImm(MO); + int32_t disp = (int32_t)MCOperand_getImm(MO); switch (MCInst_getOpcode(MI)) { - case TriCore_JEQ_sbc1: - case TriCore_JEQ_sbr1: - case TriCore_JGEZ_sbr: - case TriCore_JGTZ_sbr: - case TriCore_JLEZ_sbr: - case TriCore_JLTZ_sbr: - case TriCore_JNE_sbc1: - case TriCore_JNE_sbr1: - case TriCore_JNZ_sbr: - case TriCore_JNZ_A_sbr: - case TriCore_JNZ_T_sbrn: - case TriCore_JZ_sbr: - case TriCore_JZ_A_sbr: - case TriCore_JZ_T_sbrn: - disp = (int32_t) MI->address + disp * 2; - break; - case TriCore_JEQ_sbc2: - case TriCore_JEQ_sbr2: - case TriCore_JNE_sbc2: - case TriCore_JNE_sbr2: - disp = (int32_t) MI->address + (disp + 16) * 2; - break; - case TriCore_LOOP_sbr: - // {27b’111111111111111111111111111, disp4, 0}; - disp = (int32_t) MI->address + ((0b111111111111111111111111111 << 5) | (disp << 1)); - break; - default: - // handle other cases, if any - break; + case TriCore_JEQ_sbc1: + case TriCore_JEQ_sbr1: + case TriCore_JGEZ_sbr: + case TriCore_JGTZ_sbr: + case TriCore_JLEZ_sbr: + case TriCore_JLTZ_sbr: + case TriCore_JNE_sbc1: + case TriCore_JNE_sbr1: + case TriCore_JNZ_sbr: + case TriCore_JNZ_A_sbr: + case TriCore_JNZ_T_sbrn: + case TriCore_JZ_sbr: + case TriCore_JZ_A_sbr: + case TriCore_JZ_T_sbrn: + disp = (int32_t)MI->address + disp * 2; + break; + case TriCore_JEQ_sbc2: + case TriCore_JEQ_sbr2: + case TriCore_JNE_sbc2: + case TriCore_JNE_sbr2: + disp = (int32_t)MI->address + (disp + 16) * 2; + break; + case TriCore_LOOP_sbr: + // {27b’111111111111111111111111111, disp4, 0}; + disp = (int32_t)MI->address + + ((0b111111111111111111111111111 << 5) | + (disp << 1)); + break; + default: + // handle other cases, if any + break; } SS_print_sign_hex(O, disp); @@ -437,42 +464,45 @@ static void printDisp4Imm(MCInst *MI, int OpNum, SStream *O) { printOperand(MI, OpNum, O); } -#define printSExtImm_(n) \ - static void printSExtImm_ ##n(MCInst *MI, int OpNum, SStream *O) \ - { \ - print_sign_ext(MI, OpNum, O, n); \ - } - +#define printSExtImm_(n) \ + static void printSExtImm_##n(MCInst *MI, int OpNum, SStream *O) \ + { \ + print_sign_ext(MI, OpNum, O, n); \ + } printSExtImm_(16) -printSExtImm_(10) + printSExtImm_(10) -printSExtImm_(9) + printSExtImm_(9) -printSExtImm_(4) + printSExtImm_(4) -#define printZExtImm_(n) \ - static void printZExtImm_ ##n(MCInst *MI, int OpNum, SStream *O) \ - { \ - print_zero_ext(MI, OpNum, O, n); \ - } +#define printZExtImm_(n) \ + static void printZExtImm_##n(MCInst *MI, int OpNum, SStream *O) \ + { \ + print_zero_ext(MI, OpNum, O, n); \ + } -printZExtImm_(16) + printZExtImm_(16) -printZExtImm_(9) + printZExtImm_(9) -printZExtImm_(8) + printZExtImm_(8) -printZExtImm_(4) + printZExtImm_(4) -printZExtImm_(2) + printZExtImm_(2) -static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) { + static void printOExtImm_4( + MCInst *MI, + int OpNum, + SStream *O) +{ MCOperand *MO = MCInst_getOperand(MI, OpNum); if (MCOperand_isImm(MO)) { uint32_t imm = MCOperand_getImm(MO); -// {27b’111111111111111111111111111, disp4, 0}; + // {27b’111111111111111111111111111, disp4, 0}; imm = 0b11111111111111111111111111100000 | (imm << 1); SS_print_sign_hex(O, imm); @@ -481,14 +511,14 @@ static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) { printOperand(MI, OpNum, O); } - /// Returned by getMnemonic() of the AsmPrinters. typedef struct { const char *first; // Menmonic - uint64_t second; // Bits + uint64_t second; // Bits } MnemonicBitsInfo; -void set_mem_access(MCInst *MI, unsigned int access) { +void set_mem_access(MCInst *MI, unsigned int access) +{ // TODO: TriCore } @@ -496,7 +526,8 @@ void set_mem_access(MCInst *MI, unsigned int access) { #include "TriCoreGenAsmWriter.inc" -const char *TriCore_getRegisterName(csh handle, unsigned int id) { +const char *TriCore_getRegisterName(csh handle, unsigned int id) +{ #ifndef CAPSTONE_DIET return getRegisterName(id); #else @@ -504,7 +535,8 @@ const char *TriCore_getRegisterName(csh handle, unsigned int id) { #endif } -void TriCore_printInst(MCInst *MI, SStream *O, void *Info) { +void TriCore_printInst(MCInst *MI, SStream *O, void *Info) +{ printInstruction(MI, MI->address, O); } diff --git a/arch/TriCore/TriCoreMapping.c b/arch/TriCore/TriCoreMapping.c index 4abecc65..99cfb89c 100644 --- a/arch/TriCore/TriCoreMapping.c +++ b/arch/TriCore/TriCoreMapping.c @@ -15,23 +15,25 @@ #include "TriCoreGenInstrInfo.inc" static insn_map insns[] = { - // dummy item - {0, - 0, + // dummy item + { 0, + 0, #ifndef CAPSTONE_DIET - {0}, - {0}, - {0}, - 0, - 0 + { 0 }, + { 0 }, + { 0 }, + 0, + 0 #endif - }, + }, #include "TriCoreGenCSMappingInsn.inc" }; -unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id) { - unsigned short i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); +unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id) +{ + unsigned short i = + insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); if (i != 0) { return insns[i].mapid; } @@ -39,7 +41,8 @@ unsigned int TriCore_map_insn_id(cs_struct *h, unsigned int id) { } // given internal insn id, return public instruction info -void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { +void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) +{ unsigned short i; i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache); @@ -51,19 +54,23 @@ void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { memcpy(insn->detail->regs_read, insns[i].regs_use, sizeof(insns[i].regs_use)); insn->detail->regs_read_count = - (uint8_t) count_positive(insns[i].regs_use); + (uint8_t)count_positive(insns[i].regs_use); memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod)); insn->detail->regs_write_count = - (uint8_t) count_positive(insns[i].regs_mod); + (uint8_t)count_positive(insns[i].regs_mod); - memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups)); - insn->detail->groups_count = (uint8_t) count_positive8(insns[i].groups); + memcpy(insn->detail->groups, insns[i].groups, + sizeof(insns[i].groups)); + insn->detail->groups_count = + (uint8_t)count_positive8(insns[i].groups); if (insns[i].branch || insns[i].indirect_branch) { // this insn also belongs to JUMP group. add JUMP group - insn->detail->groups[insn->detail->groups_count] = TriCore_GRP_JUMP; + insn->detail + ->groups[insn->detail->groups_count] = + TriCore_GRP_JUMP; insn->detail->groups_count++; } #endif @@ -74,16 +81,17 @@ void TriCore_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id) { #ifndef CAPSTONE_DIET static const char *insn_names[] = { - NULL, + NULL, #include "TriCoreGenCSMappingInsnName.inc" }; // special alias insn -static name_map alias_insn_names[] = {{0, NULL}}; +static name_map alias_insn_names[] = { { 0, NULL } }; #endif -const char *TriCore_insn_name(csh handle, unsigned int id) { +const char *TriCore_insn_name(csh handle, unsigned int id) +{ #ifndef CAPSTONE_DIET unsigned int i; @@ -104,13 +112,14 @@ const char *TriCore_insn_name(csh handle, unsigned int id) { #ifndef CAPSTONE_DIET static name_map group_name_maps[] = { - {TriCore_GRP_INVALID, NULL}, - {TriCore_GRP_CALL, "call"}, - {TriCore_GRP_JUMP, "jump"}, + { TriCore_GRP_INVALID, NULL }, + { TriCore_GRP_CALL, "call" }, + { TriCore_GRP_JUMP, "jump" }, }; #endif -const char *TriCore_group_name(csh handle, unsigned int id) { +const char *TriCore_group_name(csh handle, unsigned int id) +{ #ifndef CAPSTONE_DIET if (id >= TriCore_GRP_ENDING) return NULL; diff --git a/arch/TriCore/TriCoreMapping.h b/arch/TriCore/TriCoreMapping.h index 698f4160..1eac1d35 100644 --- a/arch/TriCore/TriCoreMapping.h +++ b/arch/TriCore/TriCoreMapping.h @@ -16,4 +16,3 @@ const char *TriCore_insn_name(csh handle, unsigned int id); const char *TriCore_group_name(csh handle, unsigned int id); #endif - diff --git a/arch/TriCore/TriCoreModule.c b/arch/TriCore/TriCoreModule.c index b64693f7..a0aca3b4 100644 --- a/arch/TriCore/TriCoreModule.c +++ b/arch/TriCore/TriCoreModule.c @@ -32,7 +32,7 @@ cs_err TRICORE_global_init(cs_struct *ud) cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value) { if (type == CS_OPT_SYNTAX) - handle->syntax = (int) value; + handle->syntax = (int)value; return CS_ERR_OK; } diff --git a/cstool/cstool_tricore.c b/cstool/cstool_tricore.c index 282fa063..54af15ff 100644 --- a/cstool/cstool_tricore.c +++ b/cstool/cstool_tricore.c @@ -5,61 +5,67 @@ void print_insn_detail_tricore(csh handle, cs_insn *ins) { - cs_tricore *tricore; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; + cs_tricore *tricore; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; - // detail can be NULL on "data" instruction if SKIPDATA option is turned ON - if (ins->detail == NULL) - return; + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; - tricore = &(ins->detail->tricore); + tricore = &(ins->detail->tricore); - if (tricore->op_count) - printf("\top_count: %u\n", tricore->op_count); + if (tricore->op_count) + printf("\top_count: %u\n", tricore->op_count); - for (i = 0; i < tricore->op_count; i++) { - cs_tricore_op *op = &(tricore->operands[i]); - switch ((int)op->type) { - default: - break; - case TRICORE_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case TRICORE_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); - break; - case TRICORE_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != TriCore_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, - cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); - break; - } + for (i = 0; i < tricore->op_count; i++) { + cs_tricore_op *op = &(tricore->operands[i]); + switch ((int)op->type) { + default: + break; + case TRICORE_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case TRICORE_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, + op->imm); + break; + case TRICORE_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != TriCore_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, + op->mem.disp); + break; + } - // Print out all registers accessed by this instruction (either implicit or - // explicit) - if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, regs_write, - ®s_write_count)) { - if (regs_read_count) { - printf("\tRegisters read:"); - for (i = 0; i < regs_read_count; i++) { - printf(" %s", cs_reg_name(handle, regs_read[i])); + // Print out all registers accessed by this instruction (either implicit or + // explicit) + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for (i = 0; i < regs_read_count; i++) { + printf(" %s", + cs_reg_name(handle, + regs_read[i])); + } + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for (i = 0; i < regs_write_count; i++) { + printf(" %s", + cs_reg_name(handle, + regs_write[i])); + } + printf("\n"); + } + } } - printf("\n"); - } - - if (regs_write_count) { - printf("\tRegisters modified:"); - for (i = 0; i < regs_write_count; i++) { - printf(" %s", cs_reg_name(handle, regs_write[i])); - } - printf("\n"); - } - } - } } \ No newline at end of file diff --git a/include/capstone/tricore.h b/include/capstone/tricore.h index 4de8ca87..df99f647 100644 --- a/include/capstone/tricore.h +++ b/include/capstone/tricore.h @@ -15,7 +15,7 @@ extern "C" { #include "platform.h" #ifdef _MSC_VER -#pragma warning(disable:4201) +#pragma warning(disable : 4201) #endif //> Operand type for instruction's operands @@ -29,17 +29,17 @@ typedef enum tricore_op_type { // Instruction's operand referring to memory // This is associated with TRICORE_OP_MEM operand type above typedef struct tricore_op_mem { - uint8_t base; // base register - int32_t disp; // displacement/offset value + uint8_t base; // base register + int32_t disp; // displacement/offset value } tricore_op_mem; // Instruction operand typedef struct cs_tricore_op { - tricore_op_type type; // operand type + tricore_op_type type; // operand type union { - unsigned int reg; // register value for REG operand - int32_t imm; // immediate value for IMM operand - tricore_op_mem mem; // base/disp value for MEM operand + unsigned int reg; // register value for REG operand + int32_t imm; // immediate value for IMM operand + tricore_op_mem mem; // base/disp value for MEM operand }; } cs_tricore_op; @@ -60,22 +60,22 @@ typedef enum tricore_reg { typedef enum tricore_insn { TriCore_INS_INVALID = 0, #include "./inc/TriCoreGenCSInsnEnum.inc" - TriCore_INS_ENDING, // <-- mark the end of the list of instructions + TriCore_INS_ENDING, // <-- mark the end of the list of instructions } tricore_insn; //> Group of TriCore instructions typedef enum tricore_insn_group { - TriCore_GRP_INVALID, ///< = CS_GRP_INVALID + TriCore_GRP_INVALID, ///< = CS_GRP_INVALID //> Generic groups - TriCore_GRP_CALL, ///< = CS_GRP_CALL - TriCore_GRP_JUMP, ///< = CS_GRP_JUMP - TriCore_GRP_ENDING, ///< = mark the end of the list of groups + TriCore_GRP_CALL, ///< = CS_GRP_CALL + TriCore_GRP_JUMP, ///< = CS_GRP_JUMP + TriCore_GRP_ENDING, ///< = mark the end of the list of groups } tricore_insn_group; typedef enum tricore_feature_t { TriCore_FEATURE_INVALID = 0, #include "./inc/TriCoreGenCSFeatureEnum.inc" - TriCore_FEATURE_ENDING, // <-- mark the end of the list of features + TriCore_FEATURE_ENDING, // <-- mark the end of the list of features } tricore_feature; #ifdef __cplusplus diff --git a/suite/cstest/src/tricore_detail.c b/suite/cstest/src/tricore_detail.c index 4605c16e..752f224a 100644 --- a/suite/cstest/src/tricore_detail.c +++ b/suite/cstest/src/tricore_detail.c @@ -6,69 +6,76 @@ char *get_detail_tricore(csh *p_handle, cs_mode mode, cs_insn *ins) { - cs_tricore *tricore; - int i; - cs_regs regs_read, regs_write; - uint8_t regs_read_count, regs_write_count; + cs_tricore *tricore; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; - char *result; - result = (char *)malloc(sizeof(char)); - result[0] = '\0'; + char *result; + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; - if (ins->detail == NULL) - return result; + if (ins->detail == NULL) + return result; - csh handle = *p_handle; + csh handle = *p_handle; - tricore = &(ins->detail->tricore); + tricore = &(ins->detail->tricore); - if (tricore->op_count) - add_str(&result, "\top_count: %u\n", tricore->op_count); + if (tricore->op_count) + add_str(&result, "\top_count: %u\n", tricore->op_count); - for (i = 0; i < tricore->op_count; i++) { - cs_tricore_op *op = &(tricore->operands[i]); - switch ((int)op->type) { - default: - break; - case TRICORE_OP_REG: - add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, - cs_reg_name(handle, op->reg)); - break; - case TRICORE_OP_IMM: - add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); - break; - case TRICORE_OP_MEM: - add_str(&result, "\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != TriCore_REG_INVALID) - add_str(&result, "\t\t\toperands[%u].mem.base: REG = %s\n", i, - cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - add_str(&result, "\t\t\toperands[%u].mem.disp: 0x%x\n", i, - op->mem.disp); - break; - } + for (i = 0; i < tricore->op_count; i++) { + cs_tricore_op *op = &(tricore->operands[i]); + switch ((int)op->type) { + default: + break; + case TRICORE_OP_REG: + add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case TRICORE_OP_IMM: + add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", + i, op->imm); + break; + case TRICORE_OP_MEM: + add_str(&result, "\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != TriCore_REG_INVALID) + add_str(&result, + "\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.disp != 0) + add_str(&result, + "\t\t\toperands[%u].mem.disp: 0x%x\n", + i, op->mem.disp); + break; + } - // Print out all registers accessed by this instruction (either implicit or - // explicit) - if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, regs_write, - ®s_write_count)) { - if (regs_read_count) { - add_str(&result, "\tRegisters read:"); - for (i = 0; i < regs_read_count; i++) { - add_str(&result, " %s", cs_reg_name(handle, regs_read[i])); + // Print out all registers accessed by this instruction (either implicit or + // explicit) + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + add_str(&result, "\tRegisters read:"); + for (i = 0; i < regs_read_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_read[i])); + } + add_str(&result, "\n"); + } + + if (regs_write_count) { + add_str(&result, "\tRegisters modified:"); + for (i = 0; i < regs_write_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_write[i])); + } + add_str(&result, "\n"); + } + } } - add_str(&result, "\n"); - } - if (regs_write_count) { - add_str(&result, "\tRegisters modified:"); - for (i = 0; i < regs_write_count; i++) { - add_str(&result, " %s", cs_reg_name(handle, regs_write[i])); - } - add_str(&result, "\n"); - } - } - } - - return result; + return result; } diff --git a/tests/test_tricore.c b/tests/test_tricore.c index c8f6e07e..7aa29200 100644 --- a/tests/test_tricore.c +++ b/tests/test_tricore.c @@ -43,24 +43,27 @@ static void print_insn_detail(cs_insn *ins) for (i = 0; i < tricore->op_count; i++) { cs_tricore_op *op = &(tricore->operands[i]); - switch((int)op->type) { - default: - break; - case TRICORE_OP_REG: - printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); - break; - case TRICORE_OP_IMM: - printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm); - break; - case TRICORE_OP_MEM: - printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.base != TriCore_REG_INVALID) - printf("\t\t\toperands[%u].mem.base: REG = %s\n", - i, cs_reg_name(handle, op->mem.base)); - if (op->mem.disp != 0) - printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp); + switch ((int)op->type) { + default: + break; + case TRICORE_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case TRICORE_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%x\n", i, + op->imm); + break; + case TRICORE_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.base != TriCore_REG_INVALID) + printf("\t\t\toperands[%u].mem.base: REG = %s\n", + i, cs_reg_name(handle, op->mem.base)); + if (op->mem.disp != 0) + printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, + op->mem.disp); - break; + break; } } @@ -70,13 +73,14 @@ static void print_insn_detail(cs_insn *ins) static void test() { //#define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10" -#define TRICORE_CODE "\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01" +#define TRICORE_CODE \ + "\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01" struct platform platforms[] = { { CS_ARCH_TRICORE, CS_MODE_TRICORE_162, - (unsigned char*)TRICORE_CODE, + (unsigned char *)TRICORE_CODE, sizeof(TRICORE_CODE) - 1, "TriCore", }, @@ -87,36 +91,44 @@ static void test() int i; size_t count; - for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) { - cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle); + for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { + cs_err err = + cs_open(platforms[i].arch, platforms[i].mode, &handle); if (err) { - printf("Failed on cs_open() with error returned: %u\n", err); + printf("Failed on cs_open() with error returned: %u\n", + err); continue; } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); - count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn); + count = cs_disasm(handle, platforms[i].code, platforms[i].size, + address, 0, &insn); if (count) { size_t j; printf("****************\n"); printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); + print_string_hex("Code:", platforms[i].code, + platforms[i].size); printf("Disasm:\n"); for (j = 0; j < count; j++) { - printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str); + printf("0x%" PRIx64 ":\t%s\t%s\n", + insn[j].address, insn[j].mnemonic, + insn[j].op_str); print_insn_detail(&insn[j]); } - printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size); + printf("0x%" PRIx64 ":\n", + insn[j - 1].address + insn[j - 1].size); // free memory allocated by cs_disasm() cs_free(insn, count); } else { printf("****************\n"); printf("Platform: %s\n", platforms[i].comment); - print_string_hex("Code:", platforms[i].code, platforms[i].size); + print_string_hex("Code:", platforms[i].code, + platforms[i].size); printf("ERROR: Failed to disasm given code!\n"); }