Merge branch 'master' of https://github.com/aquynh/capstone
This commit is contained in:
commit
31a2855012
2
Makefile
2
Makefile
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@ -397,7 +397,7 @@ uninstall:
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clean:
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rm -f $(LIBOBJ)
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rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).*
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rm -f $(BLDIR)/lib$(LIBNAME).* $(BLDIR)/$(LIBNAME).pc
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rm -f $(PKGCFGF)
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$(MAKE) -C cstool clean
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@ -588,6 +588,11 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
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MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_REG;
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MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].reg = MCOperand_getReg(MCInst_getOperand(MI, 0));
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MI->flat_insn->detail->arm.op_count++;
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// this instruction implicitly read/write SP register
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MI->flat_insn->detail->regs_read[MI->flat_insn->detail->regs_read_count] = ARM_REG_SP;
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MI->flat_insn->detail->regs_read_count++;
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MI->flat_insn->detail->regs_write[MI->flat_insn->detail->regs_write_count] = ARM_REG_SP;
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MI->flat_insn->detail->regs_write_count++;
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}
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SStream_concat0(O, "}");
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return;
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@ -676,7 +676,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
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MCOperand *DispSpec = MCInst_getOperand(MI, Op + X86_AddrDisp);
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MCOperand *SegReg = MCInst_getOperand(MI, Op + X86_AddrSegmentReg);
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uint64_t ScaleVal;
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int reg;
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int segreg;
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if (MI->csh->detail) {
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MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM;
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@ -689,11 +689,11 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
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}
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// If this has a segment register, print it.
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reg = MCOperand_getReg(SegReg);
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if (reg) {
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segreg = MCOperand_getReg(SegReg);
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if (segreg) {
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_printOperand(MI, Op + X86_AddrSegmentReg, O);
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if (MI->csh->detail) {
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MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = reg;
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MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.segment = segreg;
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}
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SStream_concat0(O, ":");
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@ -728,7 +728,8 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
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}
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}
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} else {
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//SStream_concat0(O, "0");
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if (segreg)
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SStream_concat0(O, "0");
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}
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}
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@ -835,6 +835,12 @@ bool X86_getInstruction(csh ud, const uint8_t *code, size_t code_len,
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result = (!translateInstruction(instr, &insn)) ? true : false;
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if (result) {
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// quick fix for #904. TODO: fix this properly in the next update
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if (handle->mode & CS_MODE_64 &&
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(instr->Opcode == X86_LES16rm || instr->Opcode == X86_LES32rm))
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// LES is invalid in x64
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return false;
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instr->imm_size = insn.immSize;
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if (handle->detail) {
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update_pub_insn(instr->flat_insn, &insn, instr->x86_prefix);
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@ -2133,6 +2133,9 @@ static bool checkPrefix(struct InternalInstruction *insn)
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// invalid LOCK
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return true;
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// nop dword [rax]
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case X86_NOOPL:
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// DEC
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case X86_DEC16m:
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case X86_DEC32m:
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