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Add tricore tc1.8 instructions (#2595) 

* Add tricore tc1.8 instructions:
add.df
sub.df
madd.df
msub.df
mul.df
div.df
cmp.df
max.df
min.df
min.f
max.f
dftoi
dftoiz
dftoin
ftoin
dftou
dftouz
dftol
dftoul
dftoulz
abs.f
abs.df
dftolz
neg.df
neg.f
qseed.df
itodf
utodf
ltodf
ultodf
dftof
ftodf

* Fix python binding

* Fix python binding

* add tricore tc1.8 instructions
div64
div64.u
rem64
rem64.u

* add tricore tc1.8 instruction to tests/details

* Fix review
This commit is contained in:
Changqing Jing 2025-01-28 20:50:43 +08:00 committed by GitHub
parent 5f290cad1f
commit 3c4d7fc8d6
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
32 changed files with 10207 additions and 8151 deletions
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10
arch/TriCore/TriCoreDisassembler.c
View File

@ -201,6 +201,9 @@ bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature)
case CS_MODE_TRICORE_162: {
return feature == TriCore_HasV162Ops;
}
case CS_MODE_TRICORE_180: {
return feature == TriCore_HasV180Ops;
}
default:
return false;
}
@ -1723,6 +1726,13 @@ static bool getInstruction(csh ud, const uint8_t *code, size_t code_len,
}
break;
}
case CS_MODE_TRICORE_180: {
if (decodeInstruction2_or_4(code, code_len, MI, size, address,
NULL, DecoderTablev16232)) {
return true;
}
break;
}
default:
break;
}

2956
arch/TriCore/TriCoreGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

3
arch/TriCore/TriCoreGenCSFeatureName.inc
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@ -18,15 +18,18 @@
{ TRICORE_FEATURE_HASV160, "HasV160" },
{ TRICORE_FEATURE_HASV161, "HasV161" },
{ TRICORE_FEATURE_HASV162, "HasV162" },
{ TRICORE_FEATURE_HASV180, "HasV180" },
{ TRICORE_FEATURE_HASV120_UP, "HasV120_UP" },
{ TRICORE_FEATURE_HASV130_UP, "HasV130_UP" },
{ TRICORE_FEATURE_HASV131_UP, "HasV131_UP" },
{ TRICORE_FEATURE_HASV160_UP, "HasV160_UP" },
{ TRICORE_FEATURE_HASV161_UP, "HasV161_UP" },
{ TRICORE_FEATURE_HASV162_UP, "HasV162_UP" },
{ TRICORE_FEATURE_HASV180_UP, "HasV180_UP" },
{ TRICORE_FEATURE_HASV120_DN, "HasV120_DN" },
{ TRICORE_FEATURE_HASV130_DN, "HasV130_DN" },
{ TRICORE_FEATURE_HASV131_DN, "HasV131_DN" },
{ TRICORE_FEATURE_HASV160_DN, "HasV160_DN" },
{ TRICORE_FEATURE_HASV161_DN, "HasV161_DN" },
{ TRICORE_FEATURE_HASV162_DN, "HasV162_DN" },
{ TRICORE_FEATURE_HASV180_DN, "HasV180_DN" },

2312
arch/TriCore/TriCoreGenCSMappingInsn.inc
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File diff suppressed because it is too large Load Diff

36
arch/TriCore/TriCoreGenCSMappingInsnName.inc
View File

@ -22,6 +22,8 @@
"abss.h", // TRICORE_INS_ABSS_H
"abss", // TRICORE_INS_ABSS
"abs.b", // TRICORE_INS_ABS_B
"abs.df", // TRICORE_INS_ABS_DF
"abs.f", // TRICORE_INS_ABS_F
"abs.h", // TRICORE_INS_ABS_H
"abs", // TRICORE_INS_ABS
"addc", // TRICORE_INS_ADDC
@ -39,6 +41,7 @@
"addx", // TRICORE_INS_ADDX
"add.a", // TRICORE_INS_ADD_A
"add.b", // TRICORE_INS_ADD_B
"add.df", // TRICORE_INS_ADD_DF
"add.f", // TRICORE_INS_ADD_F
"add.h", // TRICORE_INS_ADD_H
"add", // TRICORE_INS_ADD
@ -84,6 +87,7 @@
"cmovn", // TRICORE_INS_CMOVN
"cmov", // TRICORE_INS_CMOV
"cmpswap.w", // TRICORE_INS_CMPSWAP_W
"cmp.df", // TRICORE_INS_CMP_DF
"cmp.f", // TRICORE_INS_CMP_F
"crc32b.w", // TRICORE_INS_CRC32B_W
"crc32l.w", // TRICORE_INS_CRC32L_W
@ -95,8 +99,21 @@
"csub", // TRICORE_INS_CSUB
"debug", // TRICORE_INS_DEBUG
"dextr", // TRICORE_INS_DEXTR
"dftof", // TRICORE_INS_DFTOF
"dftoin", // TRICORE_INS_DFTOIN
"dftoiz", // TRICORE_INS_DFTOIZ
"dftoi", // TRICORE_INS_DFTOI
"dftolz", // TRICORE_INS_DFTOLZ
"dftol", // TRICORE_INS_DFTOL
"dftoulz", // TRICORE_INS_DFTOULZ
"dftoul", // TRICORE_INS_DFTOUL
"dftouz", // TRICORE_INS_DFTOUZ
"dftou", // TRICORE_INS_DFTOU
"difsc.a", // TRICORE_INS_DIFSC_A
"disable", // TRICORE_INS_DISABLE
"div64.u", // TRICORE_INS_DIV64_U
"div64", // TRICORE_INS_DIV64
"div.df", // TRICORE_INS_DIV_DF
"div.f", // TRICORE_INS_DIV_F
"div.u", // TRICORE_INS_DIV_U
"div", // TRICORE_INS_DIV
@ -125,7 +142,9 @@
"fcalli", // TRICORE_INS_FCALLI
"fcall", // TRICORE_INS_FCALL
"fret", // TRICORE_INS_FRET
"ftodf", // TRICORE_INS_FTODF
"ftohp", // TRICORE_INS_FTOHP
"ftoin", // TRICORE_INS_FTOIN
"ftoiz", // TRICORE_INS_FTOIZ
"ftoi", // TRICORE_INS_FTOI
"ftoq31z", // TRICORE_INS_FTOQ31Z
@ -141,6 +160,7 @@
"insn.t", // TRICORE_INS_INSN_T
"ins.t", // TRICORE_INS_INS_T
"isync", // TRICORE_INS_ISYNC
"itodf", // TRICORE_INS_ITODF
"itof", // TRICORE_INS_ITOF
"ixmax.u", // TRICORE_INS_IXMAX_U
"ixmax", // TRICORE_INS_IXMAX
@ -188,6 +208,7 @@
"lha", // TRICORE_INS_LHA
"loopu", // TRICORE_INS_LOOPU
"loop", // TRICORE_INS_LOOP
"ltodf", // TRICORE_INS_LTODF
"lt.a", // TRICORE_INS_LT_A
"lt.b", // TRICORE_INS_LT_B
"lt.bu", // TRICORE_INS_LT_BU
@ -218,6 +239,7 @@
"madds.q", // TRICORE_INS_MADDS_Q
"madds.u", // TRICORE_INS_MADDS_U
"madds", // TRICORE_INS_MADDS
"madd.df", // TRICORE_INS_MADD_DF
"madd.f", // TRICORE_INS_MADD_F
"madd.h", // TRICORE_INS_MADD_H
"madd.q", // TRICORE_INS_MADD_Q
@ -225,6 +247,8 @@
"madd", // TRICORE_INS_MADD
"max.b", // TRICORE_INS_MAX_B
"max.bu", // TRICORE_INS_MAX_BU
"max.df", // TRICORE_INS_MAX_DF
"max.f", // TRICORE_INS_MAX_F
"max.h", // TRICORE_INS_MAX_H
"max.hu", // TRICORE_INS_MAX_HU
"max.u", // TRICORE_INS_MAX_U
@ -232,6 +256,8 @@
"mfcr", // TRICORE_INS_MFCR
"min.b", // TRICORE_INS_MIN_B
"min.bu", // TRICORE_INS_MIN_BU
"min.df", // TRICORE_INS_MIN_DF
"min.f", // TRICORE_INS_MIN_F
"min.h", // TRICORE_INS_MIN_H
"min.hu", // TRICORE_INS_MIN_HU
"min.u", // TRICORE_INS_MIN_U
@ -265,6 +291,7 @@
"msubs.q", // TRICORE_INS_MSUBS_Q
"msubs.u", // TRICORE_INS_MSUBS_U
"msubs", // TRICORE_INS_MSUBS
"msub.df", // TRICORE_INS_MSUB_DF
"msub.f", // TRICORE_INS_MSUB_F
"msub.h", // TRICORE_INS_MSUB_H
"msub.q", // TRICORE_INS_MSUB_Q
@ -279,6 +306,7 @@
"mulr.q", // TRICORE_INS_MULR_Q
"muls.u", // TRICORE_INS_MULS_U
"muls", // TRICORE_INS_MULS
"mul.df", // TRICORE_INS_MUL_DF
"mul.f", // TRICORE_INS_MUL_F
"mul.h", // TRICORE_INS_MUL_H
"mul.q", // TRICORE_INS_MUL_Q
@ -286,6 +314,8 @@
"mul", // TRICORE_INS_MUL
"nand.t", // TRICORE_INS_NAND_T
"nand", // TRICORE_INS_NAND
"neg.df", // TRICORE_INS_NEG_DF
"neg.f", // TRICORE_INS_NEG_F
"nez.a", // TRICORE_INS_NEZ_A
"ne.a", // TRICORE_INS_NE_A
"ne", // TRICORE_INS_NE
@ -311,7 +341,10 @@
"parity", // TRICORE_INS_PARITY
"popcnt.w", // TRICORE_INS_POPCNT_W
"q31tof", // TRICORE_INS_Q31TOF
"qseed.df", // TRICORE_INS_QSEED_DF
"qseed.f", // TRICORE_INS_QSEED_F
"rem64.u", // TRICORE_INS_REM64_U
"rem64", // TRICORE_INS_REM64
"restore", // TRICORE_INS_RESTORE
"ret", // TRICORE_INS_RET
"rfe", // TRICORE_INS_RFE
@ -372,6 +405,7 @@
"subx", // TRICORE_INS_SUBX
"sub.a", // TRICORE_INS_SUB_A
"sub.b", // TRICORE_INS_SUB_B
"sub.df", // TRICORE_INS_SUB_DF
"sub.f", // TRICORE_INS_SUB_F
"sub.h", // TRICORE_INS_SUB_H
"sub", // TRICORE_INS_SUB
@ -388,8 +422,10 @@
"tlbprobe.i", // TRICORE_INS_TLBPROBE_I
"trapsv", // TRICORE_INS_TRAPSV
"trapv", // TRICORE_INS_TRAPV
"ultodf", // TRICORE_INS_ULTODF
"unpack", // TRICORE_INS_UNPACK
"updfl", // TRICORE_INS_UPDFL
"utodf", // TRICORE_INS_UTODF
"utof", // TRICORE_INS_UTOF
"wait", // TRICORE_INS_WAIT
"xnor.t", // TRICORE_INS_XNOR_T

2259
arch/TriCore/TriCoreGenCSMappingInsnOp.inc
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File diff suppressed because it is too large Load Diff

4577
arch/TriCore/TriCoreGenDisassemblerTables.inc
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File diff suppressed because it is too large Load Diff

4261
arch/TriCore/TriCoreGenInstrInfo.inc
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File diff suppressed because it is too large Load Diff

24
arch/TriCore/TriCoreGenSubtargetInfo.inc
View File

@ -22,17 +22,19 @@ enum {
TriCore_HasV160Ops = 4,
TriCore_HasV161Ops = 5,
TriCore_HasV162Ops = 6,
TriCore_TRICORE_PCP = 7,
TriCore_TRICORE_PCP2 = 8,
TriCore_TRICORE_RIDER_A = 9,
TriCore_TRICORE_V1_1 = 10,
TriCore_TRICORE_V1_2 = 11,
TriCore_TRICORE_V1_3 = 12,
TriCore_TRICORE_V1_3_1 = 13,
TriCore_TRICORE_V1_6 = 14,
TriCore_TRICORE_V1_6_1 = 15,
TriCore_TRICORE_V1_6_2 = 16,
TriCore_NumSubtargetFeatures = 17
TriCore_HasV180Ops = 7,
TriCore_TRICORE_PCP = 8,
TriCore_TRICORE_PCP2 = 9,
TriCore_TRICORE_RIDER_A = 10,
TriCore_TRICORE_V1_1 = 11,
TriCore_TRICORE_V1_2 = 12,
TriCore_TRICORE_V1_3 = 13,
TriCore_TRICORE_V1_3_1 = 14,
TriCore_TRICORE_V1_6 = 15,
TriCore_TRICORE_V1_6_1 = 16,
TriCore_TRICORE_V1_6_2 = 17,
TriCore_TRICORE_V1_8_0 = 18,
TriCore_NumSubtargetFeatures = 19
};
#endif // GET_SUBTARGETINFO_ENUM

2
bindings/python/capstone/__init__.py
View File

@ -126,6 +126,7 @@ __all__ = [
'CS_MODE_TRICORE_160',
'CS_MODE_TRICORE_161',
'CS_MODE_TRICORE_162',
"CS_MODE_TRICORE_180",
'CS_MODE_HPPA_11',
'CS_MODE_HPPA_20',
'CS_MODE_HPPA_20W',
@ -367,6 +368,7 @@ CS_MODE_TRICORE_131 = 1 << 4 # Tricore 1.3.1
CS_MODE_TRICORE_160 = 1 << 5 # Tricore 1.6
CS_MODE_TRICORE_161 = 1 << 6 # Tricore 1.6.1
CS_MODE_TRICORE_162 = 1 << 7 # Tricore 1.6.2
CS_MODE_TRICORE_180 = 1 << 8 # Tricore 1.8.0
CS_MODE_HPPA_11 = 1 << 1 # HPPA 1.1
CS_MODE_HPPA_20 = 1 << 2 # HPPA 2.0
CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide

827
bindings/python/capstone/tricore_const.py
View File

@ -79,387 +79,423 @@ TRICORE_INS_ABSS_B = 7
TRICORE_INS_ABSS_H = 8
TRICORE_INS_ABSS = 9
TRICORE_INS_ABS_B = 10
TRICORE_INS_ABS_H = 11
TRICORE_INS_ABS = 12
TRICORE_INS_ADDC = 13
TRICORE_INS_ADDIH_A = 14
TRICORE_INS_ADDIH = 15
TRICORE_INS_ADDI = 16
TRICORE_INS_ADDSC_AT = 17
TRICORE_INS_ADDSC_A = 18
TRICORE_INS_ADDS_BU = 19
TRICORE_INS_ADDS_B = 20
TRICORE_INS_ADDS_H = 21
TRICORE_INS_ADDS_HU = 22
TRICORE_INS_ADDS_U = 23
TRICORE_INS_ADDS = 24
TRICORE_INS_ADDX = 25
TRICORE_INS_ADD_A = 26
TRICORE_INS_ADD_B = 27
TRICORE_INS_ADD_F = 28
TRICORE_INS_ADD_H = 29
TRICORE_INS_ADD = 30
TRICORE_INS_ANDN_T = 31
TRICORE_INS_ANDN = 32
TRICORE_INS_AND_ANDN_T = 33
TRICORE_INS_AND_AND_T = 34
TRICORE_INS_AND_EQ = 35
TRICORE_INS_AND_GE_U = 36
TRICORE_INS_AND_GE = 37
TRICORE_INS_AND_LT_U = 38
TRICORE_INS_AND_LT = 39
TRICORE_INS_AND_NE = 40
TRICORE_INS_AND_NOR_T = 41
TRICORE_INS_AND_OR_T = 42
TRICORE_INS_AND_T = 43
TRICORE_INS_AND = 44
TRICORE_INS_BISR = 45
TRICORE_INS_BMERGE = 46
TRICORE_INS_BSPLIT = 47
TRICORE_INS_CACHEA_I = 48
TRICORE_INS_CACHEA_WI = 49
TRICORE_INS_CACHEA_W = 50
TRICORE_INS_CACHEI_I = 51
TRICORE_INS_CACHEI_WI = 52
TRICORE_INS_CACHEI_W = 53
TRICORE_INS_CADDN_A = 54
TRICORE_INS_CADDN = 55
TRICORE_INS_CADD_A = 56
TRICORE_INS_CADD = 57
TRICORE_INS_CALLA = 58
TRICORE_INS_CALLI = 59
TRICORE_INS_CALL = 60
TRICORE_INS_CLO_B = 61
TRICORE_INS_CLO_H = 62
TRICORE_INS_CLO = 63
TRICORE_INS_CLS_B = 64
TRICORE_INS_CLS_H = 65
TRICORE_INS_CLS = 66
TRICORE_INS_CLZ_B = 67
TRICORE_INS_CLZ_H = 68
TRICORE_INS_CLZ = 69
TRICORE_INS_CMOVN = 70
TRICORE_INS_CMOV = 71
TRICORE_INS_CMPSWAP_W = 72
TRICORE_INS_CMP_F = 73
TRICORE_INS_CRC32B_W = 74
TRICORE_INS_CRC32L_W = 75
TRICORE_INS_CRC32_B = 76
TRICORE_INS_CRCN = 77
TRICORE_INS_CSUBN_A = 78
TRICORE_INS_CSUBN = 79
TRICORE_INS_CSUB_A = 80
TRICORE_INS_CSUB = 81
TRICORE_INS_DEBUG = 82
TRICORE_INS_DEXTR = 83
TRICORE_INS_DIFSC_A = 84
TRICORE_INS_DISABLE = 85
TRICORE_INS_DIV_F = 86
TRICORE_INS_DIV_U = 87
TRICORE_INS_DIV = 88
TRICORE_INS_DSYNC = 89
TRICORE_INS_DVADJ = 90
TRICORE_INS_DVINIT_BU = 91
TRICORE_INS_DVINIT_B = 92
TRICORE_INS_DVINIT_HU = 93
TRICORE_INS_DVINIT_H = 94
TRICORE_INS_DVINIT_U = 95
TRICORE_INS_DVINIT = 96
TRICORE_INS_DVSTEP_U = 97
TRICORE_INS_DVSTEP = 98
TRICORE_INS_ENABLE = 99
TRICORE_INS_EQANY_B = 100
TRICORE_INS_EQANY_H = 101
TRICORE_INS_EQZ_A = 102
TRICORE_INS_EQ_A = 103
TRICORE_INS_EQ_B = 104
TRICORE_INS_EQ_H = 105
TRICORE_INS_EQ_W = 106
TRICORE_INS_EQ = 107
TRICORE_INS_EXTR_U = 108
TRICORE_INS_EXTR = 109
TRICORE_INS_FCALLA = 110
TRICORE_INS_FCALLI = 111
TRICORE_INS_FCALL = 112
TRICORE_INS_FRET = 113
TRICORE_INS_FTOHP = 114
TRICORE_INS_FTOIZ = 115
TRICORE_INS_FTOI = 116
TRICORE_INS_FTOQ31Z = 117
TRICORE_INS_FTOQ31 = 118
TRICORE_INS_FTOUZ = 119
TRICORE_INS_FTOU = 120
TRICORE_INS_GE_A = 121
TRICORE_INS_GE_U = 122
TRICORE_INS_GE = 123
TRICORE_INS_HPTOF = 124
TRICORE_INS_IMASK = 125
TRICORE_INS_INSERT = 126
TRICORE_INS_INSN_T = 127
TRICORE_INS_INS_T = 128
TRICORE_INS_ISYNC = 129
TRICORE_INS_ITOF = 130
TRICORE_INS_IXMAX_U = 131
TRICORE_INS_IXMAX = 132
TRICORE_INS_IXMIN_U = 133
TRICORE_INS_IXMIN = 134
TRICORE_INS_JA = 135
TRICORE_INS_JEQ_A = 136
TRICORE_INS_JEQ = 137
TRICORE_INS_JGEZ = 138
TRICORE_INS_JGE_U = 139
TRICORE_INS_JGE = 140
TRICORE_INS_JGTZ = 141
TRICORE_INS_JI = 142
TRICORE_INS_JLA = 143
TRICORE_INS_JLEZ = 144
TRICORE_INS_JLI = 145
TRICORE_INS_JLTZ = 146
TRICORE_INS_JLT_U = 147
TRICORE_INS_JLT = 148
TRICORE_INS_JL = 149
TRICORE_INS_JNED = 150
TRICORE_INS_JNEI = 151
TRICORE_INS_JNE_A = 152
TRICORE_INS_JNE = 153
TRICORE_INS_JNZ_A = 154
TRICORE_INS_JNZ_T = 155
TRICORE_INS_JNZ = 156
TRICORE_INS_JZ_A = 157
TRICORE_INS_JZ_T = 158
TRICORE_INS_JZ = 159
TRICORE_INS_J = 160
TRICORE_INS_LDLCX = 161
TRICORE_INS_LDMST = 162
TRICORE_INS_LDUCX = 163
TRICORE_INS_LD_A = 164
TRICORE_INS_LD_BU = 165
TRICORE_INS_LD_B = 166
TRICORE_INS_LD_DA = 167
TRICORE_INS_LD_D = 168
TRICORE_INS_LD_HU = 169
TRICORE_INS_LD_H = 170
TRICORE_INS_LD_Q = 171
TRICORE_INS_LD_W = 172
TRICORE_INS_LEA = 173
TRICORE_INS_LHA = 174
TRICORE_INS_LOOPU = 175
TRICORE_INS_LOOP = 176
TRICORE_INS_LT_A = 177
TRICORE_INS_LT_B = 178
TRICORE_INS_LT_BU = 179
TRICORE_INS_LT_H = 180
TRICORE_INS_LT_HU = 181
TRICORE_INS_LT_U = 182
TRICORE_INS_LT_W = 183
TRICORE_INS_LT_WU = 184
TRICORE_INS_LT = 185
TRICORE_INS_MADDMS_H = 186
TRICORE_INS_MADDMS_U = 187
TRICORE_INS_MADDMS = 188
TRICORE_INS_MADDM_H = 189
TRICORE_INS_MADDM_Q = 190
TRICORE_INS_MADDM_U = 191
TRICORE_INS_MADDM = 192
TRICORE_INS_MADDRS_H = 193
TRICORE_INS_MADDRS_Q = 194
TRICORE_INS_MADDR_H = 195
TRICORE_INS_MADDR_Q = 196
TRICORE_INS_MADDSUMS_H = 197
TRICORE_INS_MADDSUM_H = 198
TRICORE_INS_MADDSURS_H = 199
TRICORE_INS_MADDSUR_H = 200
TRICORE_INS_MADDSUS_H = 201
TRICORE_INS_MADDSU_H = 202
TRICORE_INS_MADDS_H = 203
TRICORE_INS_MADDS_Q = 204
TRICORE_INS_MADDS_U = 205
TRICORE_INS_MADDS = 206
TRICORE_INS_MADD_F = 207
TRICORE_INS_MADD_H = 208
TRICORE_INS_MADD_Q = 209
TRICORE_INS_MADD_U = 210
TRICORE_INS_MADD = 211
TRICORE_INS_MAX_B = 212
TRICORE_INS_MAX_BU = 213
TRICORE_INS_MAX_H = 214
TRICORE_INS_MAX_HU = 215
TRICORE_INS_MAX_U = 216
TRICORE_INS_MAX = 217
TRICORE_INS_MFCR = 218
TRICORE_INS_MIN_B = 219
TRICORE_INS_MIN_BU = 220
TRICORE_INS_MIN_H = 221
TRICORE_INS_MIN_HU = 222
TRICORE_INS_MIN_U = 223
TRICORE_INS_MIN = 224
TRICORE_INS_MOVH_A = 225
TRICORE_INS_MOVH = 226
TRICORE_INS_MOVZ_A = 227
TRICORE_INS_MOV_AA = 228
TRICORE_INS_MOV_A = 229
TRICORE_INS_MOV_D = 230
TRICORE_INS_MOV_U = 231
TRICORE_INS_MOV = 232
TRICORE_INS_MSUBADMS_H = 233
TRICORE_INS_MSUBADM_H = 234
TRICORE_INS_MSUBADRS_H = 235
TRICORE_INS_MSUBADR_H = 236
TRICORE_INS_MSUBADS_H = 237
TRICORE_INS_MSUBAD_H = 238
TRICORE_INS_MSUBMS_H = 239
TRICORE_INS_MSUBMS_U = 240
TRICORE_INS_MSUBMS = 241
TRICORE_INS_MSUBM_H = 242
TRICORE_INS_MSUBM_Q = 243
TRICORE_INS_MSUBM_U = 244
TRICORE_INS_MSUBM = 245
TRICORE_INS_MSUBRS_H = 246
TRICORE_INS_MSUBRS_Q = 247
TRICORE_INS_MSUBR_H = 248
TRICORE_INS_MSUBR_Q = 249
TRICORE_INS_MSUBS_H = 250
TRICORE_INS_MSUBS_Q = 251
TRICORE_INS_MSUBS_U = 252
TRICORE_INS_MSUBS = 253
TRICORE_INS_MSUB_F = 254
TRICORE_INS_MSUB_H = 255
TRICORE_INS_MSUB_Q = 256
TRICORE_INS_MSUB_U = 257
TRICORE_INS_MSUB = 258
TRICORE_INS_MTCR = 259
TRICORE_INS_MULMS_H = 260
TRICORE_INS_MULM_H = 261
TRICORE_INS_MULM_U = 262
TRICORE_INS_MULM = 263
TRICORE_INS_MULR_H = 264
TRICORE_INS_MULR_Q = 265
TRICORE_INS_MULS_U = 266
TRICORE_INS_MULS = 267
TRICORE_INS_MUL_F = 268
TRICORE_INS_MUL_H = 269
TRICORE_INS_MUL_Q = 270
TRICORE_INS_MUL_U = 271
TRICORE_INS_MUL = 272
TRICORE_INS_NAND_T = 273
TRICORE_INS_NAND = 274
TRICORE_INS_NEZ_A = 275
TRICORE_INS_NE_A = 276
TRICORE_INS_NE = 277
TRICORE_INS_NOP = 278
TRICORE_INS_NOR_T = 279
TRICORE_INS_NOR = 280
TRICORE_INS_NOT = 281
TRICORE_INS_ORN_T = 282
TRICORE_INS_ORN = 283
TRICORE_INS_OR_ANDN_T = 284
TRICORE_INS_OR_AND_T = 285
TRICORE_INS_OR_EQ = 286
TRICORE_INS_OR_GE_U = 287
TRICORE_INS_OR_GE = 288
TRICORE_INS_OR_LT_U = 289
TRICORE_INS_OR_LT = 290
TRICORE_INS_OR_NE = 291
TRICORE_INS_OR_NOR_T = 292
TRICORE_INS_OR_OR_T = 293
TRICORE_INS_OR_T = 294
TRICORE_INS_OR = 295
TRICORE_INS_PACK = 296
TRICORE_INS_PARITY = 297
TRICORE_INS_POPCNT_W = 298
TRICORE_INS_Q31TOF = 299
TRICORE_INS_QSEED_F = 300
TRICORE_INS_RESTORE = 301
TRICORE_INS_RET = 302
TRICORE_INS_RFE = 303
TRICORE_INS_RFM = 304
TRICORE_INS_RSLCX = 305
TRICORE_INS_RSTV = 306
TRICORE_INS_RSUBS_U = 307
TRICORE_INS_RSUBS = 308
TRICORE_INS_RSUB = 309
TRICORE_INS_SAT_BU = 310
TRICORE_INS_SAT_B = 311
TRICORE_INS_SAT_HU = 312
TRICORE_INS_SAT_H = 313
TRICORE_INS_SELN_A = 314
TRICORE_INS_SELN = 315
TRICORE_INS_SEL_A = 316
TRICORE_INS_SEL = 317
TRICORE_INS_SHAS = 318
TRICORE_INS_SHA_B = 319
TRICORE_INS_SHA_H = 320
TRICORE_INS_SHA = 321
TRICORE_INS_SHUFFLE = 322
TRICORE_INS_SH_ANDN_T = 323
TRICORE_INS_SH_AND_T = 324
TRICORE_INS_SH_B = 325
TRICORE_INS_SH_EQ = 326
TRICORE_INS_SH_GE_U = 327
TRICORE_INS_SH_GE = 328
TRICORE_INS_SH_H = 329
TRICORE_INS_SH_LT_U = 330
TRICORE_INS_SH_LT = 331
TRICORE_INS_SH_NAND_T = 332
TRICORE_INS_SH_NE = 333
TRICORE_INS_SH_NOR_T = 334
TRICORE_INS_SH_ORN_T = 335
TRICORE_INS_SH_OR_T = 336
TRICORE_INS_SH_XNOR_T = 337
TRICORE_INS_SH_XOR_T = 338
TRICORE_INS_SH = 339
TRICORE_INS_STLCX = 340
TRICORE_INS_STUCX = 341
TRICORE_INS_ST_A = 342
TRICORE_INS_ST_B = 343
TRICORE_INS_ST_DA = 344
TRICORE_INS_ST_D = 345
TRICORE_INS_ST_H = 346
TRICORE_INS_ST_Q = 347
TRICORE_INS_ST_T = 348
TRICORE_INS_ST_W = 349
TRICORE_INS_SUBC = 350
TRICORE_INS_SUBSC_A = 351
TRICORE_INS_SUBS_BU = 352
TRICORE_INS_SUBS_B = 353
TRICORE_INS_SUBS_HU = 354
TRICORE_INS_SUBS_H = 355
TRICORE_INS_SUBS_U = 356
TRICORE_INS_SUBS = 357
TRICORE_INS_SUBX = 358
TRICORE_INS_SUB_A = 359
TRICORE_INS_SUB_B = 360
TRICORE_INS_SUB_F = 361
TRICORE_INS_SUB_H = 362
TRICORE_INS_SUB = 363
TRICORE_INS_SVLCX = 364
TRICORE_INS_SWAPMSK_W = 365
TRICORE_INS_SWAP_A = 366
TRICORE_INS_SWAP_W = 367
TRICORE_INS_SYSCALL = 368
TRICORE_INS_TLBDEMAP = 369
TRICORE_INS_TLBFLUSH_A = 370
TRICORE_INS_TLBFLUSH_B = 371
TRICORE_INS_TLBMAP = 372
TRICORE_INS_TLBPROBE_A = 373
TRICORE_INS_TLBPROBE_I = 374
TRICORE_INS_TRAPSV = 375
TRICORE_INS_TRAPV = 376
TRICORE_INS_UNPACK = 377
TRICORE_INS_UPDFL = 378
TRICORE_INS_UTOF = 379
TRICORE_INS_WAIT = 380
TRICORE_INS_XNOR_T = 381
TRICORE_INS_XNOR = 382
TRICORE_INS_XOR_EQ = 383
TRICORE_INS_XOR_GE_U = 384
TRICORE_INS_XOR_GE = 385
TRICORE_INS_XOR_LT_U = 386
TRICORE_INS_XOR_LT = 387
TRICORE_INS_XOR_NE = 388
TRICORE_INS_XOR_T = 389
TRICORE_INS_XOR = 390
TRICORE_INS_ENDING = 391
TRICORE_INS_ABS_DF = 11
TRICORE_INS_ABS_F = 12
TRICORE_INS_ABS_H = 13
TRICORE_INS_ABS = 14
TRICORE_INS_ADDC = 15
TRICORE_INS_ADDIH_A = 16
TRICORE_INS_ADDIH = 17
TRICORE_INS_ADDI = 18
TRICORE_INS_ADDSC_AT = 19
TRICORE_INS_ADDSC_A = 20
TRICORE_INS_ADDS_BU = 21
TRICORE_INS_ADDS_B = 22
TRICORE_INS_ADDS_H = 23
TRICORE_INS_ADDS_HU = 24
TRICORE_INS_ADDS_U = 25
TRICORE_INS_ADDS = 26
TRICORE_INS_ADDX = 27
TRICORE_INS_ADD_A = 28
TRICORE_INS_ADD_B = 29
TRICORE_INS_ADD_DF = 30
TRICORE_INS_ADD_F = 31
TRICORE_INS_ADD_H = 32
TRICORE_INS_ADD = 33
TRICORE_INS_ANDN_T = 34
TRICORE_INS_ANDN = 35
TRICORE_INS_AND_ANDN_T = 36
TRICORE_INS_AND_AND_T = 37
TRICORE_INS_AND_EQ = 38
TRICORE_INS_AND_GE_U = 39
TRICORE_INS_AND_GE = 40
TRICORE_INS_AND_LT_U = 41
TRICORE_INS_AND_LT = 42
TRICORE_INS_AND_NE = 43
TRICORE_INS_AND_NOR_T = 44
TRICORE_INS_AND_OR_T = 45
TRICORE_INS_AND_T = 46
TRICORE_INS_AND = 47
TRICORE_INS_BISR = 48
TRICORE_INS_BMERGE = 49
TRICORE_INS_BSPLIT = 50
TRICORE_INS_CACHEA_I = 51
TRICORE_INS_CACHEA_WI = 52
TRICORE_INS_CACHEA_W = 53
TRICORE_INS_CACHEI_I = 54
TRICORE_INS_CACHEI_WI = 55
TRICORE_INS_CACHEI_W = 56
TRICORE_INS_CADDN_A = 57
TRICORE_INS_CADDN = 58
TRICORE_INS_CADD_A = 59
TRICORE_INS_CADD = 60
TRICORE_INS_CALLA = 61
TRICORE_INS_CALLI = 62
TRICORE_INS_CALL = 63
TRICORE_INS_CLO_B = 64
TRICORE_INS_CLO_H = 65
TRICORE_INS_CLO = 66
TRICORE_INS_CLS_B = 67
TRICORE_INS_CLS_H = 68
TRICORE_INS_CLS = 69
TRICORE_INS_CLZ_B = 70
TRICORE_INS_CLZ_H = 71
TRICORE_INS_CLZ = 72
TRICORE_INS_CMOVN = 73
TRICORE_INS_CMOV = 74
TRICORE_INS_CMPSWAP_W = 75
TRICORE_INS_CMP_DF = 76
TRICORE_INS_CMP_F = 77
TRICORE_INS_CRC32B_W = 78
TRICORE_INS_CRC32L_W = 79
TRICORE_INS_CRC32_B = 80
TRICORE_INS_CRCN = 81
TRICORE_INS_CSUBN_A = 82
TRICORE_INS_CSUBN = 83
TRICORE_INS_CSUB_A = 84
TRICORE_INS_CSUB = 85
TRICORE_INS_DEBUG = 86
TRICORE_INS_DEXTR = 87
TRICORE_INS_DFTOF = 88
TRICORE_INS_DFTOIN = 89
TRICORE_INS_DFTOIZ = 90
TRICORE_INS_DFTOI = 91
TRICORE_INS_DFTOLZ = 92
TRICORE_INS_DFTOL = 93
TRICORE_INS_DFTOULZ = 94
TRICORE_INS_DFTOUL = 95
TRICORE_INS_DFTOUZ = 96
TRICORE_INS_DFTOU = 97
TRICORE_INS_DIFSC_A = 98
TRICORE_INS_DISABLE = 99
TRICORE_INS_DIV64_U = 100
TRICORE_INS_DIV64 = 101
TRICORE_INS_DIV_DF = 102
TRICORE_INS_DIV_F = 103
TRICORE_INS_DIV_U = 104
TRICORE_INS_DIV = 105
TRICORE_INS_DSYNC = 106
TRICORE_INS_DVADJ = 107
TRICORE_INS_DVINIT_BU = 108
TRICORE_INS_DVINIT_B = 109
TRICORE_INS_DVINIT_HU = 110
TRICORE_INS_DVINIT_H = 111
TRICORE_INS_DVINIT_U = 112
TRICORE_INS_DVINIT = 113
TRICORE_INS_DVSTEP_U = 114
TRICORE_INS_DVSTEP = 115
TRICORE_INS_ENABLE = 116
TRICORE_INS_EQANY_B = 117
TRICORE_INS_EQANY_H = 118
TRICORE_INS_EQZ_A = 119
TRICORE_INS_EQ_A = 120
TRICORE_INS_EQ_B = 121
TRICORE_INS_EQ_H = 122
TRICORE_INS_EQ_W = 123
TRICORE_INS_EQ = 124
TRICORE_INS_EXTR_U = 125
TRICORE_INS_EXTR = 126
TRICORE_INS_FCALLA = 127
TRICORE_INS_FCALLI = 128
TRICORE_INS_FCALL = 129
TRICORE_INS_FRET = 130
TRICORE_INS_FTODF = 131
TRICORE_INS_FTOHP = 132
TRICORE_INS_FTOIN = 133
TRICORE_INS_FTOIZ = 134
TRICORE_INS_FTOI = 135
TRICORE_INS_FTOQ31Z = 136
TRICORE_INS_FTOQ31 = 137
TRICORE_INS_FTOUZ = 138
TRICORE_INS_FTOU = 139
TRICORE_INS_GE_A = 140
TRICORE_INS_GE_U = 141
TRICORE_INS_GE = 142
TRICORE_INS_HPTOF = 143
TRICORE_INS_IMASK = 144
TRICORE_INS_INSERT = 145
TRICORE_INS_INSN_T = 146
TRICORE_INS_INS_T = 147
TRICORE_INS_ISYNC = 148
TRICORE_INS_ITODF = 149
TRICORE_INS_ITOF = 150
TRICORE_INS_IXMAX_U = 151
TRICORE_INS_IXMAX = 152
TRICORE_INS_IXMIN_U = 153
TRICORE_INS_IXMIN = 154
TRICORE_INS_JA = 155
TRICORE_INS_JEQ_A = 156
TRICORE_INS_JEQ = 157
TRICORE_INS_JGEZ = 158
TRICORE_INS_JGE_U = 159
TRICORE_INS_JGE = 160
TRICORE_INS_JGTZ = 161
TRICORE_INS_JI = 162
TRICORE_INS_JLA = 163
TRICORE_INS_JLEZ = 164
TRICORE_INS_JLI = 165
TRICORE_INS_JLTZ = 166
TRICORE_INS_JLT_U = 167
TRICORE_INS_JLT = 168
TRICORE_INS_JL = 169
TRICORE_INS_JNED = 170
TRICORE_INS_JNEI = 171
TRICORE_INS_JNE_A = 172
TRICORE_INS_JNE = 173
TRICORE_INS_JNZ_A = 174
TRICORE_INS_JNZ_T = 175
TRICORE_INS_JNZ = 176
TRICORE_INS_JZ_A = 177
TRICORE_INS_JZ_T = 178
TRICORE_INS_JZ = 179
TRICORE_INS_J = 180
TRICORE_INS_LDLCX = 181
TRICORE_INS_LDMST = 182
TRICORE_INS_LDUCX = 183
TRICORE_INS_LD_A = 184
TRICORE_INS_LD_BU = 185
TRICORE_INS_LD_B = 186
TRICORE_INS_LD_DA = 187
TRICORE_INS_LD_D = 188
TRICORE_INS_LD_HU = 189
TRICORE_INS_LD_H = 190
TRICORE_INS_LD_Q = 191
TRICORE_INS_LD_W = 192
TRICORE_INS_LEA = 193
TRICORE_INS_LHA = 194
TRICORE_INS_LOOPU = 195
TRICORE_INS_LOOP = 196
TRICORE_INS_LTODF = 197
TRICORE_INS_LT_A = 198
TRICORE_INS_LT_B = 199
TRICORE_INS_LT_BU = 200
TRICORE_INS_LT_H = 201
TRICORE_INS_LT_HU = 202
TRICORE_INS_LT_U = 203
TRICORE_INS_LT_W = 204
TRICORE_INS_LT_WU = 205
TRICORE_INS_LT = 206
TRICORE_INS_MADDMS_H = 207
TRICORE_INS_MADDMS_U = 208
TRICORE_INS_MADDMS = 209
TRICORE_INS_MADDM_H = 210
TRICORE_INS_MADDM_Q = 211
TRICORE_INS_MADDM_U = 212
TRICORE_INS_MADDM = 213
TRICORE_INS_MADDRS_H = 214
TRICORE_INS_MADDRS_Q = 215
TRICORE_INS_MADDR_H = 216
TRICORE_INS_MADDR_Q = 217
TRICORE_INS_MADDSUMS_H = 218
TRICORE_INS_MADDSUM_H = 219
TRICORE_INS_MADDSURS_H = 220
TRICORE_INS_MADDSUR_H = 221
TRICORE_INS_MADDSUS_H = 222
TRICORE_INS_MADDSU_H = 223
TRICORE_INS_MADDS_H = 224
TRICORE_INS_MADDS_Q = 225
TRICORE_INS_MADDS_U = 226
TRICORE_INS_MADDS = 227
TRICORE_INS_MADD_DF = 228
TRICORE_INS_MADD_F = 229
TRICORE_INS_MADD_H = 230
TRICORE_INS_MADD_Q = 231
TRICORE_INS_MADD_U = 232
TRICORE_INS_MADD = 233
TRICORE_INS_MAX_B = 234
TRICORE_INS_MAX_BU = 235
TRICORE_INS_MAX_DF = 236
TRICORE_INS_MAX_F = 237
TRICORE_INS_MAX_H = 238
TRICORE_INS_MAX_HU = 239
TRICORE_INS_MAX_U = 240
TRICORE_INS_MAX = 241
TRICORE_INS_MFCR = 242
TRICORE_INS_MIN_B = 243
TRICORE_INS_MIN_BU = 244
TRICORE_INS_MIN_DF = 245
TRICORE_INS_MIN_F = 246
TRICORE_INS_MIN_H = 247
TRICORE_INS_MIN_HU = 248
TRICORE_INS_MIN_U = 249
TRICORE_INS_MIN = 250
TRICORE_INS_MOVH_A = 251
TRICORE_INS_MOVH = 252
TRICORE_INS_MOVZ_A = 253
TRICORE_INS_MOV_AA = 254
TRICORE_INS_MOV_A = 255
TRICORE_INS_MOV_D = 256
TRICORE_INS_MOV_U = 257
TRICORE_INS_MOV = 258
TRICORE_INS_MSUBADMS_H = 259
TRICORE_INS_MSUBADM_H = 260
TRICORE_INS_MSUBADRS_H = 261
TRICORE_INS_MSUBADR_H = 262
TRICORE_INS_MSUBADS_H = 263
TRICORE_INS_MSUBAD_H = 264
TRICORE_INS_MSUBMS_H = 265
TRICORE_INS_MSUBMS_U = 266
TRICORE_INS_MSUBMS = 267
TRICORE_INS_MSUBM_H = 268
TRICORE_INS_MSUBM_Q = 269
TRICORE_INS_MSUBM_U = 270
TRICORE_INS_MSUBM = 271
TRICORE_INS_MSUBRS_H = 272
TRICORE_INS_MSUBRS_Q = 273
TRICORE_INS_MSUBR_H = 274
TRICORE_INS_MSUBR_Q = 275
TRICORE_INS_MSUBS_H = 276
TRICORE_INS_MSUBS_Q = 277
TRICORE_INS_MSUBS_U = 278
TRICORE_INS_MSUBS = 279
TRICORE_INS_MSUB_DF = 280
TRICORE_INS_MSUB_F = 281
TRICORE_INS_MSUB_H = 282
TRICORE_INS_MSUB_Q = 283
TRICORE_INS_MSUB_U = 284
TRICORE_INS_MSUB = 285
TRICORE_INS_MTCR = 286
TRICORE_INS_MULMS_H = 287
TRICORE_INS_MULM_H = 288
TRICORE_INS_MULM_U = 289
TRICORE_INS_MULM = 290
TRICORE_INS_MULR_H = 291
TRICORE_INS_MULR_Q = 292
TRICORE_INS_MULS_U = 293
TRICORE_INS_MULS = 294
TRICORE_INS_MUL_DF = 295
TRICORE_INS_MUL_F = 296
TRICORE_INS_MUL_H = 297
TRICORE_INS_MUL_Q = 298
TRICORE_INS_MUL_U = 299
TRICORE_INS_MUL = 300
TRICORE_INS_NAND_T = 301
TRICORE_INS_NAND = 302
TRICORE_INS_NEG_DF = 303
TRICORE_INS_NEG_F = 304
TRICORE_INS_NEZ_A = 305
TRICORE_INS_NE_A = 306
TRICORE_INS_NE = 307
TRICORE_INS_NOP = 308
TRICORE_INS_NOR_T = 309
TRICORE_INS_NOR = 310
TRICORE_INS_NOT = 311
TRICORE_INS_ORN_T = 312
TRICORE_INS_ORN = 313
TRICORE_INS_OR_ANDN_T = 314
TRICORE_INS_OR_AND_T = 315
TRICORE_INS_OR_EQ = 316
TRICORE_INS_OR_GE_U = 317
TRICORE_INS_OR_GE = 318
TRICORE_INS_OR_LT_U = 319
TRICORE_INS_OR_LT = 320
TRICORE_INS_OR_NE = 321
TRICORE_INS_OR_NOR_T = 322
TRICORE_INS_OR_OR_T = 323
TRICORE_INS_OR_T = 324
TRICORE_INS_OR = 325
TRICORE_INS_PACK = 326
TRICORE_INS_PARITY = 327
TRICORE_INS_POPCNT_W = 328
TRICORE_INS_Q31TOF = 329
TRICORE_INS_QSEED_DF = 330
TRICORE_INS_QSEED_F = 331
TRICORE_INS_REM64_U = 332
TRICORE_INS_REM64 = 333
TRICORE_INS_RESTORE = 334
TRICORE_INS_RET = 335
TRICORE_INS_RFE = 336
TRICORE_INS_RFM = 337
TRICORE_INS_RSLCX = 338
TRICORE_INS_RSTV = 339
TRICORE_INS_RSUBS_U = 340
TRICORE_INS_RSUBS = 341
TRICORE_INS_RSUB = 342
TRICORE_INS_SAT_BU = 343
TRICORE_INS_SAT_B = 344
TRICORE_INS_SAT_HU = 345
TRICORE_INS_SAT_H = 346
TRICORE_INS_SELN_A = 347
TRICORE_INS_SELN = 348
TRICORE_INS_SEL_A = 349
TRICORE_INS_SEL = 350
TRICORE_INS_SHAS = 351
TRICORE_INS_SHA_B = 352
TRICORE_INS_SHA_H = 353
TRICORE_INS_SHA = 354
TRICORE_INS_SHUFFLE = 355
TRICORE_INS_SH_ANDN_T = 356
TRICORE_INS_SH_AND_T = 357
TRICORE_INS_SH_B = 358
TRICORE_INS_SH_EQ = 359
TRICORE_INS_SH_GE_U = 360
TRICORE_INS_SH_GE = 361
TRICORE_INS_SH_H = 362
TRICORE_INS_SH_LT_U = 363
TRICORE_INS_SH_LT = 364
TRICORE_INS_SH_NAND_T = 365
TRICORE_INS_SH_NE = 366
TRICORE_INS_SH_NOR_T = 367
TRICORE_INS_SH_ORN_T = 368
TRICORE_INS_SH_OR_T = 369
TRICORE_INS_SH_XNOR_T = 370
TRICORE_INS_SH_XOR_T = 371
TRICORE_INS_SH = 372
TRICORE_INS_STLCX = 373
TRICORE_INS_STUCX = 374
TRICORE_INS_ST_A = 375
TRICORE_INS_ST_B = 376
TRICORE_INS_ST_DA = 377
TRICORE_INS_ST_D = 378
TRICORE_INS_ST_H = 379
TRICORE_INS_ST_Q = 380
TRICORE_INS_ST_T = 381
TRICORE_INS_ST_W = 382
TRICORE_INS_SUBC = 383
TRICORE_INS_SUBSC_A = 384
TRICORE_INS_SUBS_BU = 385
TRICORE_INS_SUBS_B = 386
TRICORE_INS_SUBS_HU = 387
TRICORE_INS_SUBS_H = 388
TRICORE_INS_SUBS_U = 389
TRICORE_INS_SUBS = 390
TRICORE_INS_SUBX = 391
TRICORE_INS_SUB_A = 392
TRICORE_INS_SUB_B = 393
TRICORE_INS_SUB_DF = 394
TRICORE_INS_SUB_F = 395
TRICORE_INS_SUB_H = 396
TRICORE_INS_SUB = 397
TRICORE_INS_SVLCX = 398
TRICORE_INS_SWAPMSK_W = 399
TRICORE_INS_SWAP_A = 400
TRICORE_INS_SWAP_W = 401
TRICORE_INS_SYSCALL = 402
TRICORE_INS_TLBDEMAP = 403
TRICORE_INS_TLBFLUSH_A = 404
TRICORE_INS_TLBFLUSH_B = 405
TRICORE_INS_TLBMAP = 406
TRICORE_INS_TLBPROBE_A = 407
TRICORE_INS_TLBPROBE_I = 408
TRICORE_INS_TRAPSV = 409
TRICORE_INS_TRAPV = 410
TRICORE_INS_ULTODF = 411
TRICORE_INS_UNPACK = 412
TRICORE_INS_UPDFL = 413
TRICORE_INS_UTODF = 414
TRICORE_INS_UTOF = 415
TRICORE_INS_WAIT = 416
TRICORE_INS_XNOR_T = 417
TRICORE_INS_XNOR = 418
TRICORE_INS_XOR_EQ = 419
TRICORE_INS_XOR_GE_U = 420
TRICORE_INS_XOR_GE = 421
TRICORE_INS_XOR_LT_U = 422
TRICORE_INS_XOR_LT = 423
TRICORE_INS_XOR_NE = 424
TRICORE_INS_XOR_T = 425
TRICORE_INS_XOR = 426
TRICORE_INS_ENDING = 427
TRICORE_GRP_INVALID = 0
TRICORE_GRP_CALL = 1
@ -474,16 +510,19 @@ TRICORE_FEATURE_HASV131 = 131
TRICORE_FEATURE_HASV160 = 132
TRICORE_FEATURE_HASV161 = 133
TRICORE_FEATURE_HASV162 = 134
TRICORE_FEATURE_HASV120_UP = 135
TRICORE_FEATURE_HASV130_UP = 136
TRICORE_FEATURE_HASV131_UP = 137
TRICORE_FEATURE_HASV160_UP = 138
TRICORE_FEATURE_HASV161_UP = 139
TRICORE_FEATURE_HASV162_UP = 140
TRICORE_FEATURE_HASV120_DN = 141
TRICORE_FEATURE_HASV130_DN = 142
TRICORE_FEATURE_HASV131_DN = 143
TRICORE_FEATURE_HASV160_DN = 144
TRICORE_FEATURE_HASV161_DN = 145
TRICORE_FEATURE_HASV162_DN = 146
TRICORE_FEATURE_ENDING = 147
TRICORE_FEATURE_HASV180 = 135
TRICORE_FEATURE_HASV120_UP = 136
TRICORE_FEATURE_HASV130_UP = 137
TRICORE_FEATURE_HASV131_UP = 138
TRICORE_FEATURE_HASV160_UP = 139
TRICORE_FEATURE_HASV161_UP = 140
TRICORE_FEATURE_HASV162_UP = 141
TRICORE_FEATURE_HASV180_UP = 142
TRICORE_FEATURE_HASV120_DN = 143
TRICORE_FEATURE_HASV130_DN = 144
TRICORE_FEATURE_HASV131_DN = 145
TRICORE_FEATURE_HASV160_DN = 146
TRICORE_FEATURE_HASV161_DN = 147
TRICORE_FEATURE_HASV162_DN = 148
TRICORE_FEATURE_HASV180_DN = 149
TRICORE_FEATURE_ENDING = 150

2
cs.c
View File

@ -244,7 +244,7 @@ typedef struct cs_arch_config {
TRICORE_option, \
~(CS_MODE_TRICORE_110 | CS_MODE_TRICORE_120 | CS_MODE_TRICORE_130 \
| CS_MODE_TRICORE_131 | CS_MODE_TRICORE_160 | CS_MODE_TRICORE_161 \
| CS_MODE_TRICORE_162 | CS_MODE_LITTLE_ENDIAN), \
| CS_MODE_TRICORE_162 | CS_MODE_TRICORE_180 | CS_MODE_LITTLE_ENDIAN), \
}
#define CS_ARCH_CONFIG_ALPHA \
{ \

1
cstool/cstool.c
View File

@ -233,6 +233,7 @@ static struct {
{ "tc160", "Tricore V1.6", CS_ARCH_TRICORE, CS_MODE_TRICORE_160 },
{ "tc161", "Tricore V1.6.1", CS_ARCH_TRICORE, CS_MODE_TRICORE_161 },
{ "tc162", "Tricore V1.6.2", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 },
{ "tc180", "Tricore V1.8.0", CS_ARCH_TRICORE, CS_MODE_TRICORE_180 },
{ "loongarch32", "LoongArch 32-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32 },
{ "loongarch64", "LoongArch 64-bit", CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64 },

1
include/capstone/capstone.h
View File

@ -210,6 +210,7 @@ typedef enum cs_mode {
CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6
CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1
CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2
CS_MODE_TRICORE_180 = 1 << 8, ///< Tricore 1.8.0
CS_MODE_HPPA_11 = 1 << 1, ///< HPPA 1.1
CS_MODE_HPPA_20 = 1 << 2, ///< HPPA 2.0
CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide

39
include/capstone/tricore.h
View File

@ -146,6 +146,8 @@ typedef enum tricore_insn {
TRICORE_INS_ABSS_H,
TRICORE_INS_ABSS,
TRICORE_INS_ABS_B,
TRICORE_INS_ABS_DF,
TRICORE_INS_ABS_F,
TRICORE_INS_ABS_H,
TRICORE_INS_ABS,
TRICORE_INS_ADDC,
@ -163,6 +165,7 @@ typedef enum tricore_insn {
TRICORE_INS_ADDX,
TRICORE_INS_ADD_A,
TRICORE_INS_ADD_B,
TRICORE_INS_ADD_DF,
TRICORE_INS_ADD_F,
TRICORE_INS_ADD_H,
TRICORE_INS_ADD,
@ -208,6 +211,7 @@ typedef enum tricore_insn {
TRICORE_INS_CMOVN,
TRICORE_INS_CMOV,
TRICORE_INS_CMPSWAP_W,
TRICORE_INS_CMP_DF,
TRICORE_INS_CMP_F,
TRICORE_INS_CRC32B_W,
TRICORE_INS_CRC32L_W,
@ -219,8 +223,21 @@ typedef enum tricore_insn {
TRICORE_INS_CSUB,
TRICORE_INS_DEBUG,
TRICORE_INS_DEXTR,
TRICORE_INS_DFTOF,
TRICORE_INS_DFTOIN,
TRICORE_INS_DFTOIZ,
TRICORE_INS_DFTOI,
TRICORE_INS_DFTOLZ,
TRICORE_INS_DFTOL,
TRICORE_INS_DFTOULZ,
TRICORE_INS_DFTOUL,
TRICORE_INS_DFTOUZ,
TRICORE_INS_DFTOU,
TRICORE_INS_DIFSC_A,
TRICORE_INS_DISABLE,
TRICORE_INS_DIV64_U,
TRICORE_INS_DIV64,
TRICORE_INS_DIV_DF,
TRICORE_INS_DIV_F,
TRICORE_INS_DIV_U,
TRICORE_INS_DIV,
@ -249,7 +266,9 @@ typedef enum tricore_insn {
TRICORE_INS_FCALLI,
TRICORE_INS_FCALL,
TRICORE_INS_FRET,
TRICORE_INS_FTODF,
TRICORE_INS_FTOHP,
TRICORE_INS_FTOIN,
TRICORE_INS_FTOIZ,
TRICORE_INS_FTOI,
TRICORE_INS_FTOQ31Z,
@ -265,6 +284,7 @@ typedef enum tricore_insn {
TRICORE_INS_INSN_T,
TRICORE_INS_INS_T,
TRICORE_INS_ISYNC,
TRICORE_INS_ITODF,
TRICORE_INS_ITOF,
TRICORE_INS_IXMAX_U,
TRICORE_INS_IXMAX,
@ -312,6 +332,7 @@ typedef enum tricore_insn {
TRICORE_INS_LHA,
TRICORE_INS_LOOPU,
TRICORE_INS_LOOP,
TRICORE_INS_LTODF,
TRICORE_INS_LT_A,
TRICORE_INS_LT_B,
TRICORE_INS_LT_BU,
@ -342,6 +363,7 @@ typedef enum tricore_insn {
TRICORE_INS_MADDS_Q,
TRICORE_INS_MADDS_U,
TRICORE_INS_MADDS,
TRICORE_INS_MADD_DF,
TRICORE_INS_MADD_F,
TRICORE_INS_MADD_H,
TRICORE_INS_MADD_Q,
@ -349,6 +371,8 @@ typedef enum tricore_insn {
TRICORE_INS_MADD,
TRICORE_INS_MAX_B,
TRICORE_INS_MAX_BU,
TRICORE_INS_MAX_DF,
TRICORE_INS_MAX_F,
TRICORE_INS_MAX_H,
TRICORE_INS_MAX_HU,
TRICORE_INS_MAX_U,
@ -356,6 +380,8 @@ typedef enum tricore_insn {
TRICORE_INS_MFCR,
TRICORE_INS_MIN_B,
TRICORE_INS_MIN_BU,
TRICORE_INS_MIN_DF,
TRICORE_INS_MIN_F,
TRICORE_INS_MIN_H,
TRICORE_INS_MIN_HU,
TRICORE_INS_MIN_U,
@ -389,6 +415,7 @@ typedef enum tricore_insn {
TRICORE_INS_MSUBS_Q,
TRICORE_INS_MSUBS_U,
TRICORE_INS_MSUBS,
TRICORE_INS_MSUB_DF,
TRICORE_INS_MSUB_F,
TRICORE_INS_MSUB_H,
TRICORE_INS_MSUB_Q,
@ -403,6 +430,7 @@ typedef enum tricore_insn {
TRICORE_INS_MULR_Q,
TRICORE_INS_MULS_U,
TRICORE_INS_MULS,
TRICORE_INS_MUL_DF,
TRICORE_INS_MUL_F,
TRICORE_INS_MUL_H,
TRICORE_INS_MUL_Q,
@ -410,6 +438,8 @@ typedef enum tricore_insn {
TRICORE_INS_MUL,
TRICORE_INS_NAND_T,
TRICORE_INS_NAND,
TRICORE_INS_NEG_DF,
TRICORE_INS_NEG_F,
TRICORE_INS_NEZ_A,
TRICORE_INS_NE_A,
TRICORE_INS_NE,
@ -435,7 +465,10 @@ typedef enum tricore_insn {
TRICORE_INS_PARITY,
TRICORE_INS_POPCNT_W,
TRICORE_INS_Q31TOF,
TRICORE_INS_QSEED_DF,
TRICORE_INS_QSEED_F,
TRICORE_INS_REM64_U,
TRICORE_INS_REM64,
TRICORE_INS_RESTORE,
TRICORE_INS_RET,
TRICORE_INS_RFE,
@ -496,6 +529,7 @@ typedef enum tricore_insn {
TRICORE_INS_SUBX,
TRICORE_INS_SUB_A,
TRICORE_INS_SUB_B,
TRICORE_INS_SUB_DF,
TRICORE_INS_SUB_F,
TRICORE_INS_SUB_H,
TRICORE_INS_SUB,
@ -512,8 +546,10 @@ typedef enum tricore_insn {
TRICORE_INS_TLBPROBE_I,
TRICORE_INS_TRAPSV,
TRICORE_INS_TRAPV,
TRICORE_INS_ULTODF,
TRICORE_INS_UNPACK,
TRICORE_INS_UPDFL,
TRICORE_INS_UTODF,
TRICORE_INS_UTOF,
TRICORE_INS_WAIT,
TRICORE_INS_XNOR_T,
@ -553,18 +589,21 @@ typedef enum tricore_feature_t {
TRICORE_FEATURE_HASV160,
TRICORE_FEATURE_HASV161,
TRICORE_FEATURE_HASV162,
TRICORE_FEATURE_HASV180,
TRICORE_FEATURE_HASV120_UP,
TRICORE_FEATURE_HASV130_UP,
TRICORE_FEATURE_HASV131_UP,
TRICORE_FEATURE_HASV160_UP,
TRICORE_FEATURE_HASV161_UP,
TRICORE_FEATURE_HASV162_UP,
TRICORE_FEATURE_HASV180_UP,
TRICORE_FEATURE_HASV120_DN,
TRICORE_FEATURE_HASV130_DN,
TRICORE_FEATURE_HASV131_DN,
TRICORE_FEATURE_HASV160_DN,
TRICORE_FEATURE_HASV161_DN,
TRICORE_FEATURE_HASV162_DN,
TRICORE_FEATURE_HASV180_DN,
// clang-format on
// generated content <TriCoreGenCSFeatureEnum.inc> end

2
suite/MC/TriCore/tc130.s.cs
View File

@ -105,7 +105,7 @@
0xaa, 0x00 = cmov d0, d15, #0
0x6a, 0x00 = cmovn d0, d15, d0
0xea, 0x00 = cmovn d0, d15, #0
0x4b, 0x00, 0x00, 0x00 = cmp.f d0, d0, d0
0x4b, 0x00, 0x01, 0x00 = cmp.f d0, d0, d0
0x2b, 0x00, 0x20, 0x00 = csub d0, d0, d0, d0
0x2b, 0x00, 0x30, 0x00 = csubn d0, d0, d0, d0
0x00, 0xa0 = debug

2
suite/MC/TriCore/tc131.s.cs
View File

@ -111,7 +111,7 @@
0xaa, 0x00 = cmov d0, d15, #0
0x6a, 0x00 = cmovn d0, d15, d0
0xea, 0x00 = cmovn d0, d15, #0
0x4b, 0x00, 0x00, 0x00 = cmp.f d0, d0, d0
0x4b, 0x00, 0x01, 0x00 = cmp.f d0, d0, d0
0x2b, 0x00, 0x20, 0x00 = csub d0, d0, d0, d0
0x2b, 0x00, 0x30, 0x00 = csubn d0, d0, d0, d0
0x00, 0xa0 = debug

2
suite/MC/TriCore/tc160.s.cs
View File

@ -114,7 +114,7 @@
0xaa, 0x00 = cmov d0, d15, #0
0x6a, 0x00 = cmovn d0, d15, d0
0xea, 0x00 = cmovn d0, d15, #0
0x4b, 0x00, 0x00, 0x00 = cmp.f d0, d0, d0
0x4b, 0x00, 0x01, 0x00 = cmp.f d0, d0, d0
0x2b, 0x00, 0x20, 0x00 = csub d0, d0, d0, d0
0x2b, 0x00, 0x30, 0x00 = csubn d0, d0, d0, d0
0x00, 0xa0 = debug

2
suite/MC/TriCore/tc161.s.cs
View File

@ -115,7 +115,7 @@
0xaa, 0x00 = cmov d0, d15, #0
0x6a, 0x00 = cmovn d0, d15, d0
0xea, 0x00 = cmovn d0, d15, #0
0x4b, 0x00, 0x00, 0x00 = cmp.f d0, d0, d0
0x4b, 0x00, 0x01, 0x00 = cmp.f d0, d0, d0
0x49, 0x00, 0xc0, 0x08 = cmpswap.w [a0]#0, e0
0x69, 0x00, 0xc0, 0x00 = cmpswap.w [p0+r], e0
0x69, 0x00, 0xc0, 0x04 = cmpswap.w [p0+c]#0, e0

2
suite/MC/TriCore/tc162.s.cs
View File

@ -114,7 +114,7 @@
0xaa, 0x00 = cmov d0, d15, #0
0x6a, 0x00 = cmovn d0, d15, d0
0xea, 0x00 = cmovn d0, d15, #0
0x4b, 0x00, 0x00, 0x00 = cmp.f d0, d0, d0
0x4b, 0x00, 0x01, 0x00 = cmp.f d0, d0, d0
0x49, 0x00, 0xc0, 0x08 = cmpswap.w [a0]#0, e0
0x69, 0x00, 0xc0, 0x00 = cmpswap.w [p0+r], e0
0x69, 0x00, 0xc0, 0x04 = cmpswap.w [p0+c]#0, e0

36
suite/MC/TriCore/tc180.c.cs Normal file
View File

@ -0,0 +1,36 @@
0x6b, 0x04, 0x22, 0x02 = add.df e0, e2, e4
0x6b, 0x04, 0x32, 0x02 = sub.df e0, e2, e4
0x6b, 0x20, 0x62, 0x64 = madd.df e6, e4, e0, e2
0x6b, 0x20, 0x72, 0x64 = msub.df e6, e4, e0, e2
0x4b, 0x42, 0x42, 0x00 = mul.df e0, e2, e4
0x4b, 0x20, 0x52, 0x40 = div.df e4, e0, e2
0x4b, 0x20, 0x02, 0x40 = cmp.df d4, e0, e2
0x4b, 0x20, 0x22, 0x43 = max.df e4, e0, e2
0x4b, 0x20, 0x32, 0x43 = min.df e4, e0, e2
0x4b, 0x20, 0x31, 0x43 = min.f d4, d0, d2
0x4b, 0x20, 0x21, 0x43 = max.f d4, d0, d2
0x4b, 0x0a, 0x02, 0x21 = dftoi d2, e10
0x4b, 0x0a, 0x32, 0x21 = dftoiz d2, e10
0x4b, 0x0a, 0x72, 0x23 = dftoin d2, e10
0x4b, 0x0a, 0x71, 0x23 = ftoin d2, d10
0x4b, 0x0a, 0x22, 0x21 = dftou d2, e10
0x4b, 0x0a, 0x72, 0x21 = dftouz d2, e10
0x4b, 0x00, 0xa2, 0x21 = dftol e2, e0
0x4b, 0x00, 0xe2, 0x21 = dftoul e2, e0
0x4b, 0x00, 0xf2, 0x21 = dftoulz e2, e0
0x4b, 0x01, 0x01, 0x43 = abs.f d4, d1
0x4b, 0x02, 0x02, 0x43 = abs.df e4, e2
0x4b, 0x0a, 0xb2, 0x21 = dftolz e2, e10
0x4b, 0x0a, 0x12, 0x23 = neg.df e2, e10
0x4b, 0x0a, 0x11, 0x23 = neg.f d2, d10
0x4b, 0x00, 0x92, 0x21 = qseed.df e2, e0
0x4b, 0x00, 0x42, 0x21 = itodf e2, d0
0x4b, 0x00, 0x62, 0x21 = utodf e2, d0
0x4b, 0x00, 0x62, 0x22 = ltodf e2, e0
0x4b, 0x00, 0x72, 0x22 = ultodf e2, e0
0x4b, 0x02, 0x82, 0x12 = dftof d1, e2
0x4b, 0x05, 0x92, 0x22 = ftodf e2, d5
0x4b, 0x04, 0x02, 0x22 = div64 e2, e4, e0
0x4b, 0x04, 0x12, 0x22 = div64.u e2, e4, e0
0x4b, 0x04, 0x42, 0x23 = rem64 e2, e4, e0
0x4b, 0x04, 0x52, 0x23 = rem64.u e2, e4, e0

1
suite/cstest/include/test_mapping.h
View File

@ -175,6 +175,7 @@ static const cs_enum_id_map test_mode_map[] = {
{ .str = "CS_MODE_TRICORE_160", .val = CS_MODE_TRICORE_160 },
{ .str = "CS_MODE_TRICORE_161", .val = CS_MODE_TRICORE_161 },
{ .str = "CS_MODE_TRICORE_162", .val = CS_MODE_TRICORE_162 },
{ .str = "CS_MODE_TRICORE_180", .val = CS_MODE_TRICORE_180 },
{ .str = "CS_MODE_V8", .val = CS_MODE_V8 },
{ .str = "CS_MODE_V9", .val = CS_MODE_V9 },
{ .str = "CS_MODE_XTENSA_ESP32", .val = CS_MODE_XTENSA_ESP32 },

6
suite/fuzz/platform.c
View File

@ -379,6 +379,12 @@ struct platform platforms[] = {
"TRICORE",
"tc162"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_180,
"TRICORE",
"tc180"
},
{
CS_ARCH_XTENSA,
CS_MODE_XTENSA_ESP32,

2
suite/test_corpus3.py
View File

@ -81,6 +81,7 @@ def test_file(fname):
"CS_MODE_TRICORE_160": CS_MODE_TRICORE_160,
"CS_MODE_TRICORE_161": CS_MODE_TRICORE_161,
"CS_MODE_TRICORE_162": CS_MODE_TRICORE_162,
"CS_MODE_TRICORE_180": CS_MODE_TRICORE_180,
"CS_MODE_BIG_ENDIAN+CS_MODE_QPX": CS_MODE_BIG_ENDIAN+CS_MODE_QPX,
"CS_MODE_HPPA_11": CS_MODE_HPPA_11,
"CS_MODE_HPPA_20": CS_MODE_HPPA_20,
@ -134,6 +135,7 @@ def test_file(fname):
("CS_ARCH_ALPHA", "CS_MODE_BIG_ENDIAN"): 56,
("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57,
("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58,
("CS_ARCH_TRICORE", "CS_MODE_TRICORE_180"): 59,
}
# if not option in ('', 'None'):

2
tests/MC/TriCore/debug.s.yaml
View File

@ -1,7 +1,7 @@
test_cases:
-
input:
bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
bytes: [ 0x4b, 0x00, 0x01, 0x00 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_131" ]
expected:

2
tests/MC/TriCore/tc130.s.yaml
View File

@ -955,7 +955,7 @@ test_cases:
asm_text: "cmovn d0, d15, #0"
-
input:
bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
bytes: [ 0x4b, 0x00, 0x01, 0x00 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_130" ]
expected:

2
tests/MC/TriCore/tc131.s.yaml
View File

@ -1009,7 +1009,7 @@ test_cases:
asm_text: "cmovn d0, d15, #0"
-
input:
bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
bytes: [ 0x4b, 0x00, 0x01, 0x00 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_131" ]
expected:

2
tests/MC/TriCore/tc160.s.yaml
View File

@ -1036,7 +1036,7 @@ test_cases:
asm_text: "cmovn d0, d15, #0"
-
input:
bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
bytes: [ 0x4b, 0x00, 0x01, 0x00 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_160" ]
expected:

2
tests/MC/TriCore/tc161.s.yaml
View File

@ -1045,7 +1045,7 @@ test_cases:
asm_text: "cmovn d0, d15, #0"
-
input:
bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
bytes: [ 0x4b, 0x00, 0x01, 0x00 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_161" ]
expected:

2
tests/MC/TriCore/tc162.s.yaml
View File

@ -1036,7 +1036,7 @@ test_cases:
asm_text: "cmovn d0, d15, #0"
-
input:
bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
bytes: [ 0x4b, 0x00, 0x01, 0x00 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_162" ]
expected:

351
tests/MC/TriCore/tc180.s.yaml Normal file
View File

@ -0,0 +1,351 @@
test_cases:
-
input:
bytes: [ 0x6b, 0x04, 0x22, 0x02 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "add.df e0, e2, e4"
-
input:
bytes: [ 0x6b, 0x04, 0x32, 0x02 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "sub.df e0, e2, e4"
-
input:
bytes: [ 0x6b, 0x20, 0x62, 0x64 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "madd.df e6, e4, e0, e2"
-
input:
bytes: [ 0x6b, 0x20, 0x72, 0x64 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "msub.df e6, e4, e0, e2"
-
input:
bytes: [ 0x4b, 0x42, 0x42, 0x00 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "mul.df e0, e2, e4"
-
input:
bytes: [ 0x4b, 0x20, 0x52, 0x40 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "div.df e4, e0, e2"
-
input:
bytes: [ 0x4b, 0x20, 0x02, 0x40 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "cmp.df d4, e0, e2"
-
input:
bytes: [ 0x4b, 0x20, 0x22, 0x43 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "max.df e4, e0, e2"
-
input:
bytes: [ 0x4b, 0x20, 0x32, 0x43 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "min.df e4, e0, e2"
-
input:
bytes: [ 0x4b, 0x20, 0x31, 0x43 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "min.f d4, d0, d2"
-
input:
bytes: [ 0x4b, 0x20, 0x21, 0x43 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "max.f d4, d0, d2"
-
input:
bytes: [ 0x4b, 0x0a, 0x02, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftoi d2, e10"
-
input:
bytes: [ 0x4b, 0x0a, 0x32, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftoiz d2, e10"
-
input:
bytes: [ 0x4b, 0x0a, 0x72, 0x23 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftoin d2, e10"
-
input:
bytes: [ 0x4b, 0x0a, 0x71, 0x23 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "ftoin d2, d10"
-
input:
bytes: [ 0x4b, 0x0a, 0x22, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftou d2, e10"
-
input:
bytes: [ 0x4b, 0x0a, 0x72, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftouz d2, e10"
-
input:
bytes: [ 0x4b, 0x00, 0xa2, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftol e2, e0"
-
input:
bytes: [ 0x4b, 0x00, 0xe2, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftoul e2, e0"
-
input:
bytes: [ 0x4b, 0x00, 0xf2, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftoulz e2, e0"
-
input:
bytes: [ 0x4b, 0x01, 0x01, 0x43 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "abs.f d4, d1"
-
input:
bytes: [ 0x4b, 0x02, 0x02, 0x43 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "abs.df e4, e2"
-
input:
bytes: [ 0x4b, 0x0a, 0xb2, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftolz e2, e10"
-
input:
bytes: [ 0x4b, 0x0a, 0x12, 0x23 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "neg.df e2, e10"
-
input:
bytes: [ 0x4b, 0x0a, 0x11, 0x23 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "neg.f d2, d10"
-
input:
bytes: [ 0x4b, 0x00, 0x92, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "qseed.df e2, e0"
-
input:
bytes: [ 0x4b, 0x00, 0x42, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "itodf e2, d0"
-
input:
bytes: [ 0x4b, 0x00, 0x62, 0x21 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "utodf e2, d0"
-
input:
bytes: [ 0x4b, 0x00, 0x62, 0x22 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "ltodf e2, e0"
-
input:
bytes: [ 0x4b, 0x00, 0x72, 0x22 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "ultodf e2, e0"
-
input:
bytes: [ 0x4b, 0x02, 0x82, 0x12 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "dftof d1, e2"
-
input:
bytes: [ 0x4b, 0x05, 0x92, 0x22 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "ftodf e2, d5"
-
input:
bytes: [ 0x4b, 0x04, 0x02, 0x22 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "div64 e2, e4, e0"
-
input:
bytes: [ 0x4b, 0x04, 0x12, 0x22 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "div64.u e2, e4, e0"
-
input:
bytes: [ 0x4b, 0x04, 0x42, 0x23 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "rem64 e2, e4, e0"
-
input:
bytes: [ 0x4b, 0x04, 0x52, 0x23 ]
arch: "CS_ARCH_TRICORE"
options: [ "CS_MODE_TRICORE_180" ]
expected:
insns:
-
asm_text: "rem64.u e2, e4, e0"

630
tests/details/tricore.yaml
View File

@ -623,4 +623,632 @@ test_cases:
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
access: CS_AC_READ
- input:
bytes: [ 0x6b, 0x04, 0x22, 0x02 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "add.df e0, e2, e4"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- input:
bytes: [ 0x6b, 0x04, 0x32, 0x02 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "sub.df e0, e2, e4"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- input:
bytes: [ 0x6b, 0x20, 0x62, 0x64 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "madd.df e6, e4, e0, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e6
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x6b, 0x20, 0x72, 0x64 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "msub.df e6, e4, e0, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e6
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x42, 0x42, 0x00 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "mul.df e0, e2, e4"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x20, 0x52, 0x40 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "div.df e4, e0, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x20, 0x02, 0x40 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "cmp.df d4, e0, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x20, 0x22, 0x43 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "max.df e4, e0, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x20, 0x32, 0x43 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "min.df e4, e0, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x20, 0x31, 0x43 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "min.f d4, d0, d2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x20, 0x21, 0x43 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "max.f d4, d0, d2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x02, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftoi d2, e10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x32, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftoiz d2, e10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x72, 0x23 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftoin d2, e10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x71, 0x23 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ftoin d2, d10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x22, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftou d2, e10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x72, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftouz d2, e10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0xa2, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftol e2, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0xe2, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftoul e2, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0xf2, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftoulz e2, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x01, 0x01, 0x43 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "abs.f d4, d1"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d1
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x02, 0x02, 0x43 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "abs.df e4, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0xb2, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftolz e2, e10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x12, 0x23 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "neg.df e2, e10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x0a, 0x11, 0x23 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "neg.f d2, d10"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d10
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0x92, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "qseed.df e2, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0x42, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "itodf e2, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0x62, 0x21 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "utodf e2, d0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0x62, 0x22 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ltodf e2, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x00, 0x72, 0x22 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ultodf e2, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x02, 0x82, 0x12 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "dftof d1, e2"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: d1
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x05, 0x92, 0x22 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "ftodf e2, d5"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: d5
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x04, 0x02, 0x22 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "div64 e2, e4, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x04, 0x12, 0x22 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "div64.u e2, e4, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x04, 0x42, 0x23 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "rem64 e2, e4, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ
- input:
bytes: [ 0x4b, 0x04, 0x52, 0x23 ]
arch: CS_ARCH_TRICORE
options: [ CS_MODE_TRICORE_180, CS_OPT_DETAIL ]
expected:
insns:
- asm_text: "rem64.u e2, e4, e0"
details:
tricore:
operands:
- type: TRICORE_OP_REG
reg: e2
access: CS_AC_WRITE
- type: TRICORE_OP_REG
reg: e4
access: CS_AC_READ
- type: TRICORE_OP_REG
reg: e0
access: CS_AC_READ