diff --git a/bindings/java/capstone/Arm64_const.java b/bindings/java/capstone/Arm64_const.java
index 3048c439..6c07e605 100644
--- a/bindings/java/capstone/Arm64_const.java
+++ b/bindings/java/capstone/Arm64_const.java
@@ -776,17 +776,6 @@ public class Arm64_const {
 	public static final int ARM64_SYSREG_ZCR_EL3 = 0xF090;
 	public static final int ARM64_SYSREG_ZCR_EL12 = 0xE890;
 	public static final int ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90;
-	public static final int ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;
-	public static final int ARM64_SYSREG_OSLAR_EL1 = 0x8084;
-	public static final int ARM64_SYSREG_PMSWINC_EL0 = 0xdce4;
-	public static final int ARM64_SYSREG_TRCOSLAR = 0x8884;
-	public static final int ARM64_SYSREG_TRCLAR = 0x8be6;
-	public static final int ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661;
-	public static final int ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641;
-	public static final int ARM64_SYSREG_ICC_DIR_EL1 = 0xc659;
-	public static final int ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d;
-	public static final int ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e;
-	public static final int ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f;
 
 	public static final int ARM64_PSTATE_INVALID = 0;
 	public static final int ARM64_PSTATE_SPSEL = 0x05;
diff --git a/bindings/ocaml/arm64_const.ml b/bindings/ocaml/arm64_const.ml
index 388b8e82..a8000311 100644
--- a/bindings/ocaml/arm64_const.ml
+++ b/bindings/ocaml/arm64_const.ml
@@ -773,17 +773,6 @@ let _ARM64_SYSREG_ZCR_EL2 = 0xE090;;
 let _ARM64_SYSREG_ZCR_EL3 = 0xF090;;
 let _ARM64_SYSREG_ZCR_EL12 = 0xE890;;
 let _ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90;;
-let _ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828;;
-let _ARM64_SYSREG_OSLAR_EL1 = 0x8084;;
-let _ARM64_SYSREG_PMSWINC_EL0 = 0xdce4;;
-let _ARM64_SYSREG_TRCOSLAR = 0x8884;;
-let _ARM64_SYSREG_TRCLAR = 0x8be6;;
-let _ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661;;
-let _ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641;;
-let _ARM64_SYSREG_ICC_DIR_EL1 = 0xc659;;
-let _ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d;;
-let _ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e;;
-let _ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f;;
 
 let _ARM64_PSTATE_INVALID = 0;;
 let _ARM64_PSTATE_SPSEL = 0x05;;
diff --git a/bindings/python/capstone/arm64_const.py b/bindings/python/capstone/arm64_const.py
index 43d7f3df..b0579283 100644
--- a/bindings/python/capstone/arm64_const.py
+++ b/bindings/python/capstone/arm64_const.py
@@ -773,17 +773,6 @@ ARM64_SYSREG_ZCR_EL2 = 0xE090
 ARM64_SYSREG_ZCR_EL3 = 0xF090
 ARM64_SYSREG_ZCR_EL12 = 0xE890
 ARM64_SYSREG_CPM_IOACC_CTL_EL3 = 0xFF90
-ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828
-ARM64_SYSREG_OSLAR_EL1 = 0x8084
-ARM64_SYSREG_PMSWINC_EL0 = 0xdce4
-ARM64_SYSREG_TRCOSLAR = 0x8884
-ARM64_SYSREG_TRCLAR = 0x8be6
-ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661
-ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641
-ARM64_SYSREG_ICC_DIR_EL1 = 0xc659
-ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d
-ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e
-ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f
 
 ARM64_PSTATE_INVALID = 0
 ARM64_PSTATE_SPSEL = 0x05