Virtualization
/
capstone
mirror of https://gitlab.com/qemu-project/capstone.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fix some warnings reported by MSVC

This commit is contained in:
Nguyen Anh Quynh 2014-05-12 15:15:32 +08:00
parent 3878ff0641
commit 638835a1d5
4 changed files with 10 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/AArch64/AArch64InstPrinter.c
View File

@ -583,10 +583,10 @@ static void printSImm7ScaledOperand(MCInst *MI, unsigned OpNum,
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = res;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].mem.disp = (int32_t)res;
} else {
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = res;
MI->flat_insn.arm64.operands[MI->flat_insn.arm64.op_count].imm = (int32_t)res;
MI->flat_insn.arm64.op_count++;
}
}

4
arch/ARM/ARMInstPrinter.c
View File

@ -1152,8 +1152,8 @@ static void printMemBOption(MCInst *MI, unsigned OpNum, SStream *O)
unsigned val = (unsigned int)MCOperand_getImm(MCInst_getOperand(MI, OpNum));
// FIXME: HasV80Ops becomes a mode
// SStream_concat(O, ARM_MB_MemBOptToString(val,
// ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops));
SStream_concat(O, ARM_MB_MemBOptToString(val, ARM_HasV8Ops));
// ARM_getFeatureBits(MI->csh->mode) & ARM_HasV8Ops));
SStream_concat(O, ARM_MB_MemBOptToString(val, true));
}
void printInstSyncBOption(MCInst *MI, unsigned OpNum, SStream *O)

2
arch/SystemZ/SystemZDisassembler.c
View File

@ -38,7 +38,7 @@ static DecodeStatus decodeRegisterClass(MCInst *Inst, uint64_t RegNo, const unsi
if (RegNo == 0)
return MCDisassembler_Fail;
MCInst_addOperand(Inst, MCOperand_CreateReg(RegNo));
MCInst_addOperand(Inst, MCOperand_CreateReg((unsigned)RegNo));
return MCDisassembler_Success;
}

19
arch/X86/X86DisassemblerDecoder.c
View File

@ -46,14 +46,6 @@ static const char *x86DisassemblerGetInstrName(unsigned Opcode)
#define TRUE 1
#define FALSE 0
#define NDEBUG
#ifndef NDEBUG
#define debug(s) do { x86DisassemblerDebug(__FILE__, __LINE__, s); } while (0)
#else
#define debug(s) ((void) 0)
#endif
/*
* contextForAttrs - Client for the instruction context table. Takes a set of
* attributes and returns the appropriate decode context.
@ -221,7 +213,7 @@ static InstrUID decode(OpcodeType type,
switch (dec->modrm_type) {
default:
debug("Corrupt table! Unknown modrm_type");
//debug("Corrupt table! Unknown modrm_type");
return 0;
case MODRM_ONEENTRY:
return modRMTable[dec->instructionIDs];
@ -493,7 +485,7 @@ static int readPrefixes(struct InternalInstruction* insn)
insn->segmentOverride = SEG_OVERRIDE_GS;
break;
default:
debug("Unhandled override");
//debug("Unhandled override");
return -1;
}
if (prefixGroups[1])
@ -1265,7 +1257,7 @@ static int readSIB(struct InternalInstruction* insn)
insn->sibBase = (SIBBase)(sibBaseBase + base);
break;
case 0x3:
debug("Cannot have Mod = 0b11 and a SIB byte");
//debug("Cannot have Mod = 0b11 and a SIB byte");
return -1;
}
break;
@ -1535,7 +1527,6 @@ static int readModRM(struct InternalInstruction* insn)
} \
switch (type) { \
default: \
debug("Unhandled register type"); \
*valid = 0; \
return 0; \
case TYPE_Rv: \
@ -1621,7 +1612,7 @@ static int fixupReg(struct InternalInstruction *insn,
switch ((OperandEncoding)op->encoding) {
default:
debug("Expected a REG or R/M encoding in fixupReg");
//debug("Expected a REG or R/M encoding in fixupReg");
return -1;
case ENCODING_VVVV:
insn->vvvv = (Reg)fixupRegValue(insn,
@ -1725,7 +1716,7 @@ static int readImmediate(struct InternalInstruction* insn, uint8_t size)
// dbgprintf(insn, "readImmediate()");
if (insn->numImmediatesConsumed == 2) {
debug("Already consumed two immediates");
//debug("Already consumed two immediates");
return -1;
}