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Merge pull request #6 from danghvu/master 

Consistency of test output for binding and core
This commit is contained in:
Hoang-Vu Dang 2013-11-27 23:05:10 -08:00
parent f10be9bb9d c4325f8593
commit 7143f8ab8f
20 changed files with 469 additions and 198 deletions
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46
bindings/Makefile Normal file
View File

@ -0,0 +1,46 @@
TMPDIR = /tmp/capstone_test
DIFF = diff -u -w
TEST = $(TMPDIR)/test
TEST_ARM = $(TMPDIR)/test_arm
TEST_ARM64 = $(TMPDIR)/test_arm64
TEST_MIPS = $(TMPDIR)/test_mips
TEST_X86 = $(TMPDIR)/test_x86
all: expected python java #oclma ruby
expected:
$(MAKE) -C ../tests
mkdir -p $(TMPDIR)
../tests/test > $(TEST)_e
../tests/test_arm > $(TEST_ARM)_e
../tests/test_arm64 > $(TEST_ARM64)_e
../tests/test_mips > $(TEST_MIPS)_e
../tests/test_x86 > $(TEST_X86)_e
python: FORCE
python python/test.py > $(TEST)_o
python python/test_arm.py > $(TEST_ARM)_o
python python/test_arm64.py > $(TEST_ARM64)_o
python python/test_mips.py > $(TEST_MIPS)_o
python python/test_x86.py > $(TEST_X86)_o
$(MAKE) test
java: FORCE
$(MAKE) -C java
cd java; ./run.sh > $(TEST)_o
cd java; ./run.sh arm > $(TEST_ARM)_o
cd java; ./run.sh arm64 > $(TEST_ARM64)_o
cd java; ./run.sh mips > $(TEST_MIPS)_o
cd java; ./run.sh x86 > $(TEST_X86)_o
$(MAKE) test
test: FORCE
$(DIFF) $(TEST)_e $(TEST)_o
$(DIFF) $(TEST_ARM)_e $(TEST_ARM)_o
$(DIFF) $(TEST_ARM64)_e $(TEST_ARM64)_o
$(DIFF) $(TEST_MIPS)_e $(TEST_MIPS)_o
$(DIFF) $(TEST_X86)_e $(TEST_X86)_o
FORCE:

26
bindings/java/Makefile
View File

@ -3,8 +3,28 @@
JNA = /usr/share/java/jna/jna.jar
all:
javac -classpath $(JNA) CS.java Arm.java Arm64.java Mips.java X86.java Test.java TestArm.java TestArm64.java TestMips.java TestX86.java
ifneq ($(wildcard $(JNA)),)
else
ifneq ($(wildcard /usr/share/java/jna.jar),)
JNA = /usr/share/java/jna.jar
else
JNA =
$(error Unable to find jna.jar)
endif
endif
CAPSTONE_JAVA = Capstone.java Arm.java Arm64.java Mips.java X86.java
all: capstone tests
capstone: capstone_class
jar cf capstone.jar capstone/*.class
capstone_class:
cd capstone; javac -classpath $(JNA) $(CAPSTONE_JAVA)
tests:
javac -classpath "$(JNA):capstone.jar" Test.java TestArm.java TestArm64.java TestMips.java TestX86.java
clean:
rm -rf *.class *.log
rm -rf *.class *.log *.jar

15
bindings/java/Test.java
View File

@ -5,6 +5,8 @@ import com.sun.jna.Native;
import com.sun.jna.Memory;
import com.sun.jna.Pointer;
import capstone.Capstone;
public class Test {
public static class platform {
public int arch;
@ -20,7 +22,7 @@ public class Test {
}
};
static String stringToHex(byte[] code) {
static public String stringToHex(byte[] code) {
StringBuilder buf = new StringBuilder(200);
for (byte ch: code) {
if (buf.length() > 0)
@ -48,7 +50,7 @@ public class Test {
Capstone.CS_ARCH_X86,
Capstone.CS_MODE_32,
new byte[] { (byte)0x8d, 0x4c, 0x32, 0x08, 0x01, (byte)0xd8, (byte)0x81, (byte)0xc6, 0x34, 0x12, 0x00, 0x00 },
"X86 32bit (Intel syntax)"
"X86 32 (Intel syntax)"
),
new platform(
Capstone.CS_ARCH_X86,
@ -102,18 +104,20 @@ public class Test {
};
for (int j = 0; j < platforms.length; j++) {
System.out.println("************");
System.out.println("****************");
System.out.println(String.format("Platform: %s", platforms[j].comment));
System.out.println(String.format("Code: %s", stringToHex(platforms[j].code)));
System.out.println("Disasm:");
Capstone cs = new Capstone(platforms[j].arch, platforms[j].mode);
Capstone.cs_insn[] all_insn = cs.disasm(platforms[j].code, 0x1000);
for (int i = 0; i < all_insn.length; i++) {
System.out.println(String.format("0x%x\t%s\t%s", all_insn[i].address,
System.out.println(String.format("0x%x: \t%s\t%s", all_insn[i].address,
all_insn[i].mnemonic, all_insn[i].operands));
/*
if (all_insn[i].regs_read[0] != 0) {
System.out.print("\tRegister read: ");
for(int k = 0; k < all_insn[i].regs_read.length; k++) {
@ -142,8 +146,9 @@ public class Test {
System.out.print(String.format("%d ", all_insn[i].groups[k]));
}
System.out.println();
}
}*/
}
System.out.printf("0x%x:\n\n", all_insn[all_insn.length-1].address + all_insn[all_insn.length-1].size);
}
}
}

41
bindings/java/TestArm.java
View File

@ -5,6 +5,9 @@ import com.sun.jna.Native;
import com.sun.jna.Memory;
import com.sun.jna.Pointer;
import capstone.Capstone;
import capstone.Arm;
public class TestArm {
static byte[] hexString2Byte(String s) {
@ -38,31 +41,19 @@ public class TestArm {
Arm.OpInfo op_info = (Arm.OpInfo) ins.op_info;
if (op_info.cc != Arm.ARM_CC_AL && op_info.cc != Arm.ARM_CC_INVALID){
System.out.printf("\tCode condition: %d\n", op_info.cc);
}
if (op_info.update_flags) {
System.out.println("\tUpdate-flags: True");
}
if (op_info.writeback) {
System.out.println("\tWriteback: True");
}
if (op_info.op != null) {
System.out.printf("\top_count: %d\n", op_info.op.length);
for (int c=1; c<op_info.op.length+1; c++) {
Arm.Operand i = (Arm.Operand) op_info.op[c-1];
for (int c=0; c<op_info.op.length; c++) {
Arm.Operand i = (Arm.Operand) op_info.op[c];
String imm = hex(i.value.imm);
if (i.type == Arm.ARM_OP_REG)
System.out.printf("\t\toperands[%d].type: REG = %s\n", c, cs.reg_name(i.value.reg));
if (i.type == Arm.ARM_OP_IMM)
System.out.printf("\t\toperands[%d].type: IMM = %s\n", c, imm);
System.out.printf("\t\toperands[%d].type: IMM = 0x%x\n", c, i.value.imm);
if (i.type == Arm.ARM_OP_PIMM)
System.out.printf("\t\toperands[%d].type: P-IMM = %s\n", c, imm);
System.out.printf("\t\toperands[%d].type: P-IMM = %d\n", c, i.value.imm);
if (i.type == Arm.ARM_OP_CIMM)
System.out.printf("\t\toperands[%d].type: C-IMM = %s\n", c, imm);
System.out.printf("\t\toperands[%d].type: C-IMM = %d\n", c, i.value.imm);
if (i.type == Arm.ARM_OP_FP)
System.out.printf("\t\toperands[%d].type: FP = %f\n", c, i.value.fp);
if (i.type == Arm.ARM_OP_MEM) {
@ -74,13 +65,21 @@ public class TestArm {
if (index != null)
System.out.printf("\t\t\toperands[%d].mem.index: REG = %s\n", c, index);
if (i.value.mem.scale != 1)
System.out.printf("\t\t\toperands[%d].mem.scale: %s\n", c, hex(i.value.mem.scale));
System.out.printf("\t\t\toperands[%d].mem.scale: %d\n", c, (i.value.mem.scale));
if (i.value.mem.disp != 0)
System.out.printf("\t\t\toperands[%d].mem.disp: %s\n", c, hex(i.value.mem.disp));
System.out.printf("\t\t\toperands[%d].mem.disp: 0x%x\n", c, (i.value.mem.disp));
}
if (i.shift.type != Arm.ARM_SFT_INVALID && i.shift.value > 0)
System.out.printf("\t\t\tShift: type = %d, value = %d\n", i.shift.type, i.shift.value);
}
if (op_info.writeback)
System.out.println("\tWrite-back: True");
if (op_info.update_flags)
System.out.println("\tUpdate-flags: True");
if (op_info.cc != Arm.ARM_CC_AL && op_info.cc != Arm.ARM_CC_INVALID)
System.out.printf("\tCode condition: %d\n", op_info.cc);
}
}
@ -95,8 +94,9 @@ public class TestArm {
for (int i=0; i<all_tests.length; i++) {
Test.platform test = all_tests[i];
System.out.println(new String(new char[30]).replace("\0", "*"));
System.out.println(new String(new char[16]).replace("\0", "*"));
System.out.println("Platform: " + test.comment);
System.out.println("Code: " + Test.stringToHex(test.code));
System.out.println("Disasm:");
cs = new Capstone(test.arch, test.mode);
@ -106,6 +106,7 @@ public class TestArm {
print_ins_detail(all_ins[j]);
System.out.println();
}
System.out.printf("0x%x:\n\n", (all_ins[all_ins.length-1].address + all_ins[all_ins.length-1].size));
}
}

42
bindings/java/TestArm64.java
View File

@ -5,6 +5,9 @@ import com.sun.jna.Native;
import com.sun.jna.Memory;
import com.sun.jna.Pointer;
import capstone.Capstone;
import capstone.Arm64;
public class TestArm64 {
static byte[] hexString2Byte(String s) {
@ -35,29 +38,17 @@ public class TestArm64 {
Arm64.OpInfo op_info = (Arm64.OpInfo) ins.op_info;
if (op_info.cc != Arm64.ARM64_CC_AL && op_info.cc != Arm64.ARM64_CC_INVALID){
System.out.printf("\tCode condition: %d\n", op_info.cc);
}
if (op_info.update_flags) {
System.out.println("\tUpdate-flags: True");
}
if (op_info.writeback) {
System.out.println("\tWriteback: True");
}
if (op_info.op != null) {
System.out.printf("\top_count: %d\n", op_info.op.length);
for (int c=1; c<op_info.op.length+1; c++) {
Arm64.Operand i = (Arm64.Operand) op_info.op[c-1];
for (int c=0; c<op_info.op.length; c++) {
Arm64.Operand i = (Arm64.Operand) op_info.op[c];
String imm = hex(i.value.imm);
if (i.type == Arm64.ARM64_OP_REG)
System.out.printf("\t\toperands[%d].type: REG = %s\n", c, cs.reg_name(i.value.reg));
if (i.type == Arm64.ARM64_OP_IMM)
System.out.printf("\t\toperands[%d].type: IMM = %s\n", c, imm);
System.out.printf("\t\toperands[%d].type: IMM = 0x%x\n", c, i.value.imm);
if (i.type == Arm64.ARM64_OP_CIMM)
System.out.printf("\t\toperands[%d].type: C-IMM = %s\n", c, imm);
System.out.printf("\t\toperands[%d].type: C-IMM = %d\n", c, i.value.imm);
if (i.type == Arm64.ARM64_OP_FP)
System.out.printf("\t\toperands[%d].type: FP = %f\n", c, i.value.fp);
if (i.type == Arm64.ARM64_OP_MEM) {
@ -69,7 +60,7 @@ public class TestArm64 {
if (index != null)
System.out.printf("\t\t\toperands[%d].mem.index: REG = %s\n", c, index);
if (i.value.mem.disp != 0)
System.out.printf("\t\t\toperands[%d].mem.disp: %s\n", c, hex(i.value.mem.disp));
System.out.printf("\t\t\toperands[%d].mem.disp: 0x%x\n", c, i.value.mem.disp);
}
if (i.shift.type != Arm64.ARM64_SFT_INVALID && i.shift.value > 0)
System.out.printf("\t\t\tShift: type = %d, value = %d\n", i.shift.type, i.shift.value);
@ -77,6 +68,16 @@ public class TestArm64 {
System.out.printf("\t\t\tExt: %d\n", i.ext);
}
}
if (op_info.writeback)
System.out.println("\tWrite-back: True");
if (op_info.update_flags)
System.out.println("\tUpdate-flags: True");
if (op_info.cc != Arm64.ARM64_CC_AL && op_info.cc != Arm64.ARM64_CC_INVALID)
System.out.printf("\tCode condition: %d\n", op_info.cc);
}
public static void main(String argv[]) {
@ -87,17 +88,20 @@ public class TestArm64 {
for (int i=0; i<all_tests.length; i++) {
Test.platform test = all_tests[i];
System.out.println(new String(new char[30]).replace("\0", "*"));
System.out.println(new String(new char[16]).replace("\0", "*"));
System.out.println("Platform: " + test.comment);
System.out.println("Code: " + Test.stringToHex(test.code));
System.out.println("Disasm:");
cs = new Capstone(test.arch, test.mode);
Capstone.cs_insn[] all_ins = cs.disasm(test.code, 0x1000);
Capstone.cs_insn[] all_ins = cs.disasm(test.code, 0x2c);
for (int j = 0; j < all_ins.length; j++) {
print_ins_detail(all_ins[j]);
System.out.println();
}
System.out.printf("0x%x: \n\n", all_ins[all_ins.length-1].address + all_ins[all_ins.length-1].size);
}
}

14
bindings/java/TestMips.java
View File

@ -5,6 +5,9 @@ import com.sun.jna.Native;
import com.sun.jna.Memory;
import com.sun.jna.Pointer;
import capstone.Capstone;
import capstone.Mips;
public class TestMips {
static byte[] hexString2Byte(String s) {
@ -38,13 +41,13 @@ public class TestMips {
if (op_info.op != null) {
System.out.printf("\top_count: %d\n", op_info.op.length);
for (int c=1; c<op_info.op.length+1; c++) {
Mips.Operand i = (Mips.Operand) op_info.op[c-1];
for (int c=0; c<op_info.op.length; c++) {
Mips.Operand i = (Mips.Operand) op_info.op[c];
String imm = hex(i.value.imm);
if (i.type == Mips.MIPS_OP_REG)
System.out.printf("\t\toperands[%d].type: REG = %s\n", c, cs.reg_name(i.value.reg));
if (i.type == Mips.MIPS_OP_IMM)
System.out.printf("\t\toperands[%d].type: IMM = %s\n", c, imm);
System.out.printf("\t\toperands[%d].type: IMM = 0x%x\n", c, i.value.imm);
if (i.type == Mips.MIPS_OP_MEM) {
System.out.printf("\t\toperands[%d].type: MEM\n",c);
String base = cs.reg_name(i.value.mem.base);
@ -66,8 +69,9 @@ public class TestMips {
for (int i=0; i<all_tests.length; i++) {
Test.platform test = all_tests[i];
System.out.println(new String(new char[30]).replace("\0", "*"));
System.out.println(new String(new char[16]).replace("\0", "*"));
System.out.println("Platform: " + test.comment);
System.out.println("Code: " + Test.stringToHex(test.code));
System.out.println("Disasm:");
cs = new Capstone(test.arch, test.mode);
@ -77,6 +81,8 @@ public class TestMips {
print_ins_detail(all_ins[j]);
System.out.println();
}
System.out.printf("0x%x:\n\n", all_ins[all_ins.length-1].address + all_ins[all_ins.length-1].size);
}
}

34
bindings/java/TestX86.java
View File

@ -5,6 +5,9 @@ import com.sun.jna.Native;
import com.sun.jna.Memory;
import com.sun.jna.Pointer;
import capstone.Capstone;
import capstone.X86;
public class TestX86 {
static byte[] hexString2Byte(String s) {
@ -18,9 +21,9 @@ public class TestX86 {
return data;
}
static final String X86_CODE16 = "8d4c320801d881c6341200000523010000368b84912301000041a113486d3a";
static final String X86_CODE32 = "8d4c320801d881c6341200000523010000368b84912301000041a113486d3a8d0534120000";
static final String X86_CODE64 = "55488b05b8130000";
static final String X86_CODE16 = "8d4c320801d881c6341200000523010000368b849123010000418d8439896700008d8789670000b4c6";
static final String X86_CODE32 = "8d4c320801d881c6341200000523010000368b849123010000418d8439896700008d8789670000b4c6";
public static Capstone cs;
@ -60,31 +63,35 @@ public class TestX86 {
System.out.printf("\tmodrm: 0x%x\n", op_info.modrm);
// print displacement value
System.out.printf("\tdisp: 0x%s\n", hex(op_info.disp));
System.out.printf("\tdisp: 0x%x\n", op_info.disp);
// SIB is not available in 16-bit mode
if ( (cs.mode & Capstone.CS_MODE_16) == 0)
if ( (cs.mode & Capstone.CS_MODE_16) == 0) {
// print SIB byte
System.out.printf("\tsib: 0x%x\n", op_info.sib);
if (op_info.sib != 0)
System.out.printf("\tsib_index: %s, sib_scale: %d, sib_base: %s\n",
cs.reg_name(op_info.sib_index), op_info.sib_scale, cs.reg_name(op_info.sib_base));
}
int count = ins.op_count(X86.X86_OP_IMM);
if (count > 0) {
System.out.printf("\timm_count: %d\n", count);
for (int i=0; i<count; i++) {
int index = ins.op_index(X86.X86_OP_IMM, i + 1);
System.out.printf("\t\timms[%d] = 0x%x\n", i+1, (op_info.op[index].value.imm));
System.out.printf("\t\timms[%d]: 0x%x\n", i+1, (op_info.op[index].value.imm));
}
}
if (op_info.op != null) {
System.out.printf("\top_count: %d\n", op_info.op.length);
for (int c=1; c<op_info.op.length+1; c++) {
X86.Operand i = (X86.Operand) op_info.op[c-1];
for (int c=0; c<op_info.op.length; c++) {
X86.Operand i = (X86.Operand) op_info.op[c];
String imm = hex(i.value.imm);
if (i.type == X86.X86_OP_REG)
System.out.printf("\t\toperands[%d].type: REG = %s\n", c, cs.reg_name(i.value.reg));
if (i.type == X86.X86_OP_IMM)
System.out.printf("\t\toperands[%d].type: IMM = %s\n", c, imm);
System.out.printf("\t\toperands[%d].type: IMM = 0x%x\n", c, i.value.imm);
if (i.type == X86.X86_OP_FP)
System.out.printf("\t\toperands[%d].type: FP = %f\n", c, i.value.fp);
if (i.type == X86.X86_OP_MEM) {
@ -96,9 +103,9 @@ public class TestX86 {
if (index != null)
System.out.printf("\t\t\toperands[%d].mem.index: REG = %s\n", c, index);
if (i.value.mem.scale != 1)
System.out.printf("\t\t\toperands[%d].mem.scale: 0x%s\n", c, hex(i.value.mem.scale));
System.out.printf("\t\t\toperands[%d].mem.scale: %d\n", c, i.value.mem.scale);
if (i.value.mem.disp != 0)
System.out.printf("\t\t\toperands[%d].mem.disp: 0x%s\n", c, hex(i.value.mem.disp));
System.out.printf("\t\t\toperands[%d].mem.disp: 0x%x\n", c, i.value.mem.disp);
}
}
}
@ -108,15 +115,16 @@ public class TestX86 {
final Test.platform[] all_tests = {
new Test.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_16, hexString2Byte(X86_CODE16), "X86 16bit (Intel syntax)"),
new Test.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_32 + Capstone.CS_MODE_SYNTAX_ATT, hexString2Byte(X86_CODE32), "X86 32bit (ATT syntax)"),
new Test.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_32 + Capstone.CS_MODE_SYNTAX_ATT, hexString2Byte(X86_CODE32), "X86 32 (AT&T syntax)"),
new Test.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_32, hexString2Byte(X86_CODE32), "X86 32 (Intel syntax)"),
new Test.platform(Capstone.CS_ARCH_X86, Capstone.CS_MODE_64, hexString2Byte(X86_CODE64), "X86 64 (Intel syntax)"),
};
for (int i=0; i<all_tests.length; i++) {
Test.platform test = all_tests[i];
System.out.println(new String(new char[30]).replace("\0", "*"));
System.out.println(new String(new char[16]).replace("\0", "*"));
System.out.println("Platform: " + test.comment);
System.out.println("Code: " + Test.stringToHex(test.code));
System.out.println("Disasm:");
cs = new Capstone(test.arch, test.mode);
@ -126,6 +134,8 @@ public class TestX86 {
print_ins_detail(all_ins[j]);
System.out.println();
}
System.out.printf("0x%x:\n\n", all_ins[all_ins.length-1].address + all_ins[all_ins.length-1].size);
}
}

41
bindings/java/Arm.java → bindings/java/capstone/Arm.java
View File

@ -1,6 +1,8 @@
// Capstone Java binding
// By Nguyen Anh Quynh & Dang Hoang Vu, 2013
package capstone;
import com.sun.jna.Structure;
import com.sun.jna.Pointer;
import com.sun.jna.Union;
@ -9,7 +11,7 @@ import com.sun.jna.NativeLong;
import java.util.List;
import java.util.Arrays;
class Arm {
public class Arm {
// ARM operand shift type
public static final int ARM_SFT_INVALID = 0;
@ -91,7 +93,7 @@ class Arm {
public OpValue value;
public void read() {
super.read();
readField("type");
if (type == ARM_OP_MEM)
value.setType(MemType.class);
if (type == ARM_OP_FP)
@ -100,7 +102,10 @@ class Arm {
value.setType(Long.TYPE);
if (type == ARM_OP_REG)
value.setType(Integer.TYPE);
if (type == ARM_OP_INVALID)
return;
readField("value");
readField("shift");
}
@Override
@ -109,13 +114,37 @@ class Arm {
}
}
public static class UnionOpInfo extends Structure {
public static class UnionOpInfo extends Capstone.UnionOpInfo {
public int cc;
public byte _update_flags;
public byte _writeback;
public byte op_count;
public Operand [] op = new Operand[32];
public Operand [] op;
public UnionOpInfo(){
op = new Operand[32];
}
public UnionOpInfo(Pointer p){
op = new Operand[32];
useMemory(p);
read();
}
public static int getSize() {
UnionOpInfo x = new UnionOpInfo();
return x.size();
}
public void read() {
readField("cc");
readField("_update_flags");
readField("_writeback");
readField("op_count");
op = new Operand[op_count];
readField("op");
}
@Override
public List getFieldOrder() {
@ -134,9 +163,7 @@ class Arm {
update_flags = (op_info._update_flags > 0);
writeback = (op_info._writeback > 0);
if (op_info.op_count == 0) return;
op = new Operand[op_info.op_count];
for (int i=0; i<op_info.op_count; i++)
op[i] = op_info.op[i];
op = op_info.op;
}
}

26
bindings/java/Arm64.java → bindings/java/capstone/Arm64.java
View File

@ -1,6 +1,8 @@
// Capstone Java binding
// By Nguyen Anh Quynh & Dang Hoang Vu, 2013
package capstone;
import com.sun.jna.Structure;
import com.sun.jna.Pointer;
import com.sun.jna.Union;
@ -9,7 +11,7 @@ import com.sun.jna.NativeLong;
import java.util.List;
import java.util.Arrays;
class Arm64 {
public class Arm64 {
// ARM64 operand shift type
public static final int ARM64_SFT_INVALID = 0;
@ -97,7 +99,7 @@ class Arm64 {
public OpValue value;
public void read() {
super.read();
readField("type");
if (type == ARM64_OP_MEM)
value.setType(MemType.class);
if (type == ARM64_OP_FP)
@ -109,6 +111,8 @@ class Arm64 {
if (type == ARM64_OP_INVALID)
return;
readField("value");
readField("ext");
readField("shift");
}
@Override
@ -117,13 +121,27 @@ class Arm64 {
}
}
public static class UnionOpInfo extends Structure {
public static class UnionOpInfo extends Capstone.UnionOpInfo {
public int cc;
public byte _update_flags;
public byte _writeback;
public byte op_count;
public Operand [] op = new Operand[32];
public Operand [] op;
public UnionOpInfo() {
op = new Operand[32];
}
public UnionOpInfo(Pointer p) {
op = new Operand[32];
useMemory(p);
read();
}
public static int getSize() {
return (new UnionOpInfo()).size();
}
public void read() {
readField("cc");

132
bindings/java/CS.java → bindings/java/capstone/Capstone.java
View File

@ -1,6 +1,8 @@
// Capstone Java binding
// By Nguyen Anh Quynh & Dang Hoang Vu, 2013
package capstone;
import com.sun.jna.Library;
import com.sun.jna.Native;
import com.sun.jna.Structure;
@ -8,27 +10,26 @@ import com.sun.jna.Union;
import com.sun.jna.ptr.LongByReference;
import com.sun.jna.Pointer;
import com.sun.jna.ptr.PointerByReference;
import com.sun.jna.ptr.IntByReference;
import java.util.List;
import java.util.Arrays;
import java.lang.RuntimeException;
import java.lang.Math;
class Capstone {
public class Capstone {
public int arch;
public int mode;
public static abstract class OpInfo {
protected static abstract class OpInfo {}
protected static abstract class UnionOpInfo extends Structure {}
protected static int max(int a, int b, int c, int d) {
return Math.max(Math.max(Math.max(a,b),c),d);
}
public static class PrivateOpInfo extends Union {
public X86.UnionOpInfo x86;
public Arm64.UnionOpInfo arm64;
public Arm.UnionOpInfo arm;
public Mips.UnionOpInfo mips;
}
public static class _cs_insn extends Structure implements Structure.ByReference {
protected static class _cs_insn extends Structure {
public int id;
public long address;
public short size;
@ -38,30 +39,38 @@ class Capstone {
public int[] regs_write = new int[32];
public int[] groups = new int[8];
public PrivateOpInfo _op_info;
public _cs_insn(Pointer p) { super(p); }
public _cs_insn(Pointer p) {
mnemonic = new byte[32];
operands = new byte[96];
regs_read = new int[32];
regs_write = new int[32];
groups = new int[8];
useMemory(p);
read();
}
@Override
public List getFieldOrder() {
return Arrays.asList("id", "address", "size", "mnemonic", "operands", "regs_read", "regs_write", "groups", "_op_info");
return Arrays.asList("id", "address", "size", "mnemonic", "operands", "regs_read", "regs_write", "groups");
}
}
public static class cs_insn {
OpInfo op_info;
Pointer ptr_origin;
long csh;
CS cs;
public OpInfo op_info;
public Pointer ptr_origin;
public long csh;
int id;
long address;
short size;
String mnemonic;
String operands;
int[] regs_read;
int[] regs_write;
int[] groups;
public int id;
public long address;
public short size;
public String mnemonic;
public String operands;
public int[] regs_read;
public int[] regs_write;
public int[] groups;
private CS cs;
private int _size;
public cs_insn (_cs_insn struct, Pointer _ptr_origin, long _csh, CS _cs, OpInfo _op_info) {
id = struct.id;
@ -77,6 +86,11 @@ class Capstone {
op_info = _op_info;
csh = _csh;
cs = _cs;
_size = struct.size() + max( Arm.UnionOpInfo.getSize(), Arm64.UnionOpInfo.getSize(), Mips.UnionOpInfo.getSize(), X86.UnionOpInfo.getSize() );
}
protected int size() {
return _size;
}
public int op_count(int type) {
@ -86,33 +100,55 @@ class Capstone {
public int op_index(int type, int index) {
return cs.cs_op_index(csh, ptr_origin, type, index);
}
public boolean reg_read(int reg_id) {
return cs.cs_reg_read(csh, ptr_origin, reg_id) != 0;
}
public boolean reg_write(int reg_id) {
return cs.cs_reg_write(csh, ptr_origin, reg_id) != 0;
}
public int errno() {
return cs.cs_errno(csh);
}
public String reg_name(int reg_id) {
return cs.cs_reg_name(csh, reg_id);
}
public String insn_name() {
return cs.cs_insn_name(csh, id);
}
public boolean group(int gid) {
return cs.cs_insn_group(csh, ptr_origin, gid) != 0;
}
}
private cs_insn fromPointer(Pointer pointer)
{
_cs_insn insn = new _cs_insn(pointer);
OpInfo op_info = null;
UnionOpInfo _op_info = null;
switch (this.arch) {
case CS_ARCH_ARM:
insn._op_info.setType(Arm.UnionOpInfo.class);
insn.read();
op_info = new Arm.OpInfo(insn._op_info.arm);
_op_info = new Arm.UnionOpInfo(pointer.share(insn.size()));
op_info = new Arm.OpInfo((Arm.UnionOpInfo) _op_info);
break;
case CS_ARCH_ARM64:
insn._op_info.setType(Arm64.UnionOpInfo.class);
insn.read();
op_info = new Arm64.OpInfo(insn._op_info.arm64);
_op_info = new Arm64.UnionOpInfo(pointer.share(insn.size()));
op_info = new Arm64.OpInfo((Arm64.UnionOpInfo) _op_info);
break;
case CS_ARCH_MIPS:
insn._op_info.setType(Mips.UnionOpInfo.class);
insn.read();
op_info = new Mips.OpInfo(insn._op_info.mips);
_op_info = new Mips.UnionOpInfo(pointer.share(insn.size()));
op_info = new Mips.OpInfo((Mips.UnionOpInfo) _op_info);
break;
case CS_ARCH_X86:
insn._op_info.setType(X86.UnionOpInfo.class);
insn.read();
op_info = new X86.OpInfo(insn._op_info.x86);
_op_info = new X86.UnionOpInfo(pointer.share(insn.size()));
op_info = new X86.OpInfo((X86.UnionOpInfo) _op_info);
break;
default:
}
@ -126,7 +162,7 @@ class Capstone {
for (int i = 0; i < numberResults; i++) {
arr[i] = fromPointer(pointer.share(offset));
offset += 1728; // sizeof(cs_insn);
offset += arr[i].size();
}
return arr;
@ -141,6 +177,13 @@ class Capstone {
public String cs_reg_name(long csh, int id);
public int cs_op_count(long csh, Pointer insn, int type);
public int cs_op_index(long csh, Pointer insn, int type, int index);
public String cs_insn_name(long csh, int id);
public byte cs_insn_group(long csh, Pointer insn, int id);
public byte cs_reg_read(long csh, Pointer insn, int id);
public byte cs_reg_write(long csh, Pointer insn, int id);
public void cs_version(IntByReference major, IntByReference minor);
public int cs_errno(long csh);
}
public static final int CS_ARCH_ARM = 0;
@ -171,7 +214,7 @@ class Capstone {
private PointerByReference insnRef;
private CS cs;
Capstone(int arch, int mode)
public Capstone(int arch, int mode)
{
this.arch = arch;
this.mode = mode;
@ -187,18 +230,15 @@ class Capstone {
return cs.cs_reg_name(csh, reg);
}
protected void finalize()
{
protected void finalize() {
cs.cs_close(csh);
}
cs_insn[] disasm(byte[] code, long address)
{
public cs_insn[] disasm(byte[] code, long address) {
return disasm(code, address, 0);
}
cs_insn[] disasm(byte[] code, long address, long count)
{
public cs_insn[] disasm(byte[] code, long address, long count) {
insnRef = new PointerByReference();
long c = cs.cs_disasm_dyn(csh, code, code.length, address, count, insnRef);

22
bindings/java/Mips.java → bindings/java/capstone/Mips.java
View File

@ -1,6 +1,8 @@
// Capstone Java binding
// By Nguyen Anh Quynh & Dang Hoang Vu, 2013
package capstone;
import com.sun.jna.Structure;
import com.sun.jna.Pointer;
import com.sun.jna.Union;
@ -9,7 +11,7 @@ import com.sun.jna.NativeLong;
import java.util.List;
import java.util.Arrays;
class Mips {
public class Mips {
// Operand type
public static final int MIPS_OP_INVALID = 0; // Uninitialized.
@ -60,9 +62,23 @@ class Mips {
}
}
public static class UnionOpInfo extends Structure {
public static class UnionOpInfo extends Capstone.UnionOpInfo {
public short op_count;
public Operand [] op = new Operand[8];
public Operand [] op;
public UnionOpInfo() {
op = new Operand[8];
}
public UnionOpInfo(Pointer p) {
op = new Operand[8];
useMemory(p);
read();
}
public static int getSize() {
return (new UnionOpInfo()).size();
}
public void read() {
readField("op_count");

32
bindings/java/X86.java → bindings/java/capstone/X86.java
View File

@ -1,6 +1,8 @@
// Capstone Java binding
// By Nguyen Anh Quynh & Dang Hoang Vu, 2013
package capstone;
import com.sun.jna.Structure;
import com.sun.jna.Pointer;
import com.sun.jna.Union;
@ -9,7 +11,7 @@ import com.sun.jna.NativeLong;
import java.util.List;
import java.util.Arrays;
class X86 {
public class X86 {
// Operand type
public static final int X86_OP_INVALID = 0; // Uninitialized.
@ -67,10 +69,10 @@ class X86 {
}
}
public static class UnionOpInfo extends Structure {
public byte [] prefix = new byte[5];
public static class UnionOpInfo extends Capstone.UnionOpInfo {
public byte [] prefix;
public int segment;
public byte [] opcode = new byte[3];
public byte [] opcode;
public byte op_size;
public byte addr_size;
public byte disp_size;
@ -84,7 +86,25 @@ class X86 {
public int op_count;
public Operand [] op = new Operand[8];
public Operand [] op;
public UnionOpInfo() {
op = new Operand[8];
opcode = new byte[3];
prefix = new byte[5];
}
public UnionOpInfo(Pointer p) {
op = new Operand[8];
opcode = new byte[3];
prefix = new byte[5];
useMemory(p);
read();
}
public static int getSize() {
return (new UnionOpInfo()).size();
}
@Override
public List getFieldOrder() {
@ -108,7 +128,7 @@ class X86 {
public byte sib_scale;
public int sib_base;
Operand[] op;
public Operand[] op;
public OpInfo(UnionOpInfo e) {
prefix = e.prefix;

8
bindings/java/run.sh
View File

@ -2,8 +2,12 @@
JNA=/usr/share/java/jna.jar
if [ ! -f ${JNA} ]; then
echo "JNA @ ${JNA} does not exist, edit this file with the correct path";
exit
if [ ! -f /usr/share/java/jna/jna.jar ]; then
echo "*** Unable to find jna.jar *** ";
exit;
else
JNA=/usr/share/java/jna/jna.jar;
fi
fi
case "$1" in

2
bindings/python/capstone/capstone.py
View File

@ -203,7 +203,7 @@ class cs_insn:
elif arch == CS_ARCH_X86:
(self.prefix, self.segment, self.opcode, self.op_size, self.addr_size, \
self.disp_size, self.imm_size, self.modrm, self.sib, self.disp, \
self.sib_index, self.sib_scale, self.operands) = x86.get_arch_info(all_info.arch.x86)
self.sib_index, self.sib_scale, self.sib_base, self.operands) = x86.get_arch_info(all_info.arch.x86)
elif arch == CS_ARCH_MIPS:
self.operands = mips.get_arch_info(all_info.arch.mips)

2
bindings/python/capstone/x86.py
View File

@ -57,7 +57,7 @@ def get_arch_info(a):
if i.type == 0:
break
op_info.append(i)
return (a.prefix, a.segment, a.opcode, a.op_size, a.addr_size, a.disp_size, a.imm_size, a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, op_info)
return (a.prefix, a.segment, a.opcode, a.op_size, a.addr_size, a.disp_size, a.imm_size, a.modrm, a.sib, a.disp, a.sib_index, a.sib_scale, a.sib_base, op_info)
# all Intel reigsters
X86_REG_INVALID = 0

22
bindings/python/test.py
View File

@ -10,7 +10,7 @@ X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00"
ARM_CODE = "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
ARM_CODE2 = "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
THUMB_CODE = "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88"
THUMB_CODE2 = "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
MIPS_CODE = "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
MIPS_CODE2 = "\x56\x34\x21\x34\xc2\x17\x01\x00"
ARM64_CODE = "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
@ -21,18 +21,17 @@ all_tests = (
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM"),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
(CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON"),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB"),
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2"),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
(CS_ARCH_MIPS, CS_MODE_32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
(CS_ARCH_MIPS, CS_MODE_64+ CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
)
def to_hex(s):
# print " ".join("{0:x}".format(ord(c)) for c in s) # <-- Python 3 is OK
return ' '.join(x.encode('hex') for x in s) # <-- fails for Python 3
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
### Test cs_disasm_quick()
@ -50,15 +49,18 @@ def test_cs_disasm_quick():
### Test class cs
def test_class():
for (arch, mode, code, comment) in all_tests:
print('*' * 40)
print('*' * 16)
print("Platform: %s" %comment)
print("Disasm:"),
print to_hex(code)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = cs(arch, mode)
for insn in md.disasm(code, 0x1000):
all_ins = list(md.disasm(code, 0x1000))
for insn in all_ins:
print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
print("0x%x:" % (all_ins[-1].address + all_ins[-1].size))
print
except:
print("ERROR: Arch or mode unsupported!")

40
bindings/python/test_arm.py
View File

@ -17,6 +17,15 @@ all_tests = (
(CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2"),
)
def to_hex(s):
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
def to_x(s):
from struct import pack
if not s: return '0'
x = pack(">q", s).encode('hex')
while x[0] == '0': x = x[1:]
return x
### Test class cs
def test_class():
@ -24,24 +33,14 @@ def test_class():
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
print("\tCode condition: %u" %insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")
if insn.writeback:
print("\tWriteback: True")
if len(insn.operands) > 0:
print("\top_count: %u" %len(insn.operands))
c = 0
for i in insn.operands:
c += 1
if i.type == ARM_OP_REG:
print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
if i.type == ARM_OP_IMM:
print("\t\toperands[%u].type: IMM = %x" %(c, i.value.imm))
print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
if i.type == ARM_OP_PIMM:
print("\t\toperands[%u].type: P-IMM = %u" %(c, i.value.imm))
if i.type == ARM_OP_CIMM:
@ -60,24 +59,35 @@ def test_class():
print("\t\t\toperands[%u].mem.scale: %u" \
%(c, i.value.mem.scale))
if i.value.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: %x" \
%(c, i.value.mem.disp))
print("\t\t\toperands[%u].mem.disp: 0x%s" \
%(c, to_x(i.value.mem.disp)))
if i.shift.type != ARM_SFT_INVALID and i.shift.value:
print("\t\t\tShift: type = %u, value = %u\n" \
%(i.shift.type, i.shift.value))
c+=1
if insn.update_flags:
print("\tUpdate-flags: True")
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [ARM_CC_AL, ARM_CC_INVALID]:
print("\tCode condition: %u" %insn.cc)
for (arch, mode, code, comment) in all_tests:
print("*" * 30)
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = cs(arch, mode)
last = None
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
last = insn
print
print "0x%x:\n" % (last.address + last.size)
except:
print("ERROR: Arch or mode unsupported!")

42
bindings/python/test_arm64.py
View File

@ -11,6 +11,15 @@ all_tests = (
(CS_ARCH_ARM64, CS_MODE_ARM, ARM64_CODE, "ARM-64"),
)
def to_hex(s):
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
def to_x(s):
from struct import pack
if not s: return '0'
x = pack(">q", s).encode('hex')
while x[0] == '0': x = x[1:]
return x
### Test class cs
def test_class():
@ -18,24 +27,15 @@ def test_class():
# print address, mnemonic and operands
print("0x%x:\t%s\t%s" %(insn.address, insn.mnemonic, insn.op_str))
if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
print("\tCode condition: %u" %insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")
if insn.writeback:
print("\tWrite-back: True")
if len(insn.operands) > 0:
print("\top_count: %u" %len(insn.operands))
c = 0
c = -1
for i in insn.operands:
c += 1
if i.type == ARM64_OP_REG:
print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
if i.type == ARM64_OP_IMM:
print("\t\toperands[%u].type: IMM = %x" %(c, i.value.imm))
print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
if i.type == ARM64_OP_CIMM:
print("\t\toperands[%u].type: C-IMM = %u" %(c, i.value.imm))
if i.type == ARM64_OP_FP:
@ -49,8 +49,8 @@ def test_class():
print("\t\t\toperands[%u].mem.index: REG = %s" \
%(c, insn.reg_name(i.value.mem.index)))
if i.value.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: %x" \
%(c, i.value.mem.disp))
print("\t\t\toperands[%u].mem.disp: 0x%s" \
%(c, to_x(i.value.mem.disp)))
if i.shift.type != ARM64_SFT_INVALID and i.shift.value:
print("\t\t\tShift: type = %u, value = %u" \
@ -59,17 +59,27 @@ def test_class():
if i.ext != ARM64_EXT_INVALID:
print("\t\t\tExt: %u" %i.ext)
if insn.writeback:
print("\tWrite-back: True")
if not insn.cc in [ARM64_CC_AL, ARM64_CC_INVALID]:
print("\tCode condition: %u" %insn.cc)
if insn.update_flags:
print("\tUpdate-flags: True")
for (arch, mode, code, comment) in all_tests:
print("*" * 30)
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = cs(arch, mode)
for insn in md.disasm(code, 0x1000):
last = None
for insn in md.disasm(code, 0x2c):
print_insn_detail(insn)
last = insn
print
print "0x%x:\n" % (last.address + last.size)
except:
print("ERROR: Arch or mode unsupported!")

26
bindings/python/test_mips.py
View File

@ -13,6 +13,15 @@ all_tests = (
(CS_ARCH_MIPS, CS_MODE_64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
)
def to_hex(s):
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
def to_x(s):
from struct import pack
if not s: return '0'
x = pack(">q", s).encode('hex')
while x[0] == '0': x = x[1:]
return x
### Test class cs
def test_class():
@ -22,33 +31,38 @@ def test_class():
if len(insn.operands) > 0:
print("\top_count: %u" %len(insn.operands))
c = 0
c = -1
for i in insn.operands:
c += 1
if i.type == MIPS_OP_REG:
print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
if i.type == MIPS_OP_IMM:
print("\t\toperands[%u].type: IMM = %x" %(c, i.value.imm))
print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
if i.type == MIPS_OP_MEM:
print("\t\toperands[%u].type: MEM" %c)
if i.value.mem.base != 0:
print("\t\t\toperands[%u].mem.base: REG = %s" \
%(c, insn.reg_name(i.value.mem.base)))
if i.value.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: %x" \
%(c, i.value.mem.disp))
print("\t\t\toperands[%u].mem.disp: 0x%s" \
%(c, to_x(i.value.mem.disp)))
for (arch, mode, code, comment) in all_tests:
print("*" * 30)
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = cs(arch, mode)
last = None
for insn in md.disasm(code, 0x1000):
print_insn_detail(insn)
last = insn
print
print "0x%x:\n" %(insn.address + insn.size)
except:
print("ERROR: Arch or mode unsupported!")

54
bindings/python/test_x86.py
View File

@ -5,18 +5,33 @@
from capstone import *
from capstone.x86 import *
X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\xa1\x13\x48\x6d\x3a"
X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\xa1\x13\x48\x6d\x3a"
X86_CODE32 += "\x8d\x05\x34\x12\x00\x00"
X86_CODE64 = "\x55\x48\x8b\x05\xb8\x13\x00\x00"
X86_CODE16 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
X86_CODE32 = "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6"
all_tests = (
(CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)"),
(CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32bit (ATT syntax)"),
(CS_ARCH_X86, CS_MODE_32 + CS_MODE_SYNTAX_ATT, X86_CODE32, "X86 32 (AT&T syntax)"),
(CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)"),
(CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)"),
)
def to_hex(s):
return " ".join("0x" + "{0:x}".format(ord(c)).zfill(2) for c in s) # <-- Python 3 is OK
def to_x(s):
from struct import pack
if not s: return '0'
x = pack(">q", s).encode('hex')
while x[0] == '0': x = x[1:]
return x
def to_x_32(s):
from struct import pack
if not s: return '0'
x = pack(">i", s).encode('hex')
while x[0] == '0': x = x[1:]
return x
### Test class cs
def test_class():
@ -48,29 +63,31 @@ def test_class():
print("\tmodrm: 0x%x" %(insn.modrm))
# print displacement value
print("\tdisp: 0x%x" %(insn.disp))
print("\tdisp: 0x%s" %to_x_32(insn.disp))
# SIB is not available in 16-bit mode
if (mode & CS_MODE_16 == 0):
# print SIB byte
print("\tsib: 0x%x" %(insn.sib))
if (insn.sib):
print("\tsib_index: %s, sib_scale: %d, sib_base: %s" % (insn.reg_name(insn.sib_index), insn.sib_scale, insn.reg_name(insn.sib_base)))
count = insn.op_count(X86_OP_IMM)
if count > 0:
print("\timm_count: %u" %count)
for i in xrange(count):
index = insn.op_index(X86_OP_IMM, i + 1)
print("\t\timms[%u] = 0x%x" %(i+1, (insn.operands[index].value.imm)))
print("\t\timms[%u]: 0x%s" %(i+1, to_x(insn.operands[index].value.imm)))
if len(insn.operands) > 0:
print("\top_count: %u" %len(insn.operands))
c = 0
c = -1
for i in insn.operands:
c += 1
if i.type == X86_OP_REG:
print("\t\toperands[%u].type: REG = %s" %(c, insn.reg_name(i.value.reg)))
if i.type == X86_OP_IMM:
print("\t\toperands[%u].type: IMM = 0x%x" %(c, i.value.imm))
print("\t\toperands[%u].type: IMM = 0x%s" %(c, to_x(i.value.imm)))
if i.type == X86_OP_FP:
print("\t\toperands[%u].type: FP = %f" %(c, i.value.fp))
if i.type == X86_OP_MEM:
@ -82,21 +99,22 @@ def test_class():
if i.value.mem.scale != 1:
print("\t\t\toperands[%u].mem.scale: %u" %(c, i.value.mem.scale))
if i.value.mem.disp != 0:
print("\t\t\toperands[%u].mem.disp: 0x%x" %(c, i.value.mem.disp))
print("\t\t\toperands[%u].mem.disp: 0x%s" %(c, to_x(i.value.mem.disp)))
for (arch, mode, code, comment) in all_tests:
print("*" * 30)
print("*" * 16)
print("Platform: %s" %comment)
print("Code: %s" % to_hex(code))
print("Disasm:")
try:
md = cs(arch, mode)
for insn in md.disasm(code, 0x1000):
print_insn_detail(mode, insn)
print
except:
print("ERROR: Arch or mode unsupported!")
md = cs(arch, mode)
last = None
for insn in md.disasm(code, 0x1000):
print_insn_detail(mode, insn)
last = insn
print
print ("0x%x:\n" % (last.address + last.size))
test_class()