arm64: update core engine
This commit is contained in:
Nguyen Anh Quynh
parent
dcde7e7e70
commit
731bf2a714
2
Makefile
2
Makefile
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@ -20,10 +20,10 @@ INSTALL_LIBRARY ?= install -m0755
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LIBNAME = capstone
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LIBOBJ =
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LIBOBJ += cs.o utils.o SStream.o MCInstrDesc.o MCRegisterInfo.o
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LIBOBJ += arch/AArch64/AArch64BaseInfo.o arch/AArch64/AArch64Disassembler.o arch/AArch64/AArch64InstPrinter.o arch/AArch64/mapping.o
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LIBOBJ += arch/ARM/ARMDisassembler.o arch/ARM/ARMInstPrinter.o arch/ARM/mapping.o
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LIBOBJ += arch/X86/X86DisassemblerDecoder.o arch/X86/X86Disassembler.o arch/X86/X86IntelInstPrinter.o arch/X86/X86ATTInstPrinter.o arch/X86/mapping.o
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LIBOBJ += arch/Mips/MipsDisassembler.o arch/Mips/MipsInstPrinter.o arch/Mips/mapping.o
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LIBOBJ += arch/AArch64/AArch64BaseInfo.o arch/AArch64/AArch64Disassembler.o arch/AArch64/AArch64InstPrinter.o arch/AArch64/mapping.o
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LIBOBJ += MCInst.o
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EXT = so
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@ -217,6 +217,46 @@ typedef enum A64SE_ShiftExtSpecifiers {
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A64SE_SXTX
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} A64SE_ShiftExtSpecifiers;
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typedef enum A64Layout_VectorLayout {
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A64Layout_Invalid = -1,
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A64Layout_VL_8B,
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A64Layout_VL_4H,
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A64Layout_VL_2S,
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A64Layout_VL_1D,
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A64Layout_VL_16B,
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A64Layout_VL_8H,
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A64Layout_VL_4S,
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A64Layout_VL_2D,
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// Bare layout for the 128-bit vector
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// (only show ".b", ".h", ".s", ".d" without vector number)
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A64Layout_VL_B,
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A64Layout_VL_H,
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A64Layout_VL_S,
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A64Layout_VL_D
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} A64Layout_VectorLayout;
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inline static const char *
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A64VectorLayoutToString(A64Layout_VectorLayout Layout)
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{
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switch (Layout) {
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case A64Layout_VL_8B: return ".8b";
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case A64Layout_VL_4H: return ".4h";
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case A64Layout_VL_2S: return ".2s";
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case A64Layout_VL_1D: return ".1d";
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case A64Layout_VL_16B: return ".16b";
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case A64Layout_VL_8H: return ".8h";
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case A64Layout_VL_4S: return ".4s";
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case A64Layout_VL_2D: return ".2d";
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case A64Layout_VL_B: return ".b";
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case A64Layout_VL_H: return ".h";
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case A64Layout_VL_S: return ".s";
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case A64Layout_VL_D: return ".d";
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default: return NULL; // never reach
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}
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}
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enum SysRegROValues {
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A64SysReg_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
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A64SysReg_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
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@ -51,9 +51,39 @@ static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeFPR128RegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeFPR128LoRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeGPR64noxzrRegisterClass(MCInst *Inst,
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unsigned RegNo,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeQPairRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeDTripleRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeQTripleRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeDQuadRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeQQuadRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeAddrRegExtendOperand(MCInst *Inst,
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unsigned OptionHiS,
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uint64_t Address,
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@ -75,16 +105,28 @@ static DecodeStatus DecodeFPZeroOperand(MCInst *Inst,
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void *Decoder);
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static DecodeStatus DecodeShiftRightImm8(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeShiftRightImm16(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder);
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeShiftRightImm32(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder);
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeShiftRightImm64(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder);
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeShiftLeftImm8(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeShiftLeftImm16(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeShiftLeftImm32(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeShiftLeftImm64(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeMoveWideImmOperand(MCInst *Inst,
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unsigned FullImm,
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@ -147,12 +189,22 @@ static DecodeStatus DecodeMSROperand(MCInst *Inst,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeSingleIndexedInstruction(MCInst *Inst,
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unsigned Val,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeVLDSTPostInstruction(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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void *Decoder);
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static DecodeStatus DecodeSHLLInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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void *Decoder);
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static bool Check(DecodeStatus *Out, DecodeStatus In);
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@ -214,13 +266,24 @@ void AArch64_init(MCRegisterInfo *MRI)
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AArch64SubRegIdxRanges, AArch64RegEncodingTable);
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*/
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MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 228,
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/*
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RI->InitMCRegisterInfo(AArch64RegDesc, 420,
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RA, PC,
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AArch64MCRegisterClasses, 61,
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AArch64RegUnitRoots, 66,
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AArch64RegDiffLists,
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AArch64RegStrings,
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AArch64SubRegIdxLists, 53,
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AArch64SubRegIdxRanges, AArch64RegEncodingTable);
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*/
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MCRegisterInfo_InitMCRegisterInfo(MRI, AArch64RegDesc, 420,
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0, 0,
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AArch64MCRegisterClasses, 15,
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AArch64MCRegisterClasses, 61,
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0, 0,
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AArch64RegDiffLists,
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0,
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AArch64SubRegIdxLists, 6,
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AArch64SubRegIdxLists, 53,
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0);
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}
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@ -366,6 +429,16 @@ DecodeFPR64RegisterClass(MCInst *Inst, unsigned RegNo,
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return MCDisassembler_Success;
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}
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static DecodeStatus
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DecodeFPR64LoRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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if (RegNo > 15)
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return MCDisassembler_Fail;
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return DecodeFPR64RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus
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DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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@ -378,6 +451,89 @@ DecodeFPR128RegisterClass(MCInst *Inst, unsigned RegNo,
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return MCDisassembler_Success;
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}
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static DecodeStatus
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DecodeFPR128LoRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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if (RegNo > 15)
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return MCDisassembler_Fail;
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return DecodeFPR128RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPR64noxzrRegisterClass(MCInst *Inst,
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unsigned RegNo,
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uint64_t Address,
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void *Decoder)
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{
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if (RegNo > 30)
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return MCDisassembler_Fail;
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uint16_t Register = getReg(Decoder, AArch64_GPR64noxzrRegClassID, RegNo);
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MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeRegisterClassByID(MCInst *Inst, unsigned RegNo,
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unsigned RegID,
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void *Decoder)
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{
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if (RegNo > 31)
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return MCDisassembler_Fail;
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uint16_t Register = getReg(Decoder, RegID, RegNo);
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MCInst_addOperand(Inst, MCOperand_CreateReg(Register));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeDPairRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder)
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{
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return DecodeRegisterClassByID(Inst, RegNo, AArch64_DPairRegClassID,
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Decoder);
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}
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static DecodeStatus DecodeQPairRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder)
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{
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return DecodeRegisterClassByID(Inst, RegNo, AArch64_QPairRegClassID,
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Decoder);
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}
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static DecodeStatus DecodeDTripleRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address,
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void *Decoder)
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{
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return DecodeRegisterClassByID(Inst, RegNo, AArch64_DTripleRegClassID,
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Decoder);
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}
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static DecodeStatus DecodeQTripleRegisterClass(MCInst *Inst,
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unsigned RegNo, uint64_t Address,
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void *Decoder)
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{
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return DecodeRegisterClassByID(Inst, RegNo, AArch64_QTripleRegClassID,
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Decoder);
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}
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static DecodeStatus DecodeDQuadRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder)
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{
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return DecodeRegisterClassByID(Inst, RegNo, AArch64_DQuadRegClassID,
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Decoder);
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}
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static DecodeStatus DecodeQQuadRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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void *Decoder)
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{
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return DecodeRegisterClassByID(Inst, RegNo, AArch64_QQuadRegClassID,
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Decoder);
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}
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static DecodeStatus DecodeAddrRegExtendOperand(MCInst *Inst,
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unsigned OptionHiS,
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uint64_t Address,
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@ -456,6 +612,50 @@ static DecodeStatus DecodeShiftRightImm64(MCInst *Inst,
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeShiftLeftImm8(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder)
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{
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if (Val > 7)
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return MCDisassembler_Fail;
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MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeShiftLeftImm16(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder)
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{
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if (Val > 15)
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return MCDisassembler_Fail;
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MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeShiftLeftImm32(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder)
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{
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if (Val > 31)
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return MCDisassembler_Fail;
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MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeShiftLeftImm64(MCInst *Inst, unsigned Val,
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uint64_t Address,
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void *Decoder)
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{
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if (Val > 63)
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return MCDisassembler_Fail;
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MCInst_addOperand(Inst, MCOperand_CreateImm(Val));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeMoveWideImmOperand(MCInst *Inst,
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unsigned FullImm,
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uint64_t Address,
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@ -877,3 +1077,570 @@ DecodeNeonMovImmShiftOperand(MCInst *Inst, unsigned ShiftAmount,
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MCInst_addOperand(Inst, MCOperand_CreateImm(ShiftAmount));
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return MCDisassembler_Success;
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}
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// Decode post-index vector load/store instructions.
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// This is necessary as we need to decode Rm: if Rm == 0b11111, the last
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// operand is an immediate equal the the length of vector list in bytes,
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// or Rm is decoded to a GPR64noxzr register.
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static DecodeStatus DecodeVLDSTPostInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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void *Decoder)
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{
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unsigned Rt = fieldFromInstruction(Insn, 0, 5);
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unsigned Rn = fieldFromInstruction(Insn, 5, 5);
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unsigned Rm = fieldFromInstruction(Insn, 16, 5);
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unsigned Opcode = fieldFromInstruction(Insn, 12, 4);
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unsigned IsLoad = fieldFromInstruction(Insn, 22, 1);
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// 0 for 64bit vector list, 1 for 128bit vector list
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unsigned Is128BitVec = fieldFromInstruction(Insn, 30, 1);
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unsigned NumVecs;
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switch (Opcode) {
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default:
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// llvm_unreachable("Invalid opcode for post-index load/store instructions");
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case 0: // ld4/st4
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case 2: // ld1/st1 with 4 vectors
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NumVecs = 4; break;
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case 4: // ld3/st3
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case 6: // ld1/st1 with 3 vectors
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NumVecs = 3; break;
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case 7: // ld1/st1 with 1 vector
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NumVecs = 1; break;
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case 8: // ld2/st2
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case 10: // ld1/st1 with 2 vectors
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NumVecs = 2; break;
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}
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// Decode vector list of 1/2/3/4 vectors for load instructions.
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if (IsLoad) {
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switch (NumVecs) {
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case 1:
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Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
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: DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
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break;
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case 2:
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Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
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: DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
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break;
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case 3:
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Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
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: DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
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break;
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case 4:
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Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
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: DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
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break;
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}
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}
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// Decode write back register, which is equal to Rn.
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DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
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DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
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if (Rm == 31) // If Rm is 0x11111, add the vector list length in byte
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MCInst_addOperand(Inst, MCOperand_CreateImm(NumVecs * (Is128BitVec ? 16 : 8)));
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else // Decode Rm
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DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
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// Decode vector list of 1/2/3/4 vectors for load instructions.
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if (!IsLoad) {
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switch (NumVecs) {
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case 1:
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Is128BitVec ? DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder)
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: DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder);
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break;
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case 2:
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Is128BitVec ? DecodeQPairRegisterClass(Inst, Rt, Address, Decoder)
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: DecodeDPairRegisterClass(Inst, Rt, Address, Decoder);
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break;
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case 3:
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Is128BitVec ? DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder)
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: DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder);
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break;
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case 4:
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Is128BitVec ? DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder)
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: DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder);
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break;
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}
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}
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return MCDisassembler_Success;
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}
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// Decode post-index vector load/store lane instructions.
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// This is necessary as we need to decode Rm: if Rm == 0b11111, the last
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// operand is an immediate equal the the length of the changed bytes,
|
||||
// or Rm is decoded to a GPR64noxzr register.
|
||||
static DecodeStatus DecodeVLDSTLanePostInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address,
|
||||
void *Decoder)
|
||||
{
|
||||
bool Is64bitVec = false;
|
||||
bool IsLoadDup = false;
|
||||
bool IsLoad = false;
|
||||
// The total number of bytes transferred.
|
||||
// TransferBytes = NumVecs * OneLaneBytes
|
||||
unsigned TransferBytes = 0;
|
||||
unsigned NumVecs = 0;
|
||||
unsigned Opc = MCInst_getOpcode(Inst);
|
||||
switch (Opc) {
|
||||
case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:
|
||||
case AArch64_LD1R_WB_4H_fixed: case AArch64_LD1R_WB_4H_register:
|
||||
case AArch64_LD1R_WB_2S_fixed: case AArch64_LD1R_WB_2S_register:
|
||||
case AArch64_LD1R_WB_1D_fixed: case AArch64_LD1R_WB_1D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD1R_WB_8B_fixed: case AArch64_LD1R_WB_8B_register:
|
||||
TransferBytes = 1; break;
|
||||
case AArch64_LD1R_WB_4H_fixed: case AArch64_LD1R_WB_4H_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_LD1R_WB_2S_fixed: case AArch64_LD1R_WB_2S_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD1R_WB_1D_fixed: case AArch64_LD1R_WB_1D_register:
|
||||
TransferBytes = 8; break;
|
||||
}
|
||||
Is64bitVec = true;
|
||||
IsLoadDup = true;
|
||||
NumVecs = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD1R_WB_16B_fixed: case AArch64_LD1R_WB_16B_register:
|
||||
case AArch64_LD1R_WB_8H_fixed: case AArch64_LD1R_WB_8H_register:
|
||||
case AArch64_LD1R_WB_4S_fixed: case AArch64_LD1R_WB_4S_register:
|
||||
case AArch64_LD1R_WB_2D_fixed: case AArch64_LD1R_WB_2D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD1R_WB_16B_fixed: case AArch64_LD1R_WB_16B_register:
|
||||
TransferBytes = 1; break;
|
||||
case AArch64_LD1R_WB_8H_fixed: case AArch64_LD1R_WB_8H_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_LD1R_WB_4S_fixed: case AArch64_LD1R_WB_4S_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD1R_WB_2D_fixed: case AArch64_LD1R_WB_2D_register:
|
||||
TransferBytes = 8; break;
|
||||
}
|
||||
IsLoadDup = true;
|
||||
NumVecs = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD2R_WB_8B_fixed: case AArch64_LD2R_WB_8B_register:
|
||||
case AArch64_LD2R_WB_4H_fixed: case AArch64_LD2R_WB_4H_register:
|
||||
case AArch64_LD2R_WB_2S_fixed: case AArch64_LD2R_WB_2S_register:
|
||||
case AArch64_LD2R_WB_1D_fixed: case AArch64_LD2R_WB_1D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD2R_WB_8B_fixed: case AArch64_LD2R_WB_8B_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_LD2R_WB_4H_fixed: case AArch64_LD2R_WB_4H_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD2R_WB_2S_fixed: case AArch64_LD2R_WB_2S_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_LD2R_WB_1D_fixed: case AArch64_LD2R_WB_1D_register:
|
||||
TransferBytes = 16; break;
|
||||
}
|
||||
Is64bitVec = true;
|
||||
IsLoadDup = true;
|
||||
NumVecs = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD2R_WB_16B_fixed: case AArch64_LD2R_WB_16B_register:
|
||||
case AArch64_LD2R_WB_8H_fixed: case AArch64_LD2R_WB_8H_register:
|
||||
case AArch64_LD2R_WB_4S_fixed: case AArch64_LD2R_WB_4S_register:
|
||||
case AArch64_LD2R_WB_2D_fixed: case AArch64_LD2R_WB_2D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD2R_WB_16B_fixed: case AArch64_LD2R_WB_16B_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_LD2R_WB_8H_fixed: case AArch64_LD2R_WB_8H_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD2R_WB_4S_fixed: case AArch64_LD2R_WB_4S_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_LD2R_WB_2D_fixed: case AArch64_LD2R_WB_2D_register:
|
||||
TransferBytes = 16; break;
|
||||
}
|
||||
IsLoadDup = true;
|
||||
NumVecs = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD3R_WB_8B_fixed: case AArch64_LD3R_WB_8B_register:
|
||||
case AArch64_LD3R_WB_4H_fixed: case AArch64_LD3R_WB_4H_register:
|
||||
case AArch64_LD3R_WB_2S_fixed: case AArch64_LD3R_WB_2S_register:
|
||||
case AArch64_LD3R_WB_1D_fixed: case AArch64_LD3R_WB_1D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD3R_WB_8B_fixed: case AArch64_LD3R_WB_8B_register:
|
||||
TransferBytes = 3; break;
|
||||
case AArch64_LD3R_WB_4H_fixed: case AArch64_LD3R_WB_4H_register:
|
||||
TransferBytes = 6; break;
|
||||
case AArch64_LD3R_WB_2S_fixed: case AArch64_LD3R_WB_2S_register:
|
||||
TransferBytes = 12; break;
|
||||
case AArch64_LD3R_WB_1D_fixed: case AArch64_LD3R_WB_1D_register:
|
||||
TransferBytes = 24; break;
|
||||
}
|
||||
Is64bitVec = true;
|
||||
IsLoadDup = true;
|
||||
NumVecs = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD3R_WB_16B_fixed: case AArch64_LD3R_WB_16B_register:
|
||||
case AArch64_LD3R_WB_4S_fixed: case AArch64_LD3R_WB_8H_register:
|
||||
case AArch64_LD3R_WB_8H_fixed: case AArch64_LD3R_WB_4S_register:
|
||||
case AArch64_LD3R_WB_2D_fixed: case AArch64_LD3R_WB_2D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD3R_WB_16B_fixed: case AArch64_LD3R_WB_16B_register:
|
||||
TransferBytes = 3; break;
|
||||
case AArch64_LD3R_WB_8H_fixed: case AArch64_LD3R_WB_8H_register:
|
||||
TransferBytes = 6; break;
|
||||
case AArch64_LD3R_WB_4S_fixed: case AArch64_LD3R_WB_4S_register:
|
||||
TransferBytes = 12; break;
|
||||
case AArch64_LD3R_WB_2D_fixed: case AArch64_LD3R_WB_2D_register:
|
||||
TransferBytes = 24; break;
|
||||
}
|
||||
IsLoadDup = true;
|
||||
NumVecs = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD4R_WB_8B_fixed: case AArch64_LD4R_WB_8B_register:
|
||||
case AArch64_LD4R_WB_4H_fixed: case AArch64_LD4R_WB_4H_register:
|
||||
case AArch64_LD4R_WB_2S_fixed: case AArch64_LD4R_WB_2S_register:
|
||||
case AArch64_LD4R_WB_1D_fixed: case AArch64_LD4R_WB_1D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD4R_WB_8B_fixed: case AArch64_LD4R_WB_8B_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD4R_WB_4H_fixed: case AArch64_LD4R_WB_4H_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_LD4R_WB_2S_fixed: case AArch64_LD4R_WB_2S_register:
|
||||
TransferBytes = 16; break;
|
||||
case AArch64_LD4R_WB_1D_fixed: case AArch64_LD4R_WB_1D_register:
|
||||
TransferBytes = 32; break;
|
||||
}
|
||||
Is64bitVec = true;
|
||||
IsLoadDup = true;
|
||||
NumVecs = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD4R_WB_16B_fixed: case AArch64_LD4R_WB_16B_register:
|
||||
case AArch64_LD4R_WB_4S_fixed: case AArch64_LD4R_WB_8H_register:
|
||||
case AArch64_LD4R_WB_8H_fixed: case AArch64_LD4R_WB_4S_register:
|
||||
case AArch64_LD4R_WB_2D_fixed: case AArch64_LD4R_WB_2D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD4R_WB_16B_fixed: case AArch64_LD4R_WB_16B_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD4R_WB_8H_fixed: case AArch64_LD4R_WB_8H_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_LD4R_WB_4S_fixed: case AArch64_LD4R_WB_4S_register:
|
||||
TransferBytes = 16; break;
|
||||
case AArch64_LD4R_WB_2D_fixed: case AArch64_LD4R_WB_2D_register:
|
||||
TransferBytes = 32; break;
|
||||
}
|
||||
IsLoadDup = true;
|
||||
NumVecs = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD1LN_WB_B_fixed: case AArch64_LD1LN_WB_B_register:
|
||||
case AArch64_LD1LN_WB_H_fixed: case AArch64_LD1LN_WB_H_register:
|
||||
case AArch64_LD1LN_WB_S_fixed: case AArch64_LD1LN_WB_S_register:
|
||||
case AArch64_LD1LN_WB_D_fixed: case AArch64_LD1LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD1LN_WB_B_fixed: case AArch64_LD1LN_WB_B_register:
|
||||
TransferBytes = 1; break;
|
||||
case AArch64_LD1LN_WB_H_fixed: case AArch64_LD1LN_WB_H_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_LD1LN_WB_S_fixed: case AArch64_LD1LN_WB_S_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD1LN_WB_D_fixed: case AArch64_LD1LN_WB_D_register:
|
||||
TransferBytes = 8; break;
|
||||
}
|
||||
IsLoad = true;
|
||||
NumVecs = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD2LN_WB_B_fixed: case AArch64_LD2LN_WB_B_register:
|
||||
case AArch64_LD2LN_WB_H_fixed: case AArch64_LD2LN_WB_H_register:
|
||||
case AArch64_LD2LN_WB_S_fixed: case AArch64_LD2LN_WB_S_register:
|
||||
case AArch64_LD2LN_WB_D_fixed: case AArch64_LD2LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD2LN_WB_B_fixed: case AArch64_LD2LN_WB_B_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_LD2LN_WB_H_fixed: case AArch64_LD2LN_WB_H_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD2LN_WB_S_fixed: case AArch64_LD2LN_WB_S_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_LD2LN_WB_D_fixed: case AArch64_LD2LN_WB_D_register:
|
||||
TransferBytes = 16; break;
|
||||
}
|
||||
IsLoad = true;
|
||||
NumVecs = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD3LN_WB_B_fixed: case AArch64_LD3LN_WB_B_register:
|
||||
case AArch64_LD3LN_WB_H_fixed: case AArch64_LD3LN_WB_H_register:
|
||||
case AArch64_LD3LN_WB_S_fixed: case AArch64_LD3LN_WB_S_register:
|
||||
case AArch64_LD3LN_WB_D_fixed: case AArch64_LD3LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD3LN_WB_B_fixed: case AArch64_LD3LN_WB_B_register:
|
||||
TransferBytes = 3; break;
|
||||
case AArch64_LD3LN_WB_H_fixed: case AArch64_LD3LN_WB_H_register:
|
||||
TransferBytes = 6; break;
|
||||
case AArch64_LD3LN_WB_S_fixed: case AArch64_LD3LN_WB_S_register:
|
||||
TransferBytes = 12; break;
|
||||
case AArch64_LD3LN_WB_D_fixed: case AArch64_LD3LN_WB_D_register:
|
||||
TransferBytes = 24; break;
|
||||
}
|
||||
IsLoad = true;
|
||||
NumVecs = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_LD4LN_WB_B_fixed: case AArch64_LD4LN_WB_B_register:
|
||||
case AArch64_LD4LN_WB_H_fixed: case AArch64_LD4LN_WB_H_register:
|
||||
case AArch64_LD4LN_WB_S_fixed: case AArch64_LD4LN_WB_S_register:
|
||||
case AArch64_LD4LN_WB_D_fixed: case AArch64_LD4LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_LD4LN_WB_B_fixed: case AArch64_LD4LN_WB_B_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_LD4LN_WB_H_fixed: case AArch64_LD4LN_WB_H_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_LD4LN_WB_S_fixed: case AArch64_LD4LN_WB_S_register:
|
||||
TransferBytes = 16; break;
|
||||
case AArch64_LD4LN_WB_D_fixed: case AArch64_LD4LN_WB_D_register:
|
||||
TransferBytes = 32; break;
|
||||
}
|
||||
IsLoad = true;
|
||||
NumVecs = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_ST1LN_WB_B_fixed: case AArch64_ST1LN_WB_B_register:
|
||||
case AArch64_ST1LN_WB_H_fixed: case AArch64_ST1LN_WB_H_register:
|
||||
case AArch64_ST1LN_WB_S_fixed: case AArch64_ST1LN_WB_S_register:
|
||||
case AArch64_ST1LN_WB_D_fixed: case AArch64_ST1LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_ST1LN_WB_B_fixed: case AArch64_ST1LN_WB_B_register:
|
||||
TransferBytes = 1; break;
|
||||
case AArch64_ST1LN_WB_H_fixed: case AArch64_ST1LN_WB_H_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_ST1LN_WB_S_fixed: case AArch64_ST1LN_WB_S_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_ST1LN_WB_D_fixed: case AArch64_ST1LN_WB_D_register:
|
||||
TransferBytes = 8; break;
|
||||
}
|
||||
NumVecs = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_ST2LN_WB_B_fixed: case AArch64_ST2LN_WB_B_register:
|
||||
case AArch64_ST2LN_WB_H_fixed: case AArch64_ST2LN_WB_H_register:
|
||||
case AArch64_ST2LN_WB_S_fixed: case AArch64_ST2LN_WB_S_register:
|
||||
case AArch64_ST2LN_WB_D_fixed: case AArch64_ST2LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_ST2LN_WB_B_fixed: case AArch64_ST2LN_WB_B_register:
|
||||
TransferBytes = 2; break;
|
||||
case AArch64_ST2LN_WB_H_fixed: case AArch64_ST2LN_WB_H_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_ST2LN_WB_S_fixed: case AArch64_ST2LN_WB_S_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_ST2LN_WB_D_fixed: case AArch64_ST2LN_WB_D_register:
|
||||
TransferBytes = 16; break;
|
||||
}
|
||||
NumVecs = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_ST3LN_WB_B_fixed: case AArch64_ST3LN_WB_B_register:
|
||||
case AArch64_ST3LN_WB_H_fixed: case AArch64_ST3LN_WB_H_register:
|
||||
case AArch64_ST3LN_WB_S_fixed: case AArch64_ST3LN_WB_S_register:
|
||||
case AArch64_ST3LN_WB_D_fixed: case AArch64_ST3LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_ST3LN_WB_B_fixed: case AArch64_ST3LN_WB_B_register:
|
||||
TransferBytes = 3; break;
|
||||
case AArch64_ST3LN_WB_H_fixed: case AArch64_ST3LN_WB_H_register:
|
||||
TransferBytes = 6; break;
|
||||
case AArch64_ST3LN_WB_S_fixed: case AArch64_ST3LN_WB_S_register:
|
||||
TransferBytes = 12; break;
|
||||
case AArch64_ST3LN_WB_D_fixed: case AArch64_ST3LN_WB_D_register:
|
||||
TransferBytes = 24; break;
|
||||
}
|
||||
NumVecs = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
case AArch64_ST4LN_WB_B_fixed: case AArch64_ST4LN_WB_B_register:
|
||||
case AArch64_ST4LN_WB_H_fixed: case AArch64_ST4LN_WB_H_register:
|
||||
case AArch64_ST4LN_WB_S_fixed: case AArch64_ST4LN_WB_S_register:
|
||||
case AArch64_ST4LN_WB_D_fixed: case AArch64_ST4LN_WB_D_register:
|
||||
{
|
||||
switch (Opc) {
|
||||
case AArch64_ST4LN_WB_B_fixed: case AArch64_ST4LN_WB_B_register:
|
||||
TransferBytes = 4; break;
|
||||
case AArch64_ST4LN_WB_H_fixed: case AArch64_ST4LN_WB_H_register:
|
||||
TransferBytes = 8; break;
|
||||
case AArch64_ST4LN_WB_S_fixed: case AArch64_ST4LN_WB_S_register:
|
||||
TransferBytes = 16; break;
|
||||
case AArch64_ST4LN_WB_D_fixed: case AArch64_ST4LN_WB_D_register:
|
||||
TransferBytes = 32; break;
|
||||
}
|
||||
NumVecs = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
return MCDisassembler_Fail;
|
||||
} // End of switch (Opc)
|
||||
|
||||
unsigned Rt = fieldFromInstruction(Insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
|
||||
unsigned Rm = fieldFromInstruction(Insn, 16, 5);
|
||||
|
||||
// Decode post-index of load duplicate lane
|
||||
if (IsLoadDup) {
|
||||
switch (NumVecs) {
|
||||
case 1:
|
||||
Is64bitVec ? DecodeFPR64RegisterClass(Inst, Rt, Address, Decoder)
|
||||
: DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 2:
|
||||
Is64bitVec ? DecodeDPairRegisterClass(Inst, Rt, Address, Decoder)
|
||||
: DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 3:
|
||||
Is64bitVec ? DecodeDTripleRegisterClass(Inst, Rt, Address, Decoder)
|
||||
: DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 4:
|
||||
Is64bitVec ? DecodeDQuadRegisterClass(Inst, Rt, Address, Decoder)
|
||||
: DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
|
||||
}
|
||||
|
||||
// Decode write back register, which is equal to Rn.
|
||||
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
||||
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
||||
|
||||
if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
|
||||
MCInst_addOperand(Inst, MCOperand_CreateImm(TransferBytes));
|
||||
else // Decode Rm
|
||||
DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
// Decode post-index of load/store lane
|
||||
// Loads have a vector list as output.
|
||||
if (IsLoad) {
|
||||
switch (NumVecs) {
|
||||
case 1:
|
||||
DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 2:
|
||||
DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 3:
|
||||
DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 4:
|
||||
DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
|
||||
}
|
||||
}
|
||||
|
||||
// Decode write back register, which is equal to Rn.
|
||||
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
||||
DecodeGPR64xspRegisterClass(Inst, Rn, Address, Decoder);
|
||||
|
||||
if (Rm == 31) // If Rm is 0x11111, add the number of transferred bytes
|
||||
MCInst_addOperand(Inst, MCOperand_CreateImm(TransferBytes));
|
||||
else // Decode Rm
|
||||
DecodeGPR64noxzrRegisterClass(Inst, Rm, Address, Decoder);
|
||||
|
||||
// Decode the source vector list.
|
||||
switch (NumVecs) {
|
||||
case 1:
|
||||
DecodeFPR128RegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 2:
|
||||
DecodeQPairRegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 3:
|
||||
DecodeQTripleRegisterClass(Inst, Rt, Address, Decoder);
|
||||
break;
|
||||
case 4:
|
||||
DecodeQQuadRegisterClass(Inst, Rt, Address, Decoder);
|
||||
}
|
||||
|
||||
// Decode lane
|
||||
unsigned Q = fieldFromInstruction(Insn, 30, 1);
|
||||
unsigned S = fieldFromInstruction(Insn, 10, 3);
|
||||
unsigned lane = 0;
|
||||
// Calculate the number of lanes by number of vectors and transfered bytes.
|
||||
// NumLanes = 16 bytes / bytes of each lane
|
||||
unsigned NumLanes = 16 / (TransferBytes / NumVecs);
|
||||
switch (NumLanes) {
|
||||
case 16: // A vector has 16 lanes, each lane is 1 bytes.
|
||||
lane = (Q << 3) | S;
|
||||
break;
|
||||
case 8:
|
||||
lane = (Q << 2) | (S >> 1);
|
||||
break;
|
||||
case 4:
|
||||
lane = (Q << 1) | (S >> 2);
|
||||
break;
|
||||
case 2:
|
||||
lane = Q;
|
||||
break;
|
||||
}
|
||||
MCInst_addOperand(Inst, MCOperand_CreateImm(lane));
|
||||
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
static DecodeStatus DecodeSHLLInstruction(MCInst *Inst, unsigned Insn,
|
||||
uint64_t Address,
|
||||
void *Decoder)
|
||||
{
|
||||
unsigned Rd = fieldFromInstruction(Insn, 0, 5);
|
||||
unsigned Rn = fieldFromInstruction(Insn, 5, 5);
|
||||
unsigned size = fieldFromInstruction(Insn, 22, 2);
|
||||
unsigned Q = fieldFromInstruction(Insn, 30, 1);
|
||||
|
||||
DecodeFPR128RegisterClass(Inst, Rd, Address, Decoder);
|
||||
|
||||
if (Q)
|
||||
DecodeFPR128RegisterClass(Inst, Rn, Address, Decoder);
|
||||
else
|
||||
DecodeFPR64RegisterClass(Inst, Rn, Address, Decoder);
|
||||
|
||||
switch (size) {
|
||||
case 0:
|
||||
MCInst_addOperand(Inst, MCOperand_CreateImm(8));
|
||||
break;
|
||||
case 1:
|
||||
MCInst_addOperand(Inst, MCOperand_CreateImm(16));
|
||||
break;
|
||||
case 2:
|
||||
MCInst_addOperand(Inst, MCOperand_CreateImm(32));
|
||||
break;
|
||||
default :
|
||||
return MCDisassembler_Fail;
|
||||
}
|
||||
return MCDisassembler_Success;
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -13,7 +13,8 @@
|
|||
#undef GET_SUBTARGETINFO_ENUM
|
||||
enum {
|
||||
AArch64_FeatureCrypto = 1ULL << 0,
|
||||
AArch64_FeatureNEON = 1ULL << 1
|
||||
AArch64_FeatureFPARMv8 = 1ULL << 1,
|
||||
AArch64_FeatureNEON = 1ULL << 2
|
||||
};
|
||||
#endif // GET_SUBTARGETINFO_ENUM
|
||||
|
||||
|
|
@ -24,7 +25,8 @@ enum {
|
|||
// Sorted (by key) array of values for CPU features.
|
||||
static SubtargetFeatureKV AArch64FeatureKV[] = {
|
||||
{ "crypto", "Enable cryptographic instructions", AArch64_FeatureCrypto, 0ULL },
|
||||
{ "neon", "Enable Advanced SIMD instructions", AArch64_FeatureNEON, 0ULL }
|
||||
{ "fp-armv8", "Enable ARMv8 FP", AArch64_FeatureFPARMv8, 0ULL },
|
||||
{ "neon", "Enable Advanced SIMD instructions", AArch64_FeatureNEON, AArch64_FeatureFPARMv8 }
|
||||
};
|
||||
|
||||
#endif // GET_SUBTARGETINFO_MC_DESC
|
||||
|
|
|
|||
|
|
@ -556,7 +556,7 @@ static void printNeonUImm0Operand(MCInst *MI, unsigned OpNum, SStream *O)
|
|||
MI->pub_insn.arm64.op_count++;
|
||||
}
|
||||
|
||||
static void printNeonUImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
static void printUImmHexOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *MOUImm = MCInst_getOperand(MI, OpNum);
|
||||
|
||||
|
|
@ -565,13 +565,13 @@ static void printNeonUImm8Operand(MCInst *MI, unsigned OpNum, SStream *O)
|
|||
|
||||
unsigned Imm = MCOperand_getImm(MOUImm);
|
||||
|
||||
SStream_concat(O, "#0x%"PRIx64, Imm);
|
||||
SStream_concat(O, "#0x%x", Imm);
|
||||
MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].type = ARM64_OP_IMM;
|
||||
MI->pub_insn.arm64.operands[MI->pub_insn.arm64.op_count].imm = Imm;
|
||||
MI->pub_insn.arm64.op_count++;
|
||||
}
|
||||
|
||||
static void printNeonUImm8OperandBare(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
static void printUImmBareOperand(MCInst *MI, unsigned OpNum, SStream *O)
|
||||
{
|
||||
MCOperand *MOUImm = MCInst_getOperand(MI, OpNum);
|
||||
|
||||
|
|
@ -621,6 +621,38 @@ static void printMSROperand(MCInst *MI, unsigned OpNum, SStream *O)
|
|||
printSysRegOperand(&AArch64_MSRMapper, MI, OpNum, O);
|
||||
}
|
||||
|
||||
// If Count > 1, there are two valid kinds of vector list:
|
||||
// (1) {Vn.layout, Vn+1.layout, ... , Vm.layout}
|
||||
// (2) {Vn.layout - Vm.layout}
|
||||
// We choose the first kind as output.
|
||||
static void printVectorList(MCInst *MI, unsigned OpNum,
|
||||
SStream *O, MCRegisterInfo *MRI, A64Layout_VectorLayout Layout, unsigned Count)
|
||||
{
|
||||
//assert(Count >= 1 && Count <= 4 && "Invalid Number of Vectors");
|
||||
|
||||
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
|
||||
const char *LayoutStr = A64VectorLayoutToString(Layout);
|
||||
SStream_concat(O, "{");
|
||||
if (Count > 1) { // Print sub registers separately
|
||||
bool IsVec64 = (Layout < A64Layout_VL_16B);
|
||||
unsigned SubRegIdx = IsVec64 ? AArch64_dsub_0 : AArch64_qsub_0;
|
||||
unsigned I;
|
||||
for (I = 0; I < Count; I++) {
|
||||
char *Name = strdup(getRegisterName(MCRegisterInfo_getSubReg(MRI, Reg, SubRegIdx++)));
|
||||
Name[0] = 'v';
|
||||
SStream_concat(O, "%s%s", Name, LayoutStr);
|
||||
if (I != Count - 1)
|
||||
SStream_concat(O, ", ");
|
||||
free(Name);
|
||||
}
|
||||
} else { // Print the register directly when NumVecs is 1.
|
||||
char *Name = strdup(getRegisterName(Reg));
|
||||
Name[0] = 'v';
|
||||
SStream_concat(O, "%s%s", Name, LayoutStr);
|
||||
free(Name);
|
||||
}
|
||||
SStream_concat(O, "}");
|
||||
}
|
||||
|
||||
#define PRINT_ALIAS_INSTR
|
||||
#include "AArch64GenAsmWriter.inc"
|
||||
|
|
@ -645,6 +677,6 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
|
|||
MCInst_setOpcodePub(MI, AArch64_map_insn(mnem));
|
||||
free(mnem);
|
||||
} else
|
||||
AArch64InstPrinter_printInstruction(MI, O);
|
||||
AArch64InstPrinter_printInstruction(MI, O, Info);
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
747
include/arm64.h
747
include/arm64.h
|
|
@ -107,248 +107,448 @@ typedef struct cs_arm64 {
|
|||
//> ARM64 registers
|
||||
typedef enum arm64_reg {
|
||||
ARM64_REG_INVALID = 0,
|
||||
ARM64_REG_NZCV = 1,
|
||||
ARM64_REG_WSP = 2,
|
||||
ARM64_REG_WZR = 3,
|
||||
ARM64_REG_SP = 4,
|
||||
ARM64_REG_XZR = 5,
|
||||
ARM64_REG_B0 = 6,
|
||||
ARM64_REG_B1 = 7,
|
||||
ARM64_REG_B2 = 8,
|
||||
ARM64_REG_B3 = 9,
|
||||
ARM64_REG_B4 = 10,
|
||||
ARM64_REG_B5 = 11,
|
||||
ARM64_REG_B6 = 12,
|
||||
ARM64_REG_B7 = 13,
|
||||
ARM64_REG_B8 = 14,
|
||||
ARM64_REG_B9 = 15,
|
||||
ARM64_REG_B10 = 16,
|
||||
ARM64_REG_B11 = 17,
|
||||
ARM64_REG_B12 = 18,
|
||||
ARM64_REG_B13 = 19,
|
||||
ARM64_REG_B14 = 20,
|
||||
ARM64_REG_B15 = 21,
|
||||
ARM64_REG_B16 = 22,
|
||||
ARM64_REG_B17 = 23,
|
||||
ARM64_REG_B18 = 24,
|
||||
ARM64_REG_B19 = 25,
|
||||
ARM64_REG_B20 = 26,
|
||||
ARM64_REG_B21 = 27,
|
||||
ARM64_REG_B22 = 28,
|
||||
ARM64_REG_B23 = 29,
|
||||
ARM64_REG_B24 = 30,
|
||||
ARM64_REG_B25 = 31,
|
||||
ARM64_REG_B26 = 32,
|
||||
ARM64_REG_B27 = 33,
|
||||
ARM64_REG_B28 = 34,
|
||||
ARM64_REG_B29 = 35,
|
||||
ARM64_REG_B30 = 36,
|
||||
ARM64_REG_B31 = 37,
|
||||
ARM64_REG_D0 = 38,
|
||||
ARM64_REG_D1 = 39,
|
||||
ARM64_REG_D2 = 40,
|
||||
ARM64_REG_D3 = 41,
|
||||
ARM64_REG_D4 = 42,
|
||||
ARM64_REG_D5 = 43,
|
||||
ARM64_REG_D6 = 44,
|
||||
ARM64_REG_D7 = 45,
|
||||
ARM64_REG_D8 = 46,
|
||||
ARM64_REG_D9 = 47,
|
||||
ARM64_REG_D10 = 48,
|
||||
ARM64_REG_D11 = 49,
|
||||
ARM64_REG_D12 = 50,
|
||||
ARM64_REG_D13 = 51,
|
||||
ARM64_REG_D14 = 52,
|
||||
ARM64_REG_D15 = 53,
|
||||
ARM64_REG_D16 = 54,
|
||||
ARM64_REG_D17 = 55,
|
||||
ARM64_REG_D18 = 56,
|
||||
ARM64_REG_D19 = 57,
|
||||
ARM64_REG_D20 = 58,
|
||||
ARM64_REG_D21 = 59,
|
||||
ARM64_REG_D22 = 60,
|
||||
ARM64_REG_D23 = 61,
|
||||
ARM64_REG_D24 = 62,
|
||||
ARM64_REG_D25 = 63,
|
||||
ARM64_REG_D26 = 64,
|
||||
ARM64_REG_D27 = 65,
|
||||
ARM64_REG_D28 = 66,
|
||||
ARM64_REG_D29 = 67,
|
||||
ARM64_REG_D30 = 68,
|
||||
ARM64_REG_D31 = 69,
|
||||
ARM64_REG_H0 = 70,
|
||||
ARM64_REG_H1 = 71,
|
||||
ARM64_REG_H2 = 72,
|
||||
ARM64_REG_H3 = 73,
|
||||
ARM64_REG_H4 = 74,
|
||||
ARM64_REG_H5 = 75,
|
||||
ARM64_REG_H6 = 76,
|
||||
ARM64_REG_H7 = 77,
|
||||
ARM64_REG_H8 = 78,
|
||||
ARM64_REG_H9 = 79,
|
||||
ARM64_REG_H10 = 80,
|
||||
ARM64_REG_H11 = 81,
|
||||
ARM64_REG_H12 = 82,
|
||||
ARM64_REG_H13 = 83,
|
||||
ARM64_REG_H14 = 84,
|
||||
ARM64_REG_H15 = 85,
|
||||
ARM64_REG_H16 = 86,
|
||||
ARM64_REG_H17 = 87,
|
||||
ARM64_REG_H18 = 88,
|
||||
ARM64_REG_H19 = 89,
|
||||
ARM64_REG_H20 = 90,
|
||||
ARM64_REG_H21 = 91,
|
||||
ARM64_REG_H22 = 92,
|
||||
ARM64_REG_H23 = 93,
|
||||
ARM64_REG_H24 = 94,
|
||||
ARM64_REG_H25 = 95,
|
||||
ARM64_REG_H26 = 96,
|
||||
ARM64_REG_H27 = 97,
|
||||
ARM64_REG_H28 = 98,
|
||||
ARM64_REG_H29 = 99,
|
||||
ARM64_REG_H30 = 100,
|
||||
ARM64_REG_H31 = 101,
|
||||
ARM64_REG_Q0 = 102,
|
||||
ARM64_REG_Q1 = 103,
|
||||
ARM64_REG_Q2 = 104,
|
||||
ARM64_REG_Q3 = 105,
|
||||
ARM64_REG_Q4 = 106,
|
||||
ARM64_REG_Q5 = 107,
|
||||
ARM64_REG_Q6 = 108,
|
||||
ARM64_REG_Q7 = 109,
|
||||
ARM64_REG_Q8 = 110,
|
||||
ARM64_REG_Q9 = 111,
|
||||
ARM64_REG_Q10 = 112,
|
||||
ARM64_REG_Q11 = 113,
|
||||
ARM64_REG_Q12 = 114,
|
||||
ARM64_REG_Q13 = 115,
|
||||
ARM64_REG_Q14 = 116,
|
||||
ARM64_REG_Q15 = 117,
|
||||
ARM64_REG_Q16 = 118,
|
||||
ARM64_REG_Q17 = 119,
|
||||
ARM64_REG_Q18 = 120,
|
||||
ARM64_REG_Q19 = 121,
|
||||
ARM64_REG_Q20 = 122,
|
||||
ARM64_REG_Q21 = 123,
|
||||
ARM64_REG_Q22 = 124,
|
||||
ARM64_REG_Q23 = 125,
|
||||
ARM64_REG_Q24 = 126,
|
||||
ARM64_REG_Q25 = 127,
|
||||
ARM64_REG_Q26 = 128,
|
||||
ARM64_REG_Q27 = 129,
|
||||
ARM64_REG_Q28 = 130,
|
||||
ARM64_REG_Q29 = 131,
|
||||
ARM64_REG_Q30 = 132,
|
||||
ARM64_REG_Q31 = 133,
|
||||
ARM64_REG_S0 = 134,
|
||||
ARM64_REG_S1 = 135,
|
||||
ARM64_REG_S2 = 136,
|
||||
ARM64_REG_S3 = 137,
|
||||
ARM64_REG_S4 = 138,
|
||||
ARM64_REG_S5 = 139,
|
||||
ARM64_REG_S6 = 140,
|
||||
ARM64_REG_S7 = 141,
|
||||
ARM64_REG_S8 = 142,
|
||||
ARM64_REG_S9 = 143,
|
||||
ARM64_REG_S10 = 144,
|
||||
ARM64_REG_S11 = 145,
|
||||
ARM64_REG_S12 = 146,
|
||||
ARM64_REG_S13 = 147,
|
||||
ARM64_REG_S14 = 148,
|
||||
ARM64_REG_S15 = 149,
|
||||
ARM64_REG_S16 = 150,
|
||||
ARM64_REG_S17 = 151,
|
||||
ARM64_REG_S18 = 152,
|
||||
ARM64_REG_S19 = 153,
|
||||
ARM64_REG_S20 = 154,
|
||||
ARM64_REG_S21 = 155,
|
||||
ARM64_REG_S22 = 156,
|
||||
ARM64_REG_S23 = 157,
|
||||
ARM64_REG_S24 = 158,
|
||||
ARM64_REG_S25 = 159,
|
||||
ARM64_REG_S26 = 160,
|
||||
ARM64_REG_S27 = 161,
|
||||
ARM64_REG_S28 = 162,
|
||||
ARM64_REG_S29 = 163,
|
||||
ARM64_REG_S30 = 164,
|
||||
ARM64_REG_S31 = 165,
|
||||
ARM64_REG_W0 = 166,
|
||||
ARM64_REG_W1 = 167,
|
||||
ARM64_REG_W2 = 168,
|
||||
ARM64_REG_W3 = 169,
|
||||
ARM64_REG_W4 = 170,
|
||||
ARM64_REG_W5 = 171,
|
||||
ARM64_REG_W6 = 172,
|
||||
ARM64_REG_W7 = 173,
|
||||
ARM64_REG_W8 = 174,
|
||||
ARM64_REG_W9 = 175,
|
||||
ARM64_REG_W10 = 176,
|
||||
ARM64_REG_W11 = 177,
|
||||
ARM64_REG_W12 = 178,
|
||||
ARM64_REG_W13 = 179,
|
||||
ARM64_REG_W14 = 180,
|
||||
ARM64_REG_W15 = 181,
|
||||
ARM64_REG_W16 = 182,
|
||||
ARM64_REG_W17 = 183,
|
||||
ARM64_REG_W18 = 184,
|
||||
ARM64_REG_W19 = 185,
|
||||
ARM64_REG_W20 = 186,
|
||||
ARM64_REG_W21 = 187,
|
||||
ARM64_REG_W22 = 188,
|
||||
ARM64_REG_W23 = 189,
|
||||
ARM64_REG_W24 = 190,
|
||||
ARM64_REG_W25 = 191,
|
||||
ARM64_REG_W26 = 192,
|
||||
ARM64_REG_W27 = 193,
|
||||
ARM64_REG_W28 = 194,
|
||||
ARM64_REG_W29 = 195,
|
||||
ARM64_REG_W30 = 196,
|
||||
ARM64_REG_X0 = 197,
|
||||
ARM64_REG_X1 = 198,
|
||||
ARM64_REG_X2 = 199,
|
||||
ARM64_REG_X3 = 200,
|
||||
ARM64_REG_X4 = 201,
|
||||
ARM64_REG_X5 = 202,
|
||||
ARM64_REG_X6 = 203,
|
||||
ARM64_REG_X7 = 204,
|
||||
ARM64_REG_X8 = 205,
|
||||
ARM64_REG_X9 = 206,
|
||||
ARM64_REG_X10 = 207,
|
||||
ARM64_REG_X11 = 208,
|
||||
ARM64_REG_X12 = 209,
|
||||
ARM64_REG_X13 = 210,
|
||||
ARM64_REG_X14 = 211,
|
||||
ARM64_REG_X15 = 212,
|
||||
ARM64_REG_X16 = 213,
|
||||
ARM64_REG_X17 = 214,
|
||||
ARM64_REG_X18 = 215,
|
||||
ARM64_REG_X19 = 216,
|
||||
ARM64_REG_X20 = 217,
|
||||
ARM64_REG_X21 = 218,
|
||||
ARM64_REG_X22 = 219,
|
||||
ARM64_REG_X23 = 220,
|
||||
ARM64_REG_X24 = 221,
|
||||
ARM64_REG_X25 = 222,
|
||||
ARM64_REG_X26 = 223,
|
||||
ARM64_REG_X27 = 224,
|
||||
ARM64_REG_X28 = 225,
|
||||
ARM64_REG_X29 = 226,
|
||||
ARM64_REG_X30 = 227,
|
||||
|
||||
ARM64_REG_MAX = 228, // <-- mark the end of the list of registers
|
||||
ARM64_REG_NZCV,
|
||||
ARM64_REG_WSP,
|
||||
ARM64_REG_WZR,
|
||||
ARM64_REG_SP,
|
||||
ARM64_REG_XZR,
|
||||
ARM64_REG_B0,
|
||||
ARM64_REG_B1,
|
||||
ARM64_REG_B2,
|
||||
ARM64_REG_B3,
|
||||
ARM64_REG_B4,
|
||||
ARM64_REG_B5,
|
||||
ARM64_REG_B6,
|
||||
ARM64_REG_B7,
|
||||
ARM64_REG_B8,
|
||||
ARM64_REG_B9,
|
||||
ARM64_REG_B10,
|
||||
ARM64_REG_B11,
|
||||
ARM64_REG_B12,
|
||||
ARM64_REG_B13,
|
||||
ARM64_REG_B14,
|
||||
ARM64_REG_B15,
|
||||
ARM64_REG_B16,
|
||||
ARM64_REG_B17,
|
||||
ARM64_REG_B18,
|
||||
ARM64_REG_B19,
|
||||
ARM64_REG_B20,
|
||||
ARM64_REG_B21,
|
||||
ARM64_REG_B22,
|
||||
ARM64_REG_B23,
|
||||
ARM64_REG_B24,
|
||||
ARM64_REG_B25,
|
||||
ARM64_REG_B26,
|
||||
ARM64_REG_B27,
|
||||
ARM64_REG_B28,
|
||||
ARM64_REG_B29,
|
||||
ARM64_REG_B30,
|
||||
ARM64_REG_B31,
|
||||
ARM64_REG_D0,
|
||||
ARM64_REG_D1,
|
||||
ARM64_REG_D2,
|
||||
ARM64_REG_D3,
|
||||
ARM64_REG_D4,
|
||||
ARM64_REG_D5,
|
||||
ARM64_REG_D6,
|
||||
ARM64_REG_D7,
|
||||
ARM64_REG_D8,
|
||||
ARM64_REG_D9,
|
||||
ARM64_REG_D10,
|
||||
ARM64_REG_D11,
|
||||
ARM64_REG_D12,
|
||||
ARM64_REG_D13,
|
||||
ARM64_REG_D14,
|
||||
ARM64_REG_D15,
|
||||
ARM64_REG_D16,
|
||||
ARM64_REG_D17,
|
||||
ARM64_REG_D18,
|
||||
ARM64_REG_D19,
|
||||
ARM64_REG_D20,
|
||||
ARM64_REG_D21,
|
||||
ARM64_REG_D22,
|
||||
ARM64_REG_D23,
|
||||
ARM64_REG_D24,
|
||||
ARM64_REG_D25,
|
||||
ARM64_REG_D26,
|
||||
ARM64_REG_D27,
|
||||
ARM64_REG_D28,
|
||||
ARM64_REG_D29,
|
||||
ARM64_REG_D30,
|
||||
ARM64_REG_D31,
|
||||
ARM64_REG_H0,
|
||||
ARM64_REG_H1,
|
||||
ARM64_REG_H2,
|
||||
ARM64_REG_H3,
|
||||
ARM64_REG_H4,
|
||||
ARM64_REG_H5,
|
||||
ARM64_REG_H6,
|
||||
ARM64_REG_H7,
|
||||
ARM64_REG_H8,
|
||||
ARM64_REG_H9,
|
||||
ARM64_REG_H10,
|
||||
ARM64_REG_H11,
|
||||
ARM64_REG_H12,
|
||||
ARM64_REG_H13,
|
||||
ARM64_REG_H14,
|
||||
ARM64_REG_H15,
|
||||
ARM64_REG_H16,
|
||||
ARM64_REG_H17,
|
||||
ARM64_REG_H18,
|
||||
ARM64_REG_H19,
|
||||
ARM64_REG_H20,
|
||||
ARM64_REG_H21,
|
||||
ARM64_REG_H22,
|
||||
ARM64_REG_H23,
|
||||
ARM64_REG_H24,
|
||||
ARM64_REG_H25,
|
||||
ARM64_REG_H26,
|
||||
ARM64_REG_H27,
|
||||
ARM64_REG_H28,
|
||||
ARM64_REG_H29,
|
||||
ARM64_REG_H30,
|
||||
ARM64_REG_H31,
|
||||
ARM64_REG_Q0,
|
||||
ARM64_REG_Q1,
|
||||
ARM64_REG_Q2,
|
||||
ARM64_REG_Q3,
|
||||
ARM64_REG_Q4,
|
||||
ARM64_REG_Q5,
|
||||
ARM64_REG_Q6,
|
||||
ARM64_REG_Q7,
|
||||
ARM64_REG_Q8,
|
||||
ARM64_REG_Q9,
|
||||
ARM64_REG_Q10,
|
||||
ARM64_REG_Q11,
|
||||
ARM64_REG_Q12,
|
||||
ARM64_REG_Q13,
|
||||
ARM64_REG_Q14,
|
||||
ARM64_REG_Q15,
|
||||
ARM64_REG_Q16,
|
||||
ARM64_REG_Q17,
|
||||
ARM64_REG_Q18,
|
||||
ARM64_REG_Q19,
|
||||
ARM64_REG_Q20,
|
||||
ARM64_REG_Q21,
|
||||
ARM64_REG_Q22,
|
||||
ARM64_REG_Q23,
|
||||
ARM64_REG_Q24,
|
||||
ARM64_REG_Q25,
|
||||
ARM64_REG_Q26,
|
||||
ARM64_REG_Q27,
|
||||
ARM64_REG_Q28,
|
||||
ARM64_REG_Q29,
|
||||
ARM64_REG_Q30,
|
||||
ARM64_REG_Q31,
|
||||
ARM64_REG_S0,
|
||||
ARM64_REG_S1,
|
||||
ARM64_REG_S2,
|
||||
ARM64_REG_S3,
|
||||
ARM64_REG_S4,
|
||||
ARM64_REG_S5,
|
||||
ARM64_REG_S6,
|
||||
ARM64_REG_S7,
|
||||
ARM64_REG_S8,
|
||||
ARM64_REG_S9,
|
||||
ARM64_REG_S10,
|
||||
ARM64_REG_S11,
|
||||
ARM64_REG_S12,
|
||||
ARM64_REG_S13,
|
||||
ARM64_REG_S14,
|
||||
ARM64_REG_S15,
|
||||
ARM64_REG_S16,
|
||||
ARM64_REG_S17,
|
||||
ARM64_REG_S18,
|
||||
ARM64_REG_S19,
|
||||
ARM64_REG_S20,
|
||||
ARM64_REG_S21,
|
||||
ARM64_REG_S22,
|
||||
ARM64_REG_S23,
|
||||
ARM64_REG_S24,
|
||||
ARM64_REG_S25,
|
||||
ARM64_REG_S26,
|
||||
ARM64_REG_S27,
|
||||
ARM64_REG_S28,
|
||||
ARM64_REG_S29,
|
||||
ARM64_REG_S30,
|
||||
ARM64_REG_S31,
|
||||
ARM64_REG_W0,
|
||||
ARM64_REG_W1,
|
||||
ARM64_REG_W2,
|
||||
ARM64_REG_W3,
|
||||
ARM64_REG_W4,
|
||||
ARM64_REG_W5,
|
||||
ARM64_REG_W6,
|
||||
ARM64_REG_W7,
|
||||
ARM64_REG_W8,
|
||||
ARM64_REG_W9,
|
||||
ARM64_REG_W10,
|
||||
ARM64_REG_W11,
|
||||
ARM64_REG_W12,
|
||||
ARM64_REG_W13,
|
||||
ARM64_REG_W14,
|
||||
ARM64_REG_W15,
|
||||
ARM64_REG_W16,
|
||||
ARM64_REG_W17,
|
||||
ARM64_REG_W18,
|
||||
ARM64_REG_W19,
|
||||
ARM64_REG_W20,
|
||||
ARM64_REG_W21,
|
||||
ARM64_REG_W22,
|
||||
ARM64_REG_W23,
|
||||
ARM64_REG_W24,
|
||||
ARM64_REG_W25,
|
||||
ARM64_REG_W26,
|
||||
ARM64_REG_W27,
|
||||
ARM64_REG_W28,
|
||||
ARM64_REG_W29,
|
||||
ARM64_REG_W30,
|
||||
ARM64_REG_X0,
|
||||
ARM64_REG_X1,
|
||||
ARM64_REG_X2,
|
||||
ARM64_REG_X3,
|
||||
ARM64_REG_X4,
|
||||
ARM64_REG_X5,
|
||||
ARM64_REG_X6,
|
||||
ARM64_REG_X7,
|
||||
ARM64_REG_X8,
|
||||
ARM64_REG_X9,
|
||||
ARM64_REG_X10,
|
||||
ARM64_REG_X11,
|
||||
ARM64_REG_X12,
|
||||
ARM64_REG_X13,
|
||||
ARM64_REG_X14,
|
||||
ARM64_REG_X15,
|
||||
ARM64_REG_X16,
|
||||
ARM64_REG_X17,
|
||||
ARM64_REG_X18,
|
||||
ARM64_REG_X19,
|
||||
ARM64_REG_X20,
|
||||
ARM64_REG_X21,
|
||||
ARM64_REG_X22,
|
||||
ARM64_REG_X23,
|
||||
ARM64_REG_X24,
|
||||
ARM64_REG_X25,
|
||||
ARM64_REG_X26,
|
||||
ARM64_REG_X27,
|
||||
ARM64_REG_X28,
|
||||
ARM64_REG_X29,
|
||||
ARM64_REG_X30,
|
||||
ARM64_REG_D0_D1,
|
||||
ARM64_REG_D1_D2,
|
||||
ARM64_REG_D2_D3,
|
||||
ARM64_REG_D3_D4,
|
||||
ARM64_REG_D4_D5,
|
||||
ARM64_REG_D5_D6,
|
||||
ARM64_REG_D6_D7,
|
||||
ARM64_REG_D7_D8,
|
||||
ARM64_REG_D8_D9,
|
||||
ARM64_REG_D9_D10,
|
||||
ARM64_REG_D10_D11,
|
||||
ARM64_REG_D11_D12,
|
||||
ARM64_REG_D12_D13,
|
||||
ARM64_REG_D13_D14,
|
||||
ARM64_REG_D14_D15,
|
||||
ARM64_REG_D15_D16,
|
||||
ARM64_REG_D16_D17,
|
||||
ARM64_REG_D17_D18,
|
||||
ARM64_REG_D18_D19,
|
||||
ARM64_REG_D19_D20,
|
||||
ARM64_REG_D20_D21,
|
||||
ARM64_REG_D21_D22,
|
||||
ARM64_REG_D22_D23,
|
||||
ARM64_REG_D23_D24,
|
||||
ARM64_REG_D24_D25,
|
||||
ARM64_REG_D25_D26,
|
||||
ARM64_REG_D26_D27,
|
||||
ARM64_REG_D27_D28,
|
||||
ARM64_REG_D28_D29,
|
||||
ARM64_REG_D29_D30,
|
||||
ARM64_REG_D30_D31,
|
||||
ARM64_REG_D31_D0,
|
||||
ARM64_REG_Q0_Q1,
|
||||
ARM64_REG_Q1_Q2,
|
||||
ARM64_REG_Q2_Q3,
|
||||
ARM64_REG_Q3_Q4,
|
||||
ARM64_REG_Q4_Q5,
|
||||
ARM64_REG_Q5_Q6,
|
||||
ARM64_REG_Q6_Q7,
|
||||
ARM64_REG_Q7_Q8,
|
||||
ARM64_REG_Q8_Q9,
|
||||
ARM64_REG_Q9_Q10,
|
||||
ARM64_REG_Q10_Q11,
|
||||
ARM64_REG_Q11_Q12,
|
||||
ARM64_REG_Q12_Q13,
|
||||
ARM64_REG_Q13_Q14,
|
||||
ARM64_REG_Q14_Q15,
|
||||
ARM64_REG_Q15_Q16,
|
||||
ARM64_REG_Q16_Q17,
|
||||
ARM64_REG_Q17_Q18,
|
||||
ARM64_REG_Q18_Q19,
|
||||
ARM64_REG_Q19_Q20,
|
||||
ARM64_REG_Q20_Q21,
|
||||
ARM64_REG_Q21_Q22,
|
||||
ARM64_REG_Q22_Q23,
|
||||
ARM64_REG_Q23_Q24,
|
||||
ARM64_REG_Q24_Q25,
|
||||
ARM64_REG_Q25_Q26,
|
||||
ARM64_REG_Q26_Q27,
|
||||
ARM64_REG_Q27_Q28,
|
||||
ARM64_REG_Q28_Q29,
|
||||
ARM64_REG_Q29_Q30,
|
||||
ARM64_REG_Q30_Q31,
|
||||
ARM64_REG_Q31_Q0,
|
||||
ARM64_REG_D0_D1_D2,
|
||||
ARM64_REG_D1_D2_D3,
|
||||
ARM64_REG_D2_D3_D4,
|
||||
ARM64_REG_D3_D4_D5,
|
||||
ARM64_REG_D4_D5_D6,
|
||||
ARM64_REG_D5_D6_D7,
|
||||
ARM64_REG_D6_D7_D8,
|
||||
ARM64_REG_D7_D8_D9,
|
||||
ARM64_REG_D8_D9_D10,
|
||||
ARM64_REG_D9_D10_D11,
|
||||
ARM64_REG_D10_D11_D12,
|
||||
ARM64_REG_D11_D12_D13,
|
||||
ARM64_REG_D12_D13_D14,
|
||||
ARM64_REG_D13_D14_D15,
|
||||
ARM64_REG_D14_D15_D16,
|
||||
ARM64_REG_D15_D16_D17,
|
||||
ARM64_REG_D16_D17_D18,
|
||||
ARM64_REG_D17_D18_D19,
|
||||
ARM64_REG_D18_D19_D20,
|
||||
ARM64_REG_D19_D20_D21,
|
||||
ARM64_REG_D20_D21_D22,
|
||||
ARM64_REG_D21_D22_D23,
|
||||
ARM64_REG_D22_D23_D24,
|
||||
ARM64_REG_D23_D24_D25,
|
||||
ARM64_REG_D24_D25_D26,
|
||||
ARM64_REG_D25_D26_D27,
|
||||
ARM64_REG_D26_D27_D28,
|
||||
ARM64_REG_D27_D28_D29,
|
||||
ARM64_REG_D28_D29_D30,
|
||||
ARM64_REG_D29_D30_D31,
|
||||
ARM64_REG_D30_D31_D0,
|
||||
ARM64_REG_D31_D0_D1,
|
||||
ARM64_REG_Q0_Q1_Q2,
|
||||
ARM64_REG_Q1_Q2_Q3,
|
||||
ARM64_REG_Q2_Q3_Q4,
|
||||
ARM64_REG_Q3_Q4_Q5,
|
||||
ARM64_REG_Q4_Q5_Q6,
|
||||
ARM64_REG_Q5_Q6_Q7,
|
||||
ARM64_REG_Q6_Q7_Q8,
|
||||
ARM64_REG_Q7_Q8_Q9,
|
||||
ARM64_REG_Q8_Q9_Q10,
|
||||
ARM64_REG_Q9_Q10_Q11,
|
||||
ARM64_REG_Q10_Q11_Q12,
|
||||
ARM64_REG_Q11_Q12_Q13,
|
||||
ARM64_REG_Q12_Q13_Q14,
|
||||
ARM64_REG_Q13_Q14_Q15,
|
||||
ARM64_REG_Q14_Q15_Q16,
|
||||
ARM64_REG_Q15_Q16_Q17,
|
||||
ARM64_REG_Q16_Q17_Q18,
|
||||
ARM64_REG_Q17_Q18_Q19,
|
||||
ARM64_REG_Q18_Q19_Q20,
|
||||
ARM64_REG_Q19_Q20_Q21,
|
||||
ARM64_REG_Q20_Q21_Q22,
|
||||
ARM64_REG_Q21_Q22_Q23,
|
||||
ARM64_REG_Q22_Q23_Q24,
|
||||
ARM64_REG_Q23_Q24_Q25,
|
||||
ARM64_REG_Q24_Q25_Q26,
|
||||
ARM64_REG_Q25_Q26_Q27,
|
||||
ARM64_REG_Q26_Q27_Q28,
|
||||
ARM64_REG_Q27_Q28_Q29,
|
||||
ARM64_REG_Q28_Q29_Q30,
|
||||
ARM64_REG_Q29_Q30_Q31,
|
||||
ARM64_REG_Q30_Q31_Q0,
|
||||
ARM64_REG_Q31_Q0_Q1,
|
||||
ARM64_REG_D0_D1_D2_D3,
|
||||
ARM64_REG_D1_D2_D3_D4,
|
||||
ARM64_REG_D2_D3_D4_D5,
|
||||
ARM64_REG_D3_D4_D5_D6,
|
||||
ARM64_REG_D4_D5_D6_D7,
|
||||
ARM64_REG_D5_D6_D7_D8,
|
||||
ARM64_REG_D6_D7_D8_D9,
|
||||
ARM64_REG_D7_D8_D9_D10,
|
||||
ARM64_REG_D8_D9_D10_D11,
|
||||
ARM64_REG_D9_D10_D11_D12,
|
||||
ARM64_REG_D10_D11_D12_D13,
|
||||
ARM64_REG_D11_D12_D13_D14,
|
||||
ARM64_REG_D12_D13_D14_D15,
|
||||
ARM64_REG_D13_D14_D15_D16,
|
||||
ARM64_REG_D14_D15_D16_D17,
|
||||
ARM64_REG_D15_D16_D17_D18,
|
||||
ARM64_REG_D16_D17_D18_D19,
|
||||
ARM64_REG_D17_D18_D19_D20,
|
||||
ARM64_REG_D18_D19_D20_D21,
|
||||
ARM64_REG_D19_D20_D21_D22,
|
||||
ARM64_REG_D20_D21_D22_D23,
|
||||
ARM64_REG_D21_D22_D23_D24,
|
||||
ARM64_REG_D22_D23_D24_D25,
|
||||
ARM64_REG_D23_D24_D25_D26,
|
||||
ARM64_REG_D24_D25_D26_D27,
|
||||
ARM64_REG_D25_D26_D27_D28,
|
||||
ARM64_REG_D26_D27_D28_D29,
|
||||
ARM64_REG_D27_D28_D29_D30,
|
||||
ARM64_REG_D28_D29_D30_D31,
|
||||
ARM64_REG_D29_D30_D31_D0,
|
||||
ARM64_REG_D30_D31_D0_D1,
|
||||
ARM64_REG_D31_D0_D1_D2,
|
||||
ARM64_REG_Q0_Q1_Q2_Q3,
|
||||
ARM64_REG_Q1_Q2_Q3_Q4,
|
||||
ARM64_REG_Q2_Q3_Q4_Q5,
|
||||
ARM64_REG_Q3_Q4_Q5_Q6,
|
||||
ARM64_REG_Q4_Q5_Q6_Q7,
|
||||
ARM64_REG_Q5_Q6_Q7_Q8,
|
||||
ARM64_REG_Q6_Q7_Q8_Q9,
|
||||
ARM64_REG_Q7_Q8_Q9_Q10,
|
||||
ARM64_REG_Q8_Q9_Q10_Q11,
|
||||
ARM64_REG_Q9_Q10_Q11_Q12,
|
||||
ARM64_REG_Q10_Q11_Q12_Q13,
|
||||
ARM64_REG_Q11_Q12_Q13_Q14,
|
||||
ARM64_REG_Q12_Q13_Q14_Q15,
|
||||
ARM64_REG_Q13_Q14_Q15_Q16,
|
||||
ARM64_REG_Q14_Q15_Q16_Q17,
|
||||
ARM64_REG_Q15_Q16_Q17_Q18,
|
||||
ARM64_REG_Q16_Q17_Q18_Q19,
|
||||
ARM64_REG_Q17_Q18_Q19_Q20,
|
||||
ARM64_REG_Q18_Q19_Q20_Q21,
|
||||
ARM64_REG_Q19_Q20_Q21_Q22,
|
||||
ARM64_REG_Q20_Q21_Q22_Q23,
|
||||
ARM64_REG_Q21_Q22_Q23_Q24,
|
||||
ARM64_REG_Q22_Q23_Q24_Q25,
|
||||
ARM64_REG_Q23_Q24_Q25_Q26,
|
||||
ARM64_REG_Q24_Q25_Q26_Q27,
|
||||
ARM64_REG_Q25_Q26_Q27_Q28,
|
||||
ARM64_REG_Q26_Q27_Q28_Q29,
|
||||
ARM64_REG_Q27_Q28_Q29_Q30,
|
||||
ARM64_REG_Q28_Q29_Q30_Q31,
|
||||
ARM64_REG_Q29_Q30_Q31_Q0,
|
||||
ARM64_REG_Q30_Q31_Q0_Q1,
|
||||
ARM64_REG_Q31_Q0_Q1_Q2,
|
||||
|
||||
ARM64_REG_MAX, // <-- mark the end of the list of registers
|
||||
} arm64_reg;
|
||||
|
||||
//> ARM64 instruction
|
||||
typedef enum arm64_insn {
|
||||
ARM64_INS_INVALID = 0,
|
||||
|
||||
ARM64_INS_ABS,
|
||||
ARM64_INS_ADC,
|
||||
ARM64_INS_ADDHN2,
|
||||
ARM64_INS_ADDHN,
|
||||
ARM64_INS_ADDP,
|
||||
ARM64_INS_ADDV,
|
||||
ARM64_INS_ADD,
|
||||
ARM64_INS_CMN,
|
||||
ARM64_INS_ADRP,
|
||||
ARM64_INS_ADR,
|
||||
ARM64_INS_AESD,
|
||||
ARM64_INS_AESE,
|
||||
ARM64_INS_AESIMC,
|
||||
ARM64_INS_AESMC,
|
||||
ARM64_INS_AND,
|
||||
ARM64_INS_ASR,
|
||||
ARM64_INS_AT,
|
||||
|
|
@ -380,6 +580,7 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_CMLT,
|
||||
ARM64_INS_CMP,
|
||||
ARM64_INS_CMTST,
|
||||
ARM64_INS_CNT,
|
||||
ARM64_INS_CRC32B,
|
||||
ARM64_INS_CRC32CB,
|
||||
ARM64_INS_CRC32CH,
|
||||
|
|
@ -399,10 +600,12 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_DMB,
|
||||
ARM64_INS_DRPS,
|
||||
ARM64_INS_DSB,
|
||||
ARM64_INS_DUP,
|
||||
ARM64_INS_EON,
|
||||
ARM64_INS_EOR,
|
||||
ARM64_INS_ERET,
|
||||
ARM64_INS_EXTR,
|
||||
ARM64_INS_EXT,
|
||||
ARM64_INS_FABD,
|
||||
ARM64_INS_FABS,
|
||||
ARM64_INS_FACGE,
|
||||
|
|
@ -421,24 +624,34 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_FCSEL,
|
||||
ARM64_INS_FCVTAS,
|
||||
ARM64_INS_FCVTAU,
|
||||
ARM64_INS_FCVTL,
|
||||
ARM64_INS_FCVTL2,
|
||||
ARM64_INS_FCVTMS,
|
||||
ARM64_INS_FCVTMU,
|
||||
ARM64_INS_FCVTN,
|
||||
ARM64_INS_FCVTN2,
|
||||
ARM64_INS_FCVTNS,
|
||||
ARM64_INS_FCVTNU,
|
||||
ARM64_INS_FCVTPS,
|
||||
ARM64_INS_FCVTPU,
|
||||
ARM64_INS_FCVTXN,
|
||||
ARM64_INS_FCVTXN2,
|
||||
ARM64_INS_FCVTZS,
|
||||
ARM64_INS_FCVTZU,
|
||||
ARM64_INS_FCVT,
|
||||
ARM64_INS_FDIV,
|
||||
ARM64_INS_FMADD,
|
||||
ARM64_INS_FMAXNMP,
|
||||
ARM64_INS_FMAXNMV,
|
||||
ARM64_INS_FMAXNM,
|
||||
ARM64_INS_FMAXP,
|
||||
ARM64_INS_FMAXV,
|
||||
ARM64_INS_FMAX,
|
||||
ARM64_INS_FMINNMP,
|
||||
ARM64_INS_FMINNMV,
|
||||
ARM64_INS_FMINNM,
|
||||
ARM64_INS_FMINP,
|
||||
ARM64_INS_FMINV,
|
||||
ARM64_INS_FMIN,
|
||||
ARM64_INS_FMLA,
|
||||
ARM64_INS_FMLS,
|
||||
|
|
@ -450,7 +663,9 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_FNMADD,
|
||||
ARM64_INS_FNMSUB,
|
||||
ARM64_INS_FNMUL,
|
||||
ARM64_INS_FRECPE,
|
||||
ARM64_INS_FRECPS,
|
||||
ARM64_INS_FRECPX,
|
||||
ARM64_INS_FRINTA,
|
||||
ARM64_INS_FRINTI,
|
||||
ARM64_INS_FRINTM,
|
||||
|
|
@ -458,6 +673,7 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_FRINTP,
|
||||
ARM64_INS_FRINTX,
|
||||
ARM64_INS_FRINTZ,
|
||||
ARM64_INS_FRSQRTE,
|
||||
ARM64_INS_FRSQRTS,
|
||||
ARM64_INS_FSQRT,
|
||||
ARM64_INS_FSUB,
|
||||
|
|
@ -467,6 +683,14 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_IC,
|
||||
ARM64_INS_INS,
|
||||
ARM64_INS_ISB,
|
||||
ARM64_INS_LD1,
|
||||
ARM64_INS_LD1R,
|
||||
ARM64_INS_LD2,
|
||||
ARM64_INS_LD2R,
|
||||
ARM64_INS_LD3,
|
||||
ARM64_INS_LD3R,
|
||||
ARM64_INS_LD4,
|
||||
ARM64_INS_LD4R,
|
||||
ARM64_INS_LDARB,
|
||||
ARM64_INS_LDAR,
|
||||
ARM64_INS_LDARH,
|
||||
|
|
@ -525,6 +749,8 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_MUL,
|
||||
ARM64_INS_MVNI,
|
||||
ARM64_INS_MVN,
|
||||
ARM64_INS_NEG,
|
||||
ARM64_INS_NOT,
|
||||
ARM64_INS_ORN,
|
||||
ARM64_INS_ORR,
|
||||
ARM64_INS_PMULL2,
|
||||
|
|
@ -542,6 +768,7 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_RET,
|
||||
ARM64_INS_REV16,
|
||||
ARM64_INS_REV32,
|
||||
ARM64_INS_REV64,
|
||||
ARM64_INS_REV,
|
||||
ARM64_INS_ROR,
|
||||
ARM64_INS_RSHRN2,
|
||||
|
|
@ -554,7 +781,10 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SABDL2,
|
||||
ARM64_INS_SABDL,
|
||||
ARM64_INS_SABD,
|
||||
ARM64_INS_SADALP,
|
||||
ARM64_INS_SADDL2,
|
||||
ARM64_INS_SADDLP,
|
||||
ARM64_INS_SADDLV,
|
||||
ARM64_INS_SADDL,
|
||||
ARM64_INS_SADDW2,
|
||||
ARM64_INS_SADDW,
|
||||
|
|
@ -564,7 +794,19 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SBFX,
|
||||
ARM64_INS_SCVTF,
|
||||
ARM64_INS_SDIV,
|
||||
ARM64_INS_SHA1C,
|
||||
ARM64_INS_SHA1H,
|
||||
ARM64_INS_SHA1M,
|
||||
ARM64_INS_SHA1P,
|
||||
ARM64_INS_SHA1SU0,
|
||||
ARM64_INS_SHA1SU1,
|
||||
ARM64_INS_SHA256H,
|
||||
ARM64_INS_SHA256H2,
|
||||
ARM64_INS_SHA256SU0,
|
||||
ARM64_INS_SHA256SU1,
|
||||
ARM64_INS_SHADD,
|
||||
ARM64_INS_SHLL2,
|
||||
ARM64_INS_SHLL,
|
||||
ARM64_INS_SHL,
|
||||
ARM64_INS_SHRN2,
|
||||
ARM64_INS_SHRN,
|
||||
|
|
@ -572,9 +814,11 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SLI,
|
||||
ARM64_INS_SMADDL,
|
||||
ARM64_INS_SMAXP,
|
||||
ARM64_INS_SMAXV,
|
||||
ARM64_INS_SMAX,
|
||||
ARM64_INS_SMC,
|
||||
ARM64_INS_SMINP,
|
||||
ARM64_INS_SMINV,
|
||||
ARM64_INS_SMIN,
|
||||
ARM64_INS_SMLAL2,
|
||||
ARM64_INS_SMLAL,
|
||||
|
|
@ -585,6 +829,7 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SMULH,
|
||||
ARM64_INS_SMULL2,
|
||||
ARM64_INS_SMULL,
|
||||
ARM64_INS_SQABS,
|
||||
ARM64_INS_SQADD,
|
||||
ARM64_INS_SQDMLAL2,
|
||||
ARM64_INS_SQDMLAL,
|
||||
|
|
@ -593,15 +838,20 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SQDMULH,
|
||||
ARM64_INS_SQDMULL2,
|
||||
ARM64_INS_SQDMULL,
|
||||
ARM64_INS_SQNEG,
|
||||
ARM64_INS_SQRDMULH,
|
||||
ARM64_INS_SQRSHL,
|
||||
ARM64_INS_SQRSHRN2,
|
||||
ARM64_INS_SQRSHRN,
|
||||
ARM64_INS_SQRSHRN2,
|
||||
ARM64_INS_SQSHLU,
|
||||
ARM64_INS_SQSHL,
|
||||
ARM64_INS_SQSHRN2,
|
||||
ARM64_INS_SQSHRN,
|
||||
ARM64_INS_SQSHRN2,
|
||||
ARM64_INS_SQSUB,
|
||||
ARM64_INS_SQXTN,
|
||||
ARM64_INS_SQXTN2,
|
||||
ARM64_INS_SQXTUN,
|
||||
ARM64_INS_SQXTUN2,
|
||||
ARM64_INS_SRHADD,
|
||||
ARM64_INS_SRI,
|
||||
ARM64_INS_SRSHL,
|
||||
|
|
@ -616,6 +866,10 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SSUBL,
|
||||
ARM64_INS_SSUBW2,
|
||||
ARM64_INS_SSUBW,
|
||||
ARM64_INS_ST1,
|
||||
ARM64_INS_ST2,
|
||||
ARM64_INS_ST3,
|
||||
ARM64_INS_ST4,
|
||||
ARM64_INS_STLRB,
|
||||
ARM64_INS_STLR,
|
||||
ARM64_INS_STLRH,
|
||||
|
|
@ -630,15 +884,20 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SUBHN2,
|
||||
ARM64_INS_SUBHN,
|
||||
ARM64_INS_SUB,
|
||||
ARM64_INS_SUQADD,
|
||||
ARM64_INS_SVC,
|
||||
ARM64_INS_SXTB,
|
||||
ARM64_INS_SXTH,
|
||||
ARM64_INS_SXTW,
|
||||
ARM64_INS_SYSL,
|
||||
ARM64_INS_SYS,
|
||||
ARM64_INS_TBL,
|
||||
ARM64_INS_TBNZ,
|
||||
ARM64_INS_TBX,
|
||||
ARM64_INS_TBZ,
|
||||
ARM64_INS_TLBI,
|
||||
ARM64_INS_TRN1,
|
||||
ARM64_INS_TRN2,
|
||||
ARM64_INS_TST,
|
||||
ARM64_INS_UABAL2,
|
||||
ARM64_INS_UABAL,
|
||||
|
|
@ -646,7 +905,10 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_UABDL2,
|
||||
ARM64_INS_UABDL,
|
||||
ARM64_INS_UABD,
|
||||
ARM64_INS_UADALP,
|
||||
ARM64_INS_UADDL2,
|
||||
ARM64_INS_UADDLP,
|
||||
ARM64_INS_UADDLV,
|
||||
ARM64_INS_UADDL,
|
||||
ARM64_INS_UADDW2,
|
||||
ARM64_INS_UADDW,
|
||||
|
|
@ -659,8 +921,10 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_UHSUB,
|
||||
ARM64_INS_UMADDL,
|
||||
ARM64_INS_UMAXP,
|
||||
ARM64_INS_UMAXV,
|
||||
ARM64_INS_UMAX,
|
||||
ARM64_INS_UMINP,
|
||||
ARM64_INS_UMINV,
|
||||
ARM64_INS_UMIN,
|
||||
ARM64_INS_UMLAL2,
|
||||
ARM64_INS_UMLAL,
|
||||
|
|
@ -673,20 +937,25 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_UMULL,
|
||||
ARM64_INS_UQADD,
|
||||
ARM64_INS_UQRSHL,
|
||||
ARM64_INS_UQRSHRN2,
|
||||
ARM64_INS_UQRSHRN,
|
||||
ARM64_INS_UQRSHRN2,
|
||||
ARM64_INS_UQSHL,
|
||||
ARM64_INS_UQSHRN2,
|
||||
ARM64_INS_UQSHRN,
|
||||
ARM64_INS_UQSHRN2,
|
||||
ARM64_INS_UQSUB,
|
||||
ARM64_INS_UQXTN,
|
||||
ARM64_INS_UQXTN2,
|
||||
ARM64_INS_URECPE,
|
||||
ARM64_INS_URHADD,
|
||||
ARM64_INS_URSHL,
|
||||
ARM64_INS_URSHR,
|
||||
ARM64_INS_URSQRTE,
|
||||
ARM64_INS_URSRA,
|
||||
ARM64_INS_USHLL2,
|
||||
ARM64_INS_USHLL,
|
||||
ARM64_INS_USHL,
|
||||
ARM64_INS_USHR,
|
||||
ARM64_INS_USQADD,
|
||||
ARM64_INS_USRA,
|
||||
ARM64_INS_USUBL2,
|
||||
ARM64_INS_USUBL,
|
||||
|
|
@ -694,6 +963,12 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_USUBW,
|
||||
ARM64_INS_UXTB,
|
||||
ARM64_INS_UXTH,
|
||||
ARM64_INS_UZP1,
|
||||
ARM64_INS_UZP2,
|
||||
ARM64_INS_XTN,
|
||||
ARM64_INS_XTN2,
|
||||
ARM64_INS_ZIP1,
|
||||
ARM64_INS_ZIP2,
|
||||
|
||||
// alias insn
|
||||
ARM64_INS_MNEG,
|
||||
|
|
@ -707,19 +982,21 @@ typedef enum arm64_insn {
|
|||
ARM64_INS_SEV,
|
||||
ARM64_INS_SEVL,
|
||||
ARM64_INS_NGC,
|
||||
ARM64_INS_NEG,
|
||||
|
||||
ARM64_INS_MAX,
|
||||
ARM64_INS_MAX, // <-- mark the end of the list of insn
|
||||
} arm64_insn;
|
||||
|
||||
//> Group of ARM64 instructions
|
||||
typedef enum arm64_insn_group {
|
||||
ARM64_GRP_INVALID = 0,
|
||||
|
||||
ARM64_GRP_CRYPTO,
|
||||
ARM64_GRP_FPARMV8,
|
||||
ARM64_GRP_NEON,
|
||||
|
||||
ARM64_GRP_JUMP, // all jump instructions (conditional+direct+indirect jumps)
|
||||
|
||||
ARM64_GRP_MAX,
|
||||
ARM64_GRP_MAX, // <-- mark the end of the list of groups
|
||||
} arm64_insn_group;
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
|
|
|||
Loading…
Reference in New Issue