From 750ba014663396200788553c56baf045f53e32da Mon Sep 17 00:00:00 2001 From: Travis Finkenauer Date: Wed, 22 May 2019 21:25:36 -0400 Subject: [PATCH] [RISCV] Use CS_ASSERT (#1493) * makefile: set CAPSTONE_DEBUG for debug build Also fix long longs * riscv: replace assert with CS_ASSERT * cmake: add CAPSTONE_DEBUG option --- CMakeLists.txt | 5 +++++ COMPILE_CMAKE.TXT | 1 + arch/RISCV/RISCVBaseInfo.h | 4 ++-- arch/RISCV/RISCVDisassembler.c | 10 +++++----- arch/RISCV/RISCVGenAsmWriter.inc | 20 ++++++++++---------- arch/RISCV/RISCVGenDisassemblerTables.inc | 12 ++++++------ arch/RISCV/RISCVInstPrinter.c | 16 ++++++++-------- make.sh | 14 ++++++++++++-- 8 files changed, 49 insertions(+), 33 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 43179999..e9e7960e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -28,6 +28,7 @@ option(CAPSTONE_BUILD_TESTS "Build tests" ON) option(CAPSTONE_BUILD_CSTOOL "Build cstool" ON) option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON) option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by default" ON) +option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF) set(SUPPORTED_ARCHITECTURES ARM ARM64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV) set(SUPPORTED_ARCHITECTURE_LABELS ARM ARM64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV) @@ -77,6 +78,10 @@ if (CAPSTONE_X86_ATT_DISABLE) add_definitions(-DCAPSTONE_X86_ATT_DISABLE) endif () +if (CAPSTONE_DEBUG) + add_definitions(-DCAPSTONE_DEBUG) +endif () + ## sources set(SOURCES_ENGINE cs.c diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT index 0220179c..bd9d1985 100644 --- a/COMPILE_CMAKE.TXT +++ b/COMPILE_CMAKE.TXT @@ -48,6 +48,7 @@ Get CMake for free from http://www.cmake.org. - CAPSTONE_BUILD_DIET: change this to ON to make the binaries more compact. - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller. - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86. + - CAPSTONE_DEBUG: change this to ON to enable extra debug assertions. By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE modes are disabled. To use your own memory allocations, turn ON both DIET & diff --git a/arch/RISCV/RISCVBaseInfo.h b/arch/RISCV/RISCVBaseInfo.h index 35ace558..e6ae1fcb 100644 --- a/arch/RISCV/RISCVBaseInfo.h +++ b/arch/RISCV/RISCVBaseInfo.h @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #ifndef CS_RISCVBASEINFO_H #define CS_RISCVBASEINFO_H -#include +#include "../../cs_priv.h" //#include "RISCVMCTargetDesc.h" @@ -72,7 +72,7 @@ inline static const char *roundingModeToString(enum RoundingMode RndMode) { switch (RndMode) { default: - assert(0 && "Unknown floating point rounding mode"); + CS_ASSERT(0 && "Unknown floating point rounding mode"); case RISCVFPRndMode_RNE: return "rne"; case RISCVFPRndMode_RTZ: diff --git a/arch/RISCV/RISCVDisassembler.c b/arch/RISCV/RISCVDisassembler.c index 4330a4a9..9b0c089d 100644 --- a/arch/RISCV/RISCVDisassembler.c +++ b/arch/RISCV/RISCVDisassembler.c @@ -224,7 +224,7 @@ static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { - //assert(isUInt(Imm) && "Invalid immediate"); + //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); addImplySP(Inst, Address, Decoder); //Inst.addOperand(MCOperand::createImm(Imm)); MCOperand_CreateImm0(Inst, Imm); @@ -245,7 +245,7 @@ static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder, unsigned N) { - //assert(isUInt(Imm) && "Invalid immediate"); + //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); addImplySP(Inst, Address, Decoder); // Sign-extend the number in the bottom N bits of Imm //Inst.addOperand(MCOperand::createImm(SignExtend64(Imm))); @@ -268,7 +268,7 @@ static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm, const void *Decoder, unsigned N) { - //assert(isUInt(Imm) && "Invalid immediate"); + //CS_ASSERT(isUInt(Imm) && "Invalid immediate"); // Sign-extend the number in the bottom N bits of Imm after accounting for // the fact that the N bit immediate is stored in N-1 bits (the LSB is // always zero) @@ -281,7 +281,7 @@ static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { - //assert(isUInt<6>(Imm) && "Invalid immediate"); + //CS_ASSERT(isUInt<6>(Imm) && "Invalid immediate"); if (Imm > 31) { Imm = (SignExtend64(Imm, 6) & 0xfffff); } @@ -294,7 +294,7 @@ static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm, int64_t Address, const void *Decoder) { - //assert(isUInt<3>(Imm) && "Invalid immediate"); + //CS_ASSERT(isUInt<3>(Imm) && "Invalid immediate"); if (!RISCVFPRndMode_isValidRoundingMode(Imm)) return MCDisassembler_Fail; diff --git a/arch/RISCV/RISCVGenAsmWriter.inc b/arch/RISCV/RISCVGenAsmWriter.inc index f78d91dc..220dd8ee 100644 --- a/arch/RISCV/RISCVGenAsmWriter.inc +++ b/arch/RISCV/RISCVGenAsmWriter.inc @@ -1190,7 +1190,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) uint32_t Bits = 0; Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0; Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16; - // assert(Bits != 0 && "Cannot print this instruction."); + CS_ASSERT(Bits != 0 && "Cannot print this instruction."); #ifndef CAPSTONE_DIET SStream_concat0(O, AsmStrs+(Bits & 4095)-1); #endif @@ -1198,7 +1198,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 0 encoded into 2 bits for 4 unique commands. switch ((Bits >> 12) & 3) { - default: assert(0 && "Invalid command number."); + default: CS_ASSERT(0 && "Invalid command number."); case 0: // DBG_VALUE, DBG_LABEL, BUNDLE, LIFETIME_START, LIFETIME_END, FENTRY_CAL... return; @@ -1226,7 +1226,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 1 encoded into 2 bits for 3 unique commands. switch ((Bits >> 14) & 3) { - default: assert(0 && "Invalid command number."); + default: CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoCALL, PseudoTAIL, C_J, C_JAL, C_JALR, C_JR return; @@ -1247,7 +1247,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 2 encoded into 2 bits for 3 unique commands. switch ((Bits >> 16) & 3) { - default: assert(0 && "Invalid command number."); + default: CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoLA, PseudoLI, PseudoLLA, ADD, ADDI, ADDIW, ADDW, AND, ANDI, AUIP... printOperand(MI, 1, O); @@ -1268,7 +1268,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) // Fragment 3 encoded into 2 bits for 4 unique commands. switch ((Bits >> 18) & 3) { - default: assert(0 && "Invalid command number."); + default: CS_ASSERT(0 && "Invalid command number."); case 0: // PseudoLA, PseudoLI, PseudoLLA, AUIPC, C_BEQZ, C_BNEZ, C_LI, C_LUI, C_M... return; @@ -1337,7 +1337,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) static const char * getRegisterName(unsigned RegNo, unsigned AltIdx) { - assert(RegNo && RegNo < 97 && "Invalid register number!"); + CS_ASSERT(RegNo && RegNo < 97 && "Invalid register number!"); #ifndef CAPSTONE_DIET static const char AsmStrsABIRegAltName[] = { @@ -1468,13 +1468,13 @@ getRegisterName(unsigned RegNo, unsigned AltIdx) }; switch(AltIdx) { - default: assert(0 && "Invalid register alt name index!"); + default: CS_ASSERT(0 && "Invalid register alt name index!"); case RISCV_ABIRegAltName: - assert(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && + CS_ASSERT(*(AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]) && "Invalid alt name index for register!"); return AsmStrsABIRegAltName+RegAsmOffsetABIRegAltName[RegNo-1]; case RISCV_NoRegAltName: - assert(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && + CS_ASSERT(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) && "Invalid alt name index for register!"); return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]; } @@ -2608,7 +2608,7 @@ static void printCustomAliasOperand( SStream *OS) { switch (PrintMethodIdx) { default: - assert(0 && "Unknown PrintMethod kind"); + CS_ASSERT(0 && "Unknown PrintMethod kind"); break; case 0: printCSRSystemRegister(MI, OpIdx, OS); diff --git a/arch/RISCV/RISCVGenDisassemblerTables.inc b/arch/RISCV/RISCVGenDisassemblerTables.inc index 21ff4ff0..101728d3 100644 --- a/arch/RISCV/RISCVGenDisassemblerTables.inc +++ b/arch/RISCV/RISCVGenDisassemblerTables.inc @@ -11,7 +11,7 @@ #include "../../MCInst.h" #include "../../LEB128.h" -#include +#include "../../cs_priv.h" // Helper functions for extracting fields from encoded instructions. // InsnType must either be integral or an APInt-like object that must: @@ -1071,7 +1071,7 @@ static const uint8_t DecoderTableRISCV32Only_16[] = { static bool checkDecoderPredicate(unsigned Idx, uint64_t Bits) { switch (Idx) { - default: assert(0 && "Invalid index!"); + default: CS_ASSERT(0 && "Invalid index!"); case 0: return (Bits & RISCV_FeatureStdExtC); case 1: @@ -1110,7 +1110,7 @@ static DecodeStatus fname(DecodeStatus S, unsigned Idx, InsnType insn, MCInst *M *DecodeComplete = true;\ InsnType tmp; \ switch (Idx) { \ - default: assert(0 && "Invalid index!");\ + default: CS_ASSERT(0 && "Invalid index!");\ case 0: \ return S; \ case 1: \ @@ -1722,7 +1722,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI,\ MCInst_setOpcode(MI, Opc);\ bool DecodeComplete;\ S = decoder(S, DecodeIdx, insn, MI, Address, DisAsm, &DecodeComplete);\ - assert(DecodeComplete);\ + CS_ASSERT(DecodeComplete);\ \ return S;\ }\ @@ -1745,7 +1745,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI,\ *MI = TmpMI;\ return S;\ } else {\ - assert(S == MCDisassembler_Fail);\ + CS_ASSERT(S == MCDisassembler_Fail);\ Ptr += NumToSkip;\ S = MCDisassembler_Success;\ }\ @@ -1767,7 +1767,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI,\ }\ }\ }\ - assert(0 && "bogosity detected in disassembler state machine!");\ + CS_ASSERT(0 && "bogosity detected in disassembler state machine!");\ } // For RISCV instruction is 32 bits. diff --git a/arch/RISCV/RISCVInstPrinter.c b/arch/RISCV/RISCVInstPrinter.c index eba3298b..51d7b574 100644 --- a/arch/RISCV/RISCVInstPrinter.c +++ b/arch/RISCV/RISCVInstPrinter.c @@ -57,15 +57,15 @@ static void fixDetailOfEffectiveAddr(MCInst *MI) unsigned reg = 0; int64_t imm = 0; - assert(3 == MI->flat_insn->detail->riscv.op_count); - assert(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[0].type); + CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count); + CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[0].type); if (RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[1].type) { - assert(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[2].type); + CS_ASSERT(RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[2].type); imm = MI->flat_insn->detail->riscv.operands[1].imm; reg = MI->flat_insn->detail->riscv.operands[2].reg; } else if (RISCV_OP_REG == MI->flat_insn->detail->riscv.operands[1].type) { - assert(RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[2].type); + CS_ASSERT(RISCV_OP_IMM == MI->flat_insn->detail->riscv.operands[2].type); reg = MI->flat_insn->detail->riscv.operands[1].reg; imm = MI->flat_insn->detail->riscv.operands[2].imm; } @@ -129,7 +129,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) MI->flat_insn->detail->riscv.op_count++; } } else { - assert(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); + CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand"); Imm = MCOperand_getImm(MO); if (Imm >= 0) { if (Imm > HEX_THRESHOLD) @@ -150,7 +150,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) } } - //assert(MO.isExpr() && "Unknown operand kind in printOperand"); + //CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand"); return; } @@ -161,7 +161,7 @@ static void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, { // TODO: Not yeat implementated. return; - //assert (0 && "CSR system register hav't support."); + //CS_ASSERT (0 && "CSR system register hav't support."); #if 0 unsigned Imm = MI->getOperand(OpNo).getImm(); auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm); @@ -175,7 +175,7 @@ static void printCSRSystemRegister(const MCInst *MI, unsigned OpNo, static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O) { unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, OpNo)); - //assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); + //CS_ASSERT (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg"); if ((FenceArg & RISCVFenceField_I) != 0) SStream_concat0(O, "i"); diff --git a/make.sh b/make.sh index 1b715080..ddc1791c 100755 --- a/make.sh +++ b/make.sh @@ -111,7 +111,12 @@ TARGET="$1" case "$TARGET" in "" | "default" ) ${MAKE} "$@";; - "debug" ) CAPSTONE_USE_SYS_DYN_MEM=yes CAPSTONE_STATIC=yes CFLAGS='-O0 -g -fsanitize=address' LDFLAGS='-fsanitize=address' ${MAKE} "$@";; + "debug" ) \ + CAPSTONE_USE_SYS_DYN_MEM=yes \ + CAPSTONE_STATIC=yes \ + CFLAGS='-DCAPSTONE_DEBUG -O0 -g -fsanitize=address' \ + LDFLAGS='-fsanitize=address' \ + ${MAKE} "$@";; "install" ) install;; "uninstall" ) uninstall;; "nix32" ) CFLAGS=-m32 LDFLAGS=-m32 ${MAKE} "$@";; @@ -127,7 +132,12 @@ case "$TARGET" in "ios_armv7" ) build_iOS armv7 "$@";; "ios_armv7s" ) build_iOS armv7s "$@";; "ios_arm64" ) build_iOS arm64 "$@";; - "osx-kernel" ) CAPSTONE_USE_SYS_DYN_MEM=yes CAPSTONE_HAS_OSXKERNEL=yes CAPSTONE_ARCHS=x86 CAPSTONE_SHARED=no CAPSTONE_BUILD_CORE_ONLY=yes ${MAKE} "$@";; + "osx-kernel" ) CAPSTONE_USE_SYS_DYN_MEM=yes \ + CAPSTONE_HAS_OSXKERNEL=yes \ + CAPSTONE_ARCHS=x86 \ + CAPSTONE_SHARED=no \ + CAPSTONE_BUILD_CORE_ONLY=yes \ + ${MAKE} "$@";; "mac-universal" ) MACOS_UNIVERSAL=yes ${MAKE} "$@";; "mac-universal-no" ) MACOS_UNIVERSAL=no ${MAKE} "$@";; * )