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- Resolve some casting issues with Visual Studio. (#1007)

This commit is contained in:
Matt Suiche 2017-09-05 19:15:13 +04:00 committed by Nguyen Anh Quynh
parent 60f17f5b70
commit 782d339fc7
3 changed files with 13 additions and 13 deletions
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14
arch/AArch64/AArch64Disassembler.c
View File

@ -1616,11 +1616,11 @@ static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
uint32_t insn, uint64_t Addr,
void *Decoder)
{
uint64_t op1 = fieldFromInstruction(insn, 16, 3);
uint64_t op2 = fieldFromInstruction(insn, 5, 3);
uint64_t crm = fieldFromInstruction(insn, 8, 4);
uint32_t op1 = fieldFromInstruction(insn, 16, 3);
uint32_t op2 = fieldFromInstruction(insn, 5, 3);
uint32_t crm = fieldFromInstruction(insn, 8, 4);
bool ValidNamed;
uint64_t pstate_field = (op1 << 3) | op2;
uint32_t pstate_field = (op1 << 3) | op2;
MCOperand_CreateImm0(Inst, pstate_field);
MCOperand_CreateImm0(Inst, crm);
@ -1633,9 +1633,9 @@ static DecodeStatus DecodeSystemPStateInstruction(MCInst *Inst,
static DecodeStatus DecodeTestAndBranch(MCInst *Inst, uint32_t insn,
uint64_t Addr, void *Decoder)
{
uint64_t Rt = fieldFromInstruction(insn, 0, 5);
uint64_t bit = fieldFromInstruction(insn, 31, 1) << 5;
int64_t dst = fieldFromInstruction(insn, 5, 14);
uint32_t Rt = fieldFromInstruction(insn, 0, 5);
uint32_t bit = fieldFromInstruction(insn, 31, 1) << 5;
uint32_t dst = fieldFromInstruction(insn, 5, 14);
bit |= fieldFromInstruction(insn, 19, 5);

8
arch/AArch64/AArch64InstPrinter.c
View File

@ -136,8 +136,8 @@ void AArch64_printInst(MCInst *MI, SStream *O, void *Info)
if (MCOperand_isImm(Op2) && MCOperand_isImm(Op3)) {
char *AsmMnemonic = NULL;
int shift = 0;
int64_t immr = MCOperand_getImm(Op2);
int64_t imms = MCOperand_getImm(Op3);
int immr = (int)MCOperand_getImm(Op2);
int imms = (int)MCOperand_getImm(Op3);
if (Opcode == AArch64_UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
AsmMnemonic = "lsl";
@ -974,7 +974,7 @@ static void printImmScale(MCInst *MI, unsigned OpNum, SStream *O, int Scale)
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = val;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
} else {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;
@ -992,7 +992,7 @@ static void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStrea
printInt64Bang(O, val);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = val;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)val;
} else {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = val;

4
arch/ARM/ARMInstPrinter.c
View File

@ -1157,7 +1157,7 @@ static void printPostIdxRegOperand(MCInst *MI, unsigned OpNum, SStream *O)
static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, OpNum);
unsigned Imm = (unsigned int)MCOperand_getImm(MO);
int Imm = (int)MCOperand_getImm(MO);
if (((Imm & 0xff) << 2) > HEX_THRESHOLD) {
SStream_concat(O, "#%s0x%x", ((Imm & 256) ? "" : "-"), ((Imm & 0xff) << 2));
@ -1166,7 +1166,7 @@ static void printPostIdxImm8s4Operand(MCInst *MI, unsigned OpNum, SStream *O)
}
if (MI->csh->detail) {
int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((((int)Imm) & 0xff) << 2);
int v = (Imm & 256) ? ((Imm & 0xff) << 2) : -((Imm & 0xff) << 2);
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].type = ARM_OP_IMM;
MI->flat_insn->detail->arm.operands[MI->flat_insn->detail->arm.op_count].imm = v;
MI->flat_insn->detail->arm.op_count++;