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x86: detail operands for 'fstpnce st(0), st(0)' & 'fstpst(7), st(0)'

This commit is contained in:
Nguyen Anh Quynh 2014-05-21 16:18:56 +08:00
parent b6e3f01bb8
commit 7a65ad7e4b
2 changed files with 86 additions and 58 deletions
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4
arch/X86/X86IntelInstPrinter.c
View File

@ -511,8 +511,8 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O)
}
if (!MCOperand_isImm(DispSpec)) {
if (NeedPlus) SStream_concat(O, " + ");
//assert(DispSpec.isExpr() && "non-immediate displacement for LEA?");
if (NeedPlus)
SStream_concat(O, " + ");
} else {
int64_t DispVal = MCOperand_getImm(DispSpec);
if (MI->csh->detail)

140
arch/X86/X86Mapping.c
View File

@ -41579,70 +41579,98 @@ void X86_post_printer(csh handle, cs_insn *insn, char *insn_asm, MCInst *mci)
cs_struct *ud = (cs_struct *)handle;
if (ud->detail) {
if (ud->syntax != CS_OPT_SYNTAX_ATT) { // default syntax is Intel
// AT&T print this instruction without immediate 1?
switch (mci->Opcode) {
default:
break;
case X86_SAL8r1:
case X86_SAL16r1:
case X86_SAL32r1:
case X86_SAL64r1:
case X86_SAL8m1:
case X86_SAL16m1:
case X86_SAL32m1:
case X86_SAL64m1:
// printf(">>> post_printer: opcode = %u\n", mci->Opcode);
switch(mci->Opcode) {
default:
break;
case X86_ST_FPNCE:
// fstpnce st(0), st(0)
insn->detail->x86.operands[insn->detail->x86.op_count].type = X86_OP_REG;
insn->detail->x86.operands[insn->detail->x86.op_count].reg = X86_REG_ST0;
insn->detail->x86.op_count++;
insn->detail->x86.operands[insn->detail->x86.op_count].type = X86_OP_REG;
insn->detail->x86.operands[insn->detail->x86.op_count].reg = X86_REG_ST0;
insn->detail->x86.op_count++;
break;
case X86_ST_FPr0r7:
// fstp st(7), st(0)
if (ud->syntax != CS_OPT_SYNTAX_ATT) { // default syntax is Intel
insn->detail->x86.operands[insn->detail->x86.op_count].type = X86_OP_REG;
insn->detail->x86.operands[insn->detail->x86.op_count].reg = X86_REG_ST7;
insn->detail->x86.op_count++;
insn->detail->x86.operands[insn->detail->x86.op_count].type = X86_OP_REG;
insn->detail->x86.operands[insn->detail->x86.op_count].reg = X86_REG_ST0;
insn->detail->x86.op_count++;
} else {
insn->detail->x86.operands[insn->detail->x86.op_count].type = X86_OP_REG;
insn->detail->x86.operands[insn->detail->x86.op_count].reg = X86_REG_ST0;
insn->detail->x86.op_count++;
insn->detail->x86.operands[insn->detail->x86.op_count].type = X86_OP_REG;
insn->detail->x86.operands[insn->detail->x86.op_count].reg = X86_REG_ST7;
insn->detail->x86.op_count++;
}
break;
case X86_SAL8r1:
case X86_SAL16r1:
case X86_SAL32r1:
case X86_SAL64r1:
case X86_SAL8m1:
case X86_SAL16m1:
case X86_SAL32m1:
case X86_SAL64m1:
case X86_SHL8r1:
case X86_SHL16r1:
case X86_SHL32r1:
case X86_SHL64r1:
case X86_SHL8m1:
case X86_SHL16m1:
case X86_SHL32m1:
case X86_SHL64m1:
case X86_SHL8r1:
case X86_SHL16r1:
case X86_SHL32r1:
case X86_SHL64r1:
case X86_SHL8m1:
case X86_SHL16m1:
case X86_SHL32m1:
case X86_SHL64m1:
case X86_SHR8r1:
case X86_SHR16r1:
case X86_SHR32r1:
case X86_SHR64r1:
case X86_SHR8m1:
case X86_SHR16m1:
case X86_SHR32m1:
case X86_SHR64m1:
case X86_SHR8r1:
case X86_SHR16r1:
case X86_SHR32r1:
case X86_SHR64r1:
case X86_SHR8m1:
case X86_SHR16m1:
case X86_SHR32m1:
case X86_SHR64m1:
case X86_SAR8r1:
case X86_SAR16r1:
case X86_SAR32r1:
case X86_SAR64r1:
case X86_SAR8m1:
case X86_SAR16m1:
case X86_SAR32m1:
case X86_SAR64m1:
case X86_SAR8r1:
case X86_SAR16r1:
case X86_SAR32r1:
case X86_SAR64r1:
case X86_SAR8m1:
case X86_SAR16m1:
case X86_SAR32m1:
case X86_SAR64m1:
case X86_ROR8r1:
case X86_ROR16r1:
case X86_ROR32r1:
case X86_ROR64r1:
case X86_ROR8m1:
case X86_ROR16m1:
case X86_ROR32m1:
case X86_ROR64m1:
case X86_ROL8r1:
case X86_ROL16r1:
case X86_ROL32r1:
case X86_ROL64r1:
case X86_ROL8m1:
case X86_ROL16m1:
case X86_ROL32m1:
case X86_ROL64m1:
case X86_ROR8r1:
case X86_ROR16r1:
case X86_ROR32r1:
case X86_ROR64r1:
case X86_ROR8m1:
case X86_ROR16m1:
case X86_ROR32m1:
case X86_ROR64m1:
case X86_ROL8r1:
case X86_ROL16r1:
case X86_ROL32r1:
case X86_ROL64r1:
case X86_ROL8m1:
case X86_ROL16m1:
case X86_ROL32m1:
case X86_ROL64m1:
if (ud->syntax != CS_OPT_SYNTAX_ATT) { // default syntax is Intel
// AT&T print this instruction without immediate 1?
insn->detail->x86.operands[insn->detail->x86.op_count].type = X86_OP_IMM;
insn->detail->x86.operands[insn->detail->x86.op_count].imm = 1;
insn->detail->x86.op_count++;
break;
}
}
break;
}
}
#endif