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Merge pull request #2422 from david942j/v5_thumb_cpsr 

[v5][arm] Consider SpecRegRBit on setting SYSREG
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Rot127 2024-08-04 11:15:50 +00:00 committed by GitHub
parent d31d979a1e 849fdfa376
commit 7e32d747e1
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GPG Key ID: B5690EEEBB952194
2 changed files with 8 additions and 4 deletions
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8
arch/ARM/ARMInstPrinter.c
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@ -1805,22 +1805,22 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (Mask & 8) {
SStream_concat0(O, "f");
reg += ARM_SYSREG_SPSR_F;
reg += SpecRegRBit ? ARM_SYSREG_SPSR_F : ARM_SYSREG_CPSR_F;
}
if (Mask & 4) {
SStream_concat0(O, "s");
reg += ARM_SYSREG_SPSR_S;
reg += SpecRegRBit ? ARM_SYSREG_SPSR_S : ARM_SYSREG_CPSR_S;
}
if (Mask & 2) {
SStream_concat0(O, "x");
reg += ARM_SYSREG_SPSR_X;
reg += SpecRegRBit ? ARM_SYSREG_SPSR_X : ARM_SYSREG_CPSR_X;
}
if (Mask & 1) {
SStream_concat0(O, "c");
reg += ARM_SYSREG_SPSR_C;
reg += SpecRegRBit ? ARM_SYSREG_SPSR_C : ARM_SYSREG_CPSR_C;
}
ARM_addSysReg(MI, reg);

4
suite/cstest/issues.cs
View File

@ -1058,3 +1058,7 @@
!# issue 2419
!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
0x0: 0x12,0xbf,0xff,0xff == bne -4 ; Code condition: 265
!# issue 2418
!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
0x0: 0x86,0xf3,0x00,0x89 == msr cpsr_fc, r6 ; operands[0].type: SYSREG = 144