`MADD*`
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billow
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@ -674,7 +674,7 @@ class RRR<bits<8> op1, bits<4> op2 , dag outs, dag ins, string asmstr,
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//===----------------------------------------------------------------------===//
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// 32-bit RRR1 Instruction Format: <d|s3|op2|n|s2|s1|op1>
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//===----------------------------------------------------------------------===//
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class RRR1<bits<8> op1, bits<6> op2 , dag outs, dag ins, string asmstr,
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class RRR1<bits<8> op1, bits<6> op2, dag outs, dag ins, string asmstr,
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list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
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bits<4> d;
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@ -696,7 +696,7 @@ class RRR1<bits<8> op1, bits<6> op2 , dag outs, dag ins, string asmstr,
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//===----------------------------------------------------------------------===//
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// 32-bit RRR2 Instruction Format: <d|s3|op2|s2|s1|op1>
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//===----------------------------------------------------------------------===//
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class RRR2<bits<8> op1, bits<8> op2 , dag outs, dag ins, string asmstr,
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class RRR2<bits<8> op1, bits<8> op2, dag outs, dag ins, string asmstr,
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list<dag> pattern> : T32<outs, ins, asmstr, pattern> {
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bits<4> s1;
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@ -660,6 +660,11 @@ class IRCR_E<bits<8>op1, bits<3> op2, string asmstr>
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: RCR<op1, op2, (outs ExtRegs:$d), (ins DataRegs:$s1, ExtRegs:$s3, s9imm:$const9),
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asmstr # " $d, $s3, $s1, $const9", []>;
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multiclass mIRCR<bits<8>op1, bits<3> op2, bits<8>op3, bits<3> op4, string asmstr>{
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def _rcr : IRCR<op1, op2, asmstr>;
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def _rcr_e : IRCR_E<op3, op4, asmstr>;
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}
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/// CADD Instructions
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def CADD_rcr : IRCR<0xAB, 0x00, "cadd">;
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def CADD_rrr : IRRR_dab<0x2B, 0x00, "cadd">;
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@ -1206,6 +1211,100 @@ defm LT_B : mIU__RR_ab<0x0B, 0x52, 0x0B, 0x53, "lt.b">;
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defm LT_H : mIU__RR_ab<0x0B, 0x72, 0x0B, 0x73, "lt.h">;
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defm LT_W : mIU__RR_ab<0x0B, 0x92, 0x0B, 0x93, "lt.w">;
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class IRRR1_label<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc, string label>
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: RRR1<op1, op2, (outs rc:$d), (ins DataRegs:$s1, DataRegs:$s2, rc:$s3, u2imm:$n),
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asmstr # " $d, $s3, $s1, $s2 " # label # ", $n", []>;
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class IRRR1_label2<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc, string label1, string label2>
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: RRR1<op1, op2, (outs rc:$d), (ins DataRegs:$s1, DataRegs:$s2, rc:$s3, u2imm:$n),
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asmstr # " $d, $s3, $s1" # label1 # ", $s2" # label2 # ", $n", []>;
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class IRRR1<bits<8> op1, bits<6> op2, string asmstr, RegisterClass rc>
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: RRR1<op1, op2, (outs rc:$d), (ins DataRegs:$s1, DataRegs:$s2, rc:$s3, u2imm:$n),
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asmstr # " $d, $s3, $s1, $s2, $n", []>;
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class IRRR2<bits<8> op1, bits<8> op2, string asmstr, RegisterClass rc>
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: RRR2<op1, op2, (outs rc:$d), (ins DataRegs:$s1, DataRegs:$s2, rc:$s3),
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asmstr # " $d, $s3, $s1, $s2", []>;
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multiclass mIRRR2<bits<8> op1, bits<8> op2, bits<8> op3, bits<8> op4, string asmstr>{
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def _rrr2 : IRRR2<op1, op2, asmstr, DataRegs>;
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def _rrr2_e : IRRR2<op1, op2, asmstr, ExtRegs>;
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}
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defm MADD : mIRCR<0x13, 0x01, 0x13, 0x03, "madd">
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, mIRRR2<0x03, 0x0A, 0x03, 0x6A, "madd">;
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defm MADDS : mIRCR<0x13, 0x05, 0x13, 0x07, "madds">
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, mIRRR2<0x03, 0x8A, 0x03, 0xEA, "madds">;
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multiclass mIRRR1_LU2<bits<8> ll1, bits<6> ll2, bits<8> lu1, bits<6> lu2,
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bits<8> ul1, bits<6> ul2, bits<8> uu1, bits<6> uu2,
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string asmstr, RegisterClass rc>{
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def _rrr1_LL : IRRR1_label<ll1, ll2, asmstr, rc, "LL">;
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def _rrr1_LU : IRRR1_label<lu1, lu2, asmstr, rc, "LU">;
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def _rrr1_UL : IRRR1_label<ul1, ul2, asmstr, rc, "UL">;
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def _rrr1_UU : IRRR1_label<uu1, uu2, asmstr, rc, "UU">;
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}
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multiclass mIRRR1_E_LU2<bits<8> ll1, bits<6> ll2, bits<8> lu1, bits<6> lu2,
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bits<8> ul1, bits<6> ul2, bits<8> uu1, bits<6> uu2, string asmstr>{
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defm "" : mIRRR1_LU2<ll1, ll2, lu1, lu2, ul1, ul2, uu1, uu2, asmstr, ExtRegs>;
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}
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defm MADD_H : mIRRR1_E_LU2<0x83, 0x1A, 0x83, 0x19, 0x83, 0x18, 0x83, 0x1B, "madd.h">;
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defm MADDS_H : mIRRR1_E_LU2<0x83, 0x3A, 0x83, 0x39, 0x83, 0x38, 0x83, 0x3B, "madds.h">;
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def MADD_Q_rrr1 : IRRR1<0x43, 0x02, "madd.q", DataRegs>;
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def MADD_Q_rrr1_e : IRRR1<0x43, 0x1B, "madd.q", ExtRegs>;
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def MADD_Q_rrr1_L : IRRR1_label<0x43, 0x01, "madd.q", DataRegs, "L">;
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def MADD_Q_rrr1_e_L : IRRR1_label<0x43, 0x19, "madd.q", ExtRegs, "L">;
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def MADD_Q_rrr1_U : IRRR1_label<0x43, 0x00, "madd.q", DataRegs, "U">;
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def MADD_Q_rrr1_e_U : IRRR1_label<0x43, 0x18, "madd.q", ExtRegs, "U">;
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def MADD_Q_rrr1_L_L : IRRR1_label2<0x43, 0x05, "madd.q", DataRegs, "L", "L">;
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def MADD_Q_rrr1_e_L_L : IRRR1_label2<0x43, 0x1D, "madd.q", ExtRegs, "L", "L">;
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def MADD_Q_rrr1_U_U : IRRR1_label2<0x43, 0x04, "madd.q", DataRegs, "U", "U">;
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def MADD_Q_rrr1_e_U_U : IRRR1_label2<0x43, 0x1C, "madd.q", ExtRegs, "U", "U">;
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def MADDS_Q_rrr1 : IRRR1<0x43, 0x22, "madds.q", DataRegs>;
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def MADDS_Q_rrr1_e : IRRR1<0x43, 0x3B, "madds.q", ExtRegs>;
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def MADDS_Q_rrr1_L : IRRR1_label<0x43, 0x21, "madds.q", DataRegs, "L">;
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def MADDS_Q_rrr1_e_L : IRRR1_label<0x43, 0x39, "madds.q", ExtRegs, "L">;
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def MADDS_Q_rrr1_U : IRRR1_label<0x43, 0x20, "madds.q", DataRegs, "U">;
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def MADDS_Q_rrr1_e_U : IRRR1_label<0x43, 0x38, "madds.q", ExtRegs, "U">;
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def MADDS_Q_rrr1_L_L : IRRR1_label2<0x43, 0x25, "madds.q", DataRegs, "L", "L">;
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def MADDS_Q_rrr1_e_L_L : IRRR1_label2<0x43, 0x3D, "madds.q", ExtRegs, "L", "L">;
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def MADDS_Q_rrr1_U_U : IRRR1_label2<0x43, 0x24, "madds.q", DataRegs, "U", "U">;
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def MADDS_Q_rrr1_e_U_U : IRRR1_label2<0x43, 0x3C, "madds.q", ExtRegs, "U", "U">;
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def MADD_U_rcr : IRCR_E<0x13, 0x02, "madd.u">;
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def MADD_U_rrr2 : IRRR2<0x03, 0x68, "madd.u", ExtRegs>;
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defm MADDS_U : mIRCR<0x13, 0x04, 0x13, 0x06, "madds.u">
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, mIRRR2<0x03, 0x88, 0x03, 0xE8, "madds.u">;
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defm MADDM_H : mIRRR1_E_LU2<0x83, 0x1E, 0x83, 0x1D, 0x83, 0x1C, 0x83, 0x1F, "maddm.h">;
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defm MADDMS_H : mIRRR1_E_LU2<0x83, 0x3E, 0x83, 0x3D, 0x83, 0x3C, 0x83, 0x3F, "maddms.h">;
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defm MADDR_H : mIRRR1_LU2<0x83, 0x0E, 0x83, 0x0D, 0x83, 0x0C, 0x83, 0x0F, "maddr.h", DataRegs>;
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defm MADDRS_H : mIRRR1_LU2<0x83, 0x2E, 0x83, 0x2D, 0x83, 0x2C, 0x83, 0x2F, "maddrs.h", DataRegs>;
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def MADDR_H_rrr1_DcEdDaDbUL
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: RRR1<0x43, 0x1E, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2, ExtRegs:$s3, u2imm:$n),
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"maddr.h $d, $s3, $s1, $s2, UL, $n", []>;
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def MADDRS_H_rrr1_DcEdDaDbUL
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: RRR1<0x43, 0x3E, (outs DataRegs:$d), (ins DataRegs:$s1, DataRegs:$s2, ExtRegs:$s3, u2imm:$n),
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"maddrs.h $d, $s3, $s1, $s2, UL, $n", []>;
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def MADDR_Q_rrr1_L_L : IRRR1_label2<0x43, 0x07, "maddr.q", DataRegs, "L", "L">;
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def MADDR_Q_rrr1_U_U : IRRR1_label2<0x43, 0x06, "maddr.q", DataRegs, "U", "U">;
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def MADDRS_Q_rrr1_L_L : IRRR1_label2<0x43, 0x27, "maddrs.q", DataRegs, "L", "L">;
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def MADDRS_Q_rrr1_U_U : IRRR1_label2<0x43, 0x26, "maddrs.q", DataRegs, "U", "U">;
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defm MADDSU_H : mIRRR1_E_LU2<0xC3, 0x1A, 0xC3, 0x19, 0xC3, 0x18, 0xC3, 0x1B, "maddsu.h">;
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defm MADDSUS_H : mIRRR1_E_LU2<0xC3, 0x3A, 0xC3, 0x39, 0xC3, 0x38, 0xC3, 0x3B, "maddsus.h">;
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defm MADDSUM_H : mIRRR1_E_LU2<0xC3, 0x1E, 0xC3, 0x1D, 0xC3, 0x1C, 0xC3, 0x1F, "maddsum.h">;
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defm MADDSUMS_H : mIRRR1_E_LU2<0xC3, 0x3E, 0xC3, 0x3D, 0xC3, 0x3C, 0xC3, 0x3F, "maddsums.h">;
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defm MADDSUR_H : mIRRR1_LU2<0xC3, 0x0E, 0xC3, 0x0D, 0xC3, 0x0C, 0xC3, 0x0F, "maddsur.h", DataRegs>;
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defm MADDSURS_H : mIRRR1_LU2<0xC3, 0x2E, 0xC3, 0x2D, 0xC3, 0x2C, 0xC3, 0x2F, "maddsurs.h", DataRegs>;
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let Defs = [PSW], Uses = [PSW] in {
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def SUBCrr : RR<0x0B, 0x0D, (outs DataRegs:$d),
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(ins DataRegs:$s1, DataRegs:$s2),
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