MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665)
* Disable Mips_FeatureUseIndirectJumpsHazard Mips_FeatureUseIndirectJumpsHazard is only used for jalr when used in mips32 configs. * DDIV test * Fix details on instructions that contains ghost registers. * Add missing MIPS tables & Fix mips16 and JrcRa16/AddiuSpImmX16 decoding. Mips16 decoding of JrcRa16 & AddiuSpImmX16 was expecting the wrong bits. Implement DecodeCPU16RegsRegisterClass for Mips16 Adds missing mips decoding tables: - DecoderTableNanoMips_Conflict_Space16 - DecoderTableMicroMipsR6_Ambiguous32 - DecoderTableMicroMipsDSP32 - DecoderTable16 - DecoderTable32 - DecoderTableMips32r6_64r6_Ambiguous32 - DecoderTableMips32r6_64r6_BranchZero32 - DecoderTableMipsDSP32 * Patch details only when details are request. * Fix wrong tests * Address comments * Add mips DSP test * microMips32r3 DSP * Test Conflict_Space16 * Test Conflict_Space16
This commit is contained in:
Giovanni
GitHub
parent
98a393e34d
commit
81a6ba0389
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@ -236,8 +236,6 @@ bool Mips_getFeatureBits(unsigned int mode, unsigned int feature)
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}
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return true;
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}
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case Mips_FeatureUseIndirectJumpsHazard:
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return true;
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default:
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return false;
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}
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@ -1459,6 +1457,7 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
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bool IsNanoMips = Mips_getFeatureBits(mode, Mips_FeatureNanoMips);
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bool IsMips32r6 = Mips_getFeatureBits(mode, Mips_FeatureMips32r6);
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bool IsMips2 = Mips_getFeatureBits(mode, Mips_FeatureMips2);
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bool IsMips16 = Mips_getFeatureBits(mode, Mips_FeatureMips16);
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bool IsCnMips = Mips_getFeatureBits(mode, Mips_FeatureCnMips);
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bool IsCnMipsP = Mips_getFeatureBits(mode, Mips_FeatureCnMipsP);
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bool IsFP64 = Mips_getFeatureBits(mode, Mips_FeatureFP64Bit);
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@ -1498,6 +1497,14 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
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Result = readInstruction16(Bytes, BytesLen, Address, Size,
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&Insn, IsBigEndian);
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if (Result != MCDisassembler_Fail) {
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Result = decodeInstruction_2(DecoderTableNanoMips_Conflict_Space16,
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Instr, Insn, Address,
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NULL);
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if (Result != MCDisassembler_Fail) {
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*Size = 2;
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return Result;
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}
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// Calling the auto-generated decoder function for NanoMips
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// 16-bit instructions.
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Result = decodeInstruction_2(DecoderTableNanoMips16,
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@ -1550,6 +1557,14 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
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if (IsMips32r6) {
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// Calling the auto-generated decoder function.
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Result = decodeInstruction_4(DecoderTableMicroMipsR6_Ambiguous32,
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Instr, Insn, Address,
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NULL);
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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Result = decodeInstruction_4(DecoderTableMicroMipsR632,
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Instr, Insn, Address,
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NULL);
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@ -1567,6 +1582,13 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
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return Result;
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}
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Result = decodeInstruction_4(DecoderTableMicroMipsDSP32, Instr,
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Insn, Address, NULL);
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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if (IsFP64) {
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Result =
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decodeInstruction_4(DecoderTableMicroMipsFP6432,
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@ -1586,6 +1608,28 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
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return MCDisassembler_Fail;
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}
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if (IsMips16) {
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Result = readInstruction32(Bytes, BytesLen, Address, Size,
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&Insn, IsBigEndian, IsMicroMips);
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if (Result != MCDisassembler_Fail) {
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Result = decodeInstruction_4(DecoderTable32, Instr, Insn, Address,
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NULL);
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if (Result != MCDisassembler_Fail) {
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*Size = 4;
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return Result;
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}
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}
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Result = readInstruction16(Bytes, BytesLen, Address, Size,
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&Insn, IsBigEndian);
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if (Result == MCDisassembler_Fail) {
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return MCDisassembler_Fail;
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}
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*Size = 2;
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return decodeInstruction_2(DecoderTable16, Instr, Insn, Address, NULL);
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}
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// Attempt to read the instruction so that we can attempt to decode it. If
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// the buffer is not 4 bytes long, let the higher level logic figure out
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// what to do with a size of zero and MCDisassembler::Fail.
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@ -1619,6 +1663,16 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
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}
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if (IsMips32r6) {
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Result = decodeInstruction_4(DecoderTableMips32r6_64r6_Ambiguous32, Instr,
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Insn, Address, NULL);
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if (Result != MCDisassembler_Fail)
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return Result;
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Result = decodeInstruction_4(DecoderTableMips32r6_64r6_BranchZero32, Instr,
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Insn, Address, NULL);
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if (Result != MCDisassembler_Fail)
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return Result;
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Result = decodeInstruction_4(DecoderTableMips32r6_64r632, Instr,
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Insn, Address, NULL);
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if (Result != MCDisassembler_Fail)
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@ -1660,6 +1714,11 @@ static DecodeStatus getInstruction(MCInst *Instr, uint64_t *Size, const uint8_t
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return Result;
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}
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Result = decodeInstruction_4(DecoderTableMipsDSP32, Instr, Insn,
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Address, NULL);
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if (Result != MCDisassembler_Fail)
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return Result;
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// Calling the auto-generated decoder function.
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Result = decodeInstruction_4(DecoderTableMips32, Instr, Insn, Address,
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NULL);
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@ -1673,7 +1732,15 @@ static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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return MCDisassembler_Fail;
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if (RegNo > 7)
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return MCDisassembler_Fail;
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if (RegNo < 2)
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RegNo += 16;
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unsigned Reg = getReg(Inst, Mips_GPR32RegClassID, RegNo);
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeGPR64RegisterClass(MCInst *Inst, unsigned RegNo,
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@ -101,7 +101,7 @@ static const uint8_t DecoderTable16[] = {
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/* 299 */ MCD_OPC_CheckPredicate, 0, 57, 1, 0, // Skip to: 617
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/* 304 */ MCD_OPC_CheckField, 8, 3, 0, 50, 1, 0, // Skip to: 617
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/* 311 */ MCD_OPC_Decode, 150, 15, 10, // Opcode: JrcRx16
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/* 315 */ MCD_OPC_FilterValue, 7, 41, 1, 0, // Skip to: 617
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/* 315 */ MCD_OPC_FilterValue, 5, 41, 1, 0, // Skip to: 617
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/* 320 */ MCD_OPC_CheckPredicate, 0, 36, 1, 0, // Skip to: 617
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/* 325 */ MCD_OPC_CheckField, 8, 3, 0, 29, 1, 0, // Skip to: 617
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/* 332 */ MCD_OPC_Decode, 149, 15, 10, // Opcode: JrcRa16
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@ -190,7 +190,7 @@ static const uint8_t DecoderTable32[] = {
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/* 97 */ MCD_OPC_CheckField, 27, 5, 30, 167, 1, 0, // Skip to: 527
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/* 104 */ MCD_OPC_CheckField, 5, 3, 0, 160, 1, 0, // Skip to: 527
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/* 111 */ MCD_OPC_Decode, 240, 8, 16, // Opcode: BnezRxImmX16
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/* 115 */ MCD_OPC_FilterValue, 6, 106, 0, 0, // Skip to: 226
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/* 115 */ MCD_OPC_FilterValue, 12, 106, 0, 0, // Skip to: 226
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/* 120 */ MCD_OPC_ExtractField, 27, 5, // Inst{31-27} ...
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/* 123 */ MCD_OPC_FilterValue, 30, 143, 1, 0, // Skip to: 527
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/* 128 */ MCD_OPC_ExtractField, 16, 5, // Inst{20-16} ...
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@ -121,6 +121,110 @@ static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg)
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SStream_concat0(OS, Mips_LLVM_getRegisterName(Reg, syntax_opt & CS_OPT_SYNTAX_NOREGNAME));
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}
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static void patch_cs_printer(MCInst *MI, SStream *O) {
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// replace '# 16 bit inst' to empty.
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SStream_replc(O, '#', 0);
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SStream_trimls(O);
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if (MI->csh->syntax & CS_OPT_SYNTAX_NO_DOLLAR) {
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char *dollar = strchr(O->buffer, '$');
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if (!dollar) {
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return;
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}
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size_t dollar_len = strlen(dollar + 1);
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// to include `\0`
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memmove(dollar, dollar + 1, dollar_len + 1);
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}
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}
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static void patch_cs_detail_operand_reg(cs_mips_op *op, unsigned reg, unsigned access) {
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op->type = MIPS_OP_REG;
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op->reg = reg;
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op->is_reglist = false;
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op->access = access;
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}
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static void patch_cs_details(MCInst *MI) {
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if (!detail_is_set(MI))
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return;
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cs_mips_op *op0 = NULL, *op1 = NULL, *op2 = NULL;
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unsigned opcode = MCInst_getOpcode(MI);
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unsigned n_ops = MCInst_getNumOperands(MI);
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switch(opcode) {
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/* mips r2 to r5 only 64bit */
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case Mips_DSDIV: /// ddiv $$zero, $rs, $rt
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/* fall-thru */
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case Mips_DUDIV: /// ddivu $$zero, $rs, $rt
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if (n_ops != 2) {
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return;
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}
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Mips_inc_op_count(MI);
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op0 = Mips_get_detail_op(MI, -3);
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op1 = Mips_get_detail_op(MI, -2);
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op2 = Mips_get_detail_op(MI, -1);
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// move all details by one and add $zero reg
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*op2 = *op1;
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*op1 = *op0;
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patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO_64, CS_AC_WRITE);
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return;
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/* mips r2 to r5 only */
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case Mips_SDIV: /// div $$zero, $rs, $rt
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/* fall-thru */
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case Mips_UDIV: /// divu $$zero, $rs, $rt
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/* fall-thru */
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/* microMIPS only */
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case Mips_SDIV_MM: /// div $$zero, $rs, $rt
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/* fall-thru */
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case Mips_UDIV_MM: /// divu $$zero, $rs, $rt
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/* fall-thru */
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/* MIPS16 only */
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case Mips_DivRxRy16: /// div $$zero, $rx, $ry
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/* fall-thru */
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case Mips_DivuRxRy16: /// divu $$zero, $rx, $ry
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if (n_ops != 2) {
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return;
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}
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Mips_inc_op_count(MI);
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op0 = Mips_get_detail_op(MI, -3);
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op1 = Mips_get_detail_op(MI, -2);
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op2 = Mips_get_detail_op(MI, -1);
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// move all details by one and add $zero reg
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*op2 = *op1;
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*op1 = *op0;
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patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO, CS_AC_WRITE);
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return;
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case Mips_AddiuSpImm16: /// addiu $$sp, imm8
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/* fall-thru */
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case Mips_AddiuSpImmX16: /// addiu $$sp, imm8
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if (n_ops != 1) {
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return;
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}
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Mips_inc_op_count(MI);
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op0 = Mips_get_detail_op(MI, -2);
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op1 = Mips_get_detail_op(MI, -1);
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// move all details by one and add $sp reg
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*op1 = *op0;
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patch_cs_detail_operand_reg(op0, MIPS_REG_SP, CS_AC_READ_WRITE);
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return;
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case Mips_JrcRa16: /// jrc $ra
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/* fall-thru */
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case Mips_JrRa16: /// jr $ra
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if (n_ops > 0) {
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return;
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}
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Mips_inc_op_count(MI);
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op0 = Mips_get_detail_op(MI, -1);
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patch_cs_detail_operand_reg(op0, MIPS_REG_RA, CS_AC_READ);
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return;
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default:
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return;
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}
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}
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void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) {
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bool useAliasDetails = map_use_alias_details(MI);
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if (!useAliasDetails) {
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@ -137,6 +241,9 @@ void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) {
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printInstruction(MI, Address, O);
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}
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patch_cs_printer(MI, O);
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patch_cs_details(MI);
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if (!useAliasDetails) {
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map_set_fill_detail_ops(MI, true);
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}
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@ -213,6 +213,8 @@ static const TestOptionMapEntry test_option_map[] = {
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.opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_CS_REG_ALIAS } },
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{ .str = "CS_OPT_SYNTAX_PERCENT",
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.opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_PERCENT } },
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{ .str = "CS_OPT_SYNTAX_NO_DOLLAR",
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.opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_NO_DOLLAR } },
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};
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static const cs_enum_id_map cs_enum_map[] = {
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@ -207,7 +207,7 @@ test_cases:
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expected:
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insns:
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-
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asm_text: "beqzalc $2, 1340"
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asm_text: "bnezalc $2, 1340"
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-
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input:
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@ -547,7 +547,7 @@ test_cases:
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expected:
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insns:
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-
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asm_text: "bovc $zero, $zero, 12"
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asm_text: "bnvc $zero, $zero, 12"
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-
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input:
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@ -507,7 +507,7 @@ test_cases:
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expected:
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insns:
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-
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asm_text: "bovc $zero, $zero, 12"
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asm_text: "bnvc $zero, $zero, 12"
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-
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input:
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@ -517,7 +517,7 @@ test_cases:
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expected:
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insns:
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-
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asm_text: "beqzalc $2, 1340"
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asm_text: "bnezalc $2, 1340"
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-
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input:
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@ -422,7 +422,7 @@ test_cases:
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mnemonic: "lw"
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op_str: "$v0, 0($sp)"
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details:
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groups: [ HasStdEnc, NotInMicroMips, NotNanoMips ]
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groups: [ NotInMips16Mode, HasDSP ]
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-
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asm_text: "ori $at, $at, 0x3456"
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mnemonic: "ori"
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@ -5880,3 +5880,149 @@ test_cases:
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asm_text: "svc #0x8"
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details:
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groups: [ call, int ]
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-
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input:
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name: "jalr on mips32r2"
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bytes: [ 0x09, 0xf8, 0x20, 0x03 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_MODE_MIPS32R2, CS_MODE_LITTLE_ENDIAN ]
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address: 0x0
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expected:
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insns:
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-
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asm_text: "jalr $t9"
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-
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input:
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name: "ddiv on mips64r2"
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bytes: [ 0x01, 0x11, 0x00, 0x1e, 0x01, 0x65, 0x00, 0x1a ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_MODE_MIPS64R2, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NO_DOLLAR, CS_OPT_DETAIL ]
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address: 0x0
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expected:
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insns:
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- asm_text: "ddiv zero, t0, s1"
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details:
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mips:
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operands:
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- type: MIPS_OP_REG
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reg: zero
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- type: MIPS_OP_REG
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reg: t0
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- type: MIPS_OP_REG
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reg: s1
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- asm_text: "div zero, t3, a1"
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details:
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mips:
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operands:
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- type: MIPS_OP_REG
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reg: zero
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- type: MIPS_OP_REG
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reg: t3
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- type: MIPS_OP_REG
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reg: a1
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- input:
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name: "jr/jrc/ ra & div/divu zero on mips16"
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bytes: [ 0xe8, 0x20, 0xe8, 0xa0, 0xeb, 0x5a, 0xeb, 0x5b, 0x63, 0x1e, 0xf0, 0x64, 0x63, 0x05 ]
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arch: "CS_ARCH_MIPS"
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options: [ CS_MODE_MIPS16, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NO_DOLLAR, CS_OPT_DETAIL ]
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address: 0x0
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expected:
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insns:
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- asm_text: "jr ra"
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details:
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mips:
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operands:
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- type: MIPS_OP_REG
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reg: ra
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- asm_text: "jrc ra"
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details:
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mips:
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operands:
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- type: MIPS_OP_REG
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reg: ra
|
||||
- asm_text: "div zero, v1, v0"
|
||||
details:
|
||||
mips:
|
||||
operands:
|
||||
- type: MIPS_OP_REG
|
||||
reg: zero
|
||||
- type: MIPS_OP_REG
|
||||
reg: v1
|
||||
- type: MIPS_OP_REG
|
||||
reg: v0
|
||||
- asm_text: "divu zero, v1, v0"
|
||||
details:
|
||||
mips:
|
||||
operands:
|
||||
- type: MIPS_OP_REG
|
||||
reg: zero
|
||||
- type: MIPS_OP_REG
|
||||
reg: v1
|
||||
- type: MIPS_OP_REG
|
||||
reg: v0
|
||||
- asm_text: "addiu sp, 0x1e"
|
||||
details:
|
||||
mips:
|
||||
operands:
|
||||
- type: MIPS_OP_REG
|
||||
reg: sp
|
||||
- type: MIPS_OP_IMM
|
||||
imm: 0x1e
|
||||
- asm_text: "addiu sp, 0x2065"
|
||||
details:
|
||||
mips:
|
||||
operands:
|
||||
- type: MIPS_OP_REG
|
||||
reg: sp
|
||||
- type: MIPS_OP_IMM
|
||||
imm: 0x2065
|
||||
- input:
|
||||
name: "Test mips32 DSP"
|
||||
bytes: [ 0x7e,0x32,0x83,0x11,0x7e,0x53,0x8d,0x11,0x7e,0x74,0x95,0x51,0x7e,0x95,0x9b,0xd1 ]
|
||||
arch: "CS_ARCH_MIPS"
|
||||
options: [ CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ]
|
||||
address: 0x0
|
||||
expected:
|
||||
insns:
|
||||
- asm_text: "precrq.qb.ph $s0, $s1, $s2"
|
||||
- asm_text: "precrq.ph.w $s1, $s2, $s3"
|
||||
- asm_text: "precrq_rs.ph.w $s2, $s3, $s4"
|
||||
- asm_text: "precrqu_s.qb.ph $s3, $s4, $s5"
|
||||
|
||||
- input:
|
||||
name: "Test microMips32r3 DSP"
|
||||
bytes: [ 0x00,0xa4,0x1c,0x0d,0x00,0xa4,0x1b,0x05,0x00,0x65,0x42,0xbc,0x00,0x64,0x92,0xbc ]
|
||||
arch: "CS_ARCH_MIPS"
|
||||
options: [ CS_MODE_MICRO32R3, CS_MODE_BIG_ENDIAN ]
|
||||
address: 0x0
|
||||
expected:
|
||||
insns:
|
||||
- asm_text: "addq_s.ph $v1, $a0, $a1"
|
||||
- asm_text: "addq_s.w $v1, $a0, $a1"
|
||||
- asm_text: "dpaq_s.w.ph $ac1, $a1, $v1"
|
||||
- asm_text: "dpaq_sa.l.w $ac2, $a0, $v1"
|
||||
|
||||
- input:
|
||||
name: "Test nanomips BNEC[16] (not available in NMS) - Conflict_Space16"
|
||||
bytes: [ 0xd8, 0xf6 ]
|
||||
arch: "CS_ARCH_MIPS"
|
||||
options: [ CS_MODE_NANOMIPS, CS_MODE_BIG_ENDIAN ]
|
||||
address: 0x0
|
||||
expected:
|
||||
insns:
|
||||
- asm_text: "bnec $a3, $s1, 14"
|
||||
|
||||
- input:
|
||||
name: "Test mips32r6 - Conflict_Space16"
|
||||
bytes: [ 0x58, 0x63, 0x00, 0x00, 0x5C, 0x63, 0x00, 0x00 ]
|
||||
arch: "CS_ARCH_MIPS"
|
||||
options: [ CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
|
||||
address: 0x0
|
||||
expected:
|
||||
insns:
|
||||
- asm_text: "bgezc $v1, 4"
|
||||
- asm_text: "bltzc $v1, 8"
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue