Tests for XCore CPU
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// Capstone Java binding
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// By Nguyen Anh Quynh & Dang Hoang Vu, 2013-2014
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import capstone.Capstone;
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import capstone.Xcore;
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import static capstone.Xcore_const.*;
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public class TestXcore {
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static byte[] hexString2Byte(String s) {
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// from http://stackoverflow.com/questions/140131/convert-a-string-representation-of-a-hex-dump-to-a-byte-array-using-java
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int len = s.length();
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byte[] data = new byte[len / 2];
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for (int i = 0; i < len; i += 2) {
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data[i / 2] = (byte) ((Character.digit(s.charAt(i), 16) << 4)
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+ Character.digit(s.charAt(i+1), 16));
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}
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return data;
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}
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static final String XCORE_CODE = "fe0ffe171317c6feec1797f8ec4f1ffdec3707f2455bf9fa02061b1009fdeca7";
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public static Capstone cs;
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private static String hex(int i) {
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return Integer.toString(i, 16);
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}
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private static String hex(long i) {
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return Long.toString(i, 16);
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}
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public static void print_ins_detail(Capstone.CsInsn ins) {
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System.out.printf("0x%x:\t%s\t%s\n", ins.address, ins.mnemonic, ins.opStr);
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Xcore.OpInfo operands = (Xcore.OpInfo) ins.operands;
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if (operands.op.length != 0) {
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System.out.printf("\top_count: %d\n", operands.op.length);
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for (int c=0; c<operands.op.length; c++) {
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Xcore.Operand i = (Xcore.Operand) operands.op[c];
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if (i.type == XCORE_OP_REG)
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System.out.printf("\t\toperands[%d].type: REG = %s\n", c, ins.regName(i.value.reg));
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if (i.type == XCORE_OP_IMM)
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System.out.printf("\t\toperands[%d].type: IMM = 0x%x\n", c, i.value.imm);
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if (i.type == XCORE_OP_MEM) {
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System.out.printf("\t\toperands[%d].type: MEM\n", c);
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if (i.value.mem.base != XCORE_REG_INVALID)
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System.out.printf("\t\t\toperands[%d].mem.base: REG = %s\n", c, ins.regName(i.value.mem.base));
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if (i.value.mem.index != XCORE_REG_INVALID)
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System.out.printf("\t\t\toperands[%d].mem.index: REG = %s\n", c, ins.regName(i.value.mem.index));
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if (i.value.mem.disp != 0)
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System.out.printf("\t\t\toperands[%d].mem.disp: 0x%x\n", c, i.value.mem.disp);
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if (i.value.mem.direct != 1)
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System.out.printf("\t\t\toperands[%d].mem.direct: -1\n", c);
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}
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}
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}
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}
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public static void main(String argv[]) {
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final Test.platform[] all_tests = {
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new Test.platform(Capstone.CS_ARCH_XCORE, Capstone.CS_MODE_BIG_ENDIAN, hexString2Byte(XCORE_CODE), "XCore"),
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};
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for (int i=0; i<all_tests.length; i++) {
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Test.platform test = all_tests[i];
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System.out.println(new String(new char[16]).replace("\0", "*"));
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System.out.println("Platform: " + test.comment);
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System.out.println("Code: " + Test.stringToHex(test.code));
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System.out.println("Disasm:");
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cs = new Capstone(test.arch, test.mode);
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cs.setDetail(Capstone.CS_OPT_ON);
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Capstone.CsInsn[] all_ins = cs.disasm(test.code, 0x1000);
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for (int j = 0; j < all_ins.length; j++) {
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print_ins_detail(all_ins[j]);
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System.out.println();
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}
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System.out.printf("0x%x:\n\n", (all_ins[all_ins.length-1].address + all_ins[all_ins.length-1].size));
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// Close when done
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cs.close();
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}
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}
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}
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@ -76,7 +76,7 @@ public class TestSystemz extends TestTemplate {
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}
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@Test
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public void test16bitIntelSyntax() throws Exception {
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public void testSystemZNormalSyntax() throws Exception {
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// SystemZ
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CsInsn[] disassembly = createDisassembler(Capstone.CS_ARCH_SYSZ, 0, hexString2Byte(SYSZ_CODE));
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assertDisassembly("/SystemZ/assembly_normal_syntax.asm", createDisassemblyDetails(disassembly));
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// Capstone Java binding
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// By Nguyen Anh Quynh & Dang Hoang Vu, 2013-2014
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// Andreas "PAX" Lück <onkelpax-git@yahoo.de>, 2016
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package capstone;
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import static capstone.Xcore_const.XCORE_OP_IMM;
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import static capstone.Xcore_const.XCORE_OP_MEM;
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import static capstone.Xcore_const.XCORE_OP_REG;
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import static capstone.Xcore_const.XCORE_REG_INVALID;
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import org.junit.Test;
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import capstone.Capstone.CsInsn;
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import capstone.utils.AssemblyDetailDumper;
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public class TestXcore extends TestTemplate {
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private static final String XCORE_CODE = "fe0ffe171317c6feec1797f8ec4f1ffdec3707f2455bf9fa02061b1009fdeca7";
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private static class XCoreDetailDumper extends AssemblyDetailDumper {
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public XCoreDetailDumper(Capstone disassembler, CsInsn[] disassembly) {
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super(disassembler, disassembly);
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}
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@Override
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protected void printInstructionDetails(CsInsn instruction) {
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output.printf("0x%x:\t%s\t%s\n", instruction.address, instruction.mnemonic, instruction.opStr);
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Xcore.OpInfo operands = (Xcore.OpInfo) instruction.operands;
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if (operands.op.length != 0) {
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output.printf("\top_count: %d\n", operands.op.length);
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for (int c = 0; c < operands.op.length; c++) {
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Xcore.Operand i = (Xcore.Operand) operands.op[c];
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if (i.type == XCORE_OP_REG)
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output.printf("\t\toperands[%d].type: REG = %s\n", c, instruction.regName(i.value.reg));
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if (i.type == XCORE_OP_IMM)
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output.printf("\t\toperands[%d].type: IMM = 0x%x\n", c, i.value.imm);
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if (i.type == XCORE_OP_MEM) {
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output.printf("\t\toperands[%d].type: MEM\n", c);
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if (i.value.mem.base != XCORE_REG_INVALID)
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output.printf("\t\t\toperands[%d].mem.base: REG = %s\n", c,
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instruction.regName(i.value.mem.base));
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if (i.value.mem.index != XCORE_REG_INVALID)
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output.printf("\t\t\toperands[%d].mem.index: REG = %s\n", c,
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instruction.regName(i.value.mem.index));
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if (i.value.mem.disp != 0)
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output.printf("\t\t\toperands[%d].mem.disp: 0x%x\n", c, i.value.mem.disp);
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if (i.value.mem.direct != 1)
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output.printf("\t\t\toperands[%d].mem.direct: -1\n", c);
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}
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}
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}
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output.println();
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}
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}
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/**
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* Obtains detailed assembly information of the specified disassembly.
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*
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* @param disassembly
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* An array with assembler commands (and operands) extracted from
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* machine code.
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* @return A dump of the assembler commands and information about their
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* occupied total bytes and affected registers etc.
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* @throws Exception
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* If any error occurs.
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*/
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private String createDisassemblyDetails(CsInsn[] disassembly) throws Exception {
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return AssemblyDetailDumper.createDisassemblyDetails(new XCoreDetailDumper(disassembler, disassembly));
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}
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@Test
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public void testBigEndianNormalSyntax() throws Exception {
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// XCore
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CsInsn[] disassembly = createDisassembler(Capstone.CS_ARCH_XCORE, Capstone.CS_MODE_BIG_ENDIAN,
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hexString2Byte(XCORE_CODE));
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assertDisassembly("/XCore/BigEndian/assembly_normal_syntax.asm", createDisassemblyDetails(disassembly));
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}
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}
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0x1000: get r11, ed
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op_count: 2
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operands[0].type: REG = r11
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operands[1].type: REG = ed
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0x1002: ldw et, sp[4]
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op_count: 2
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operands[0].type: REG = et
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operands[1].type: MEM
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operands[1].mem.base: REG = sp
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operands[1].mem.disp: 0x4
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0x1004: setd res[r3], r4
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op_count: 1
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operands[0].type: REG = r4
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0x1006: init t[r2]:lr, r1
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op_count: 2
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operands[0].type: MEM
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operands[0].mem.base: REG = r2
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operands[0].mem.index: REG = lr
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operands[1].type: REG = r1
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0x100a: divu r9, r1, r3
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op_count: 3
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operands[0].type: REG = r9
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operands[1].type: REG = r1
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operands[2].type: REG = r3
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0x100e: lda16 r9, r3[-r11]
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op_count: 1
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operands[0].type: REG = r9
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0x1012: ldw dp, dp[0x81c5]
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op_count: 1
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operands[0].type: REG = dp
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0x1016: lmul r11, r0, r2, r5, r8, r10
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op_count: 6
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operands[0].type: REG = r11
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operands[1].type: REG = r0
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operands[2].type: REG = r2
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operands[3].type: REG = r5
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operands[4].type: REG = r8
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operands[5].type: REG = r10
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0x101a: add r1, r2, r3
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op_count: 3
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operands[0].type: REG = r1
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operands[1].type: REG = r2
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operands[2].type: REG = r3
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0x101c: ldaw r8, r2[-9]
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op_count: 1
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operands[0].type: REG = r8
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