From 8e19b13abd69f73bfd90dd05225fee2018619d0e Mon Sep 17 00:00:00 2001 From: billow Date: Sat, 8 Apr 2023 05:17:49 +0800 Subject: [PATCH] fix --- arch/TriCore/TriCoreGenAsmWriter.inc | 16 +- arch/TriCore/TriCoreGenInstrInfo.inc | 682 +++++++++++++-------------- arch/TriCore/TriCoreInstrInfo.td | 2 +- suite/MC/TriCore/debug.s.cs | 2 +- 4 files changed, 350 insertions(+), 352 deletions(-) diff --git a/arch/TriCore/TriCoreGenAsmWriter.inc b/arch/TriCore/TriCoreGenAsmWriter.inc index 355714e7..2356a12b 100644 --- a/arch/TriCore/TriCoreGenAsmWriter.inc +++ b/arch/TriCore/TriCoreGenAsmWriter.inc @@ -993,7 +993,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 2231898387U, // LD_A_bo_pos 2198409491U, // LD_A_bo_pre 101191955U, // LD_A_bo_r - 50860307U, // LD_A_bol + 587731219U, // LD_A_bol 139409U, // LD_A_sc 2466779411U, // LD_A_slr 2500333843U, // LD_A_slr_post @@ -1009,7 +1009,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 2231900367U, // LD_BU_bo_pos 2198411471U, // LD_BU_bo_pre 101193935U, // LD_BU_bo_r - 50862287U, // LD_BU_bol + 587733199U, // LD_BU_bol 2466781391U, // LD_BU_slr 2500335823U, // LD_BU_slr_post 2500335823U, // LD_BU_slr_post_v110 @@ -1024,7 +1024,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 2231898621U, // LD_B_bo_pos 2198409725U, // LD_B_bo_pre 101192189U, // LD_B_bo_r - 50860541U, // LD_B_bol + 587731453U, // LD_B_bol 2500334077U, // LD_B_slr_post_v110 2466779645U, // LD_B_slr_v110 659965U, // LD_B_slro_v110 @@ -1047,14 +1047,14 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 2231900434U, // LD_HU_bo_pos 2198411538U, // LD_HU_bo_pre 101194002U, // LD_HU_bo_r - 50862354U, // LD_HU_bol + 587733266U, // LD_HU_bol 9442194U, // LD_H_abs 2198344594U, // LD_H_bo_bso 67638162U, // LD_H_bo_c 2231899026U, // LD_H_bo_pos 2198410130U, // LD_H_bo_pre 101192594U, // LD_H_bo_r - 50860946U, // LD_H_bol + 587731858U, // LD_H_bol 2466780050U, // LD_H_slr 2500334482U, // LD_H_slr_post 2500334482U, // LD_H_slr_post_v110 @@ -1075,7 +1075,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 2231900542U, // LD_W_bo_pos 2198411646U, // LD_W_bo_pre 101194110U, // LD_W_bo_r - 50862462U, // LD_W_bol + 587733374U, // LD_W_bol 139426U, // LD_W_sc 2466781566U, // LD_W_slr 2500335998U, // LD_W_slr_post @@ -1087,7 +1087,7 @@ MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) { 24321007U, // LD_W_sro_v110 9441727U, // LEA_abs 2198344127U, // LEA_bo_bso - 50860479U, // LEA_bol + 587731391U, // LEA_bol 9441732U, // LHA_abs 43355U, // LOOPU_brr 10491372U, // LOOP_brr @@ -3305,7 +3305,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O) { return; break; case 2: - // ADDIH_A_rlc, ADDIH_rlc, ADDI_rlc + // ADDIH_A_rlc, ADDIH_rlc, ADDI_rlc, LD_A_bol, LD_BU_bol, LD_B_bol, LD_HU... printSExtImm_16(MI, 2, O); return; break; diff --git a/arch/TriCore/TriCoreGenInstrInfo.inc b/arch/TriCore/TriCoreGenInstrInfo.inc index fe8701ee..e2707e59 100644 --- a/arch/TriCore/TriCoreGenInstrInfo.inc +++ b/arch/TriCore/TriCoreGenInstrInfo.inc @@ -1375,31 +1375,29 @@ static const MCOperandInfo OperandInfo84[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, static const MCOperandInfo OperandInfo85[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo86[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; static const MCOperandInfo OperandInfo87[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo88[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo89[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo90[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo91[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo92[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo93[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo94[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo95[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo96[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo97[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo98[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo99[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo100[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo101[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo102[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo103[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo104[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo105[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo106[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo107[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo108[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo109[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; -static const MCOperandInfo OperandInfo110[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; -static const MCOperandInfo OperandInfo111[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; -static const MCOperandInfo OperandInfo112[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo88[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo89[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo90[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo91[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo92[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo93[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo94[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo95[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo96[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo97[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo98[] = { { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo99[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo100[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo101[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo102[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo103[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo104[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo105[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo106[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo107[] = { { TriCore_RPRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; +static const MCOperandInfo OperandInfo108[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, }; +static const MCOperandInfo OperandInfo109[] = { { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RARegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { TriCore_RDRegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, }; +static const MCOperandInfo OperandInfo110[] = { { TriCore_RERegClassID, 0, MCOI_OPERAND_REGISTER, 0 }, }; static const MCInstrDesc TriCoreInsts[] = { { 1, OperandInfo2 }, @@ -1976,7 +1974,7 @@ static const MCInstrDesc TriCoreInsts[] = { { 3, OperandInfo50 }, { 3, OperandInfo50 }, { 2, OperandInfo87 }, - { 3, OperandInfo88 }, + { 3, OperandInfo50 }, { 1, OperandInfo2 }, { 2, OperandInfo54 }, { 2, OperandInfo54 }, @@ -1987,12 +1985,12 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo53 }, { 2, OperandInfo53 }, { 2, OperandInfo55 }, + { 3, OperandInfo88 }, { 3, OperandInfo89 }, - { 3, OperandInfo90 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo91 }, - { 3, OperandInfo92 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo90 }, + { 3, OperandInfo88 }, { 2, OperandInfo71 }, { 2, OperandInfo71 }, { 2, OperandInfo71 }, @@ -2002,22 +2000,22 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo53 }, { 2, OperandInfo53 }, { 2, OperandInfo55 }, + { 3, OperandInfo88 }, { 3, OperandInfo89 }, - { 3, OperandInfo90 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo91 }, - { 3, OperandInfo92 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo90 }, + { 3, OperandInfo88 }, { 2, OperandInfo71 }, { 2, OperandInfo71 }, { 2, OperandInfo55 }, { 2, OperandInfo53 }, { 2, OperandInfo58 }, - { 3, OperandInfo93 }, - { 3, OperandInfo94 }, - { 3, OperandInfo93 }, - { 3, OperandInfo93 }, - { 2, OperandInfo95 }, + { 3, OperandInfo91 }, + { 3, OperandInfo92 }, + { 3, OperandInfo91 }, + { 3, OperandInfo91 }, + { 2, OperandInfo93 }, { 2, OperandInfo85 }, { 3, OperandInfo63 }, { 3, OperandInfo64 }, @@ -2025,19 +2023,19 @@ static const MCInstrDesc TriCoreInsts[] = { { 3, OperandInfo63 }, { 2, OperandInfo65 }, { 2, OperandInfo55 }, + { 3, OperandInfo88 }, { 3, OperandInfo89 }, - { 3, OperandInfo90 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo91 }, - { 3, OperandInfo92 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo90 }, + { 3, OperandInfo88 }, { 2, OperandInfo55 }, + { 3, OperandInfo88 }, { 3, OperandInfo89 }, - { 3, OperandInfo90 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo91 }, - { 3, OperandInfo92 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo90 }, + { 3, OperandInfo88 }, { 2, OperandInfo71 }, { 2, OperandInfo71 }, { 2, OperandInfo71 }, @@ -2047,18 +2045,18 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo53 }, { 2, OperandInfo53 }, { 2, OperandInfo55 }, + { 3, OperandInfo88 }, { 3, OperandInfo89 }, - { 3, OperandInfo90 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo91 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo90 }, { 2, OperandInfo55 }, + { 3, OperandInfo88 }, { 3, OperandInfo89 }, - { 3, OperandInfo90 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo91 }, - { 3, OperandInfo92 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo90 }, + { 3, OperandInfo88 }, { 1, OperandInfo2 }, { 2, OperandInfo71 }, { 2, OperandInfo71 }, @@ -2070,7 +2068,7 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo53 }, { 2, OperandInfo53 }, { 3, OperandInfo50 }, - { 3, OperandInfo88 }, + { 3, OperandInfo50 }, { 2, OperandInfo53 }, { 1, OperandInfo2 }, { 2, OperandInfo53 }, @@ -2090,113 +2088,113 @@ static const MCInstrDesc TriCoreInsts[] = { { 3, OperandInfo45 }, { 2, OperandInfo55 }, { 2, OperandInfo47 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, { 4, OperandInfo61 }, - { 4, OperandInfo97 }, + { 4, OperandInfo95 }, { 4, OperandInfo62 }, - { 4, OperandInfo98 }, + { 4, OperandInfo96 }, { 4, OperandInfo61 }, - { 4, OperandInfo97 }, + { 4, OperandInfo95 }, { 4, OperandInfo62 }, - { 4, OperandInfo98 }, + { 4, OperandInfo96 }, { 4, OperandInfo62 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, { 4, OperandInfo61 }, - { 4, OperandInfo97 }, + { 4, OperandInfo95 }, { 4, OperandInfo62 }, - { 4, OperandInfo98 }, + { 4, OperandInfo96 }, { 3, OperandInfo45 }, { 3, OperandInfo45 }, { 3, OperandInfo45 }, @@ -2222,8 +2220,8 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo54 }, { 3, OperandInfo52 }, { 2, OperandInfo53 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, { 3, OperandInfo72 }, { 2, OperandInfo71 }, { 2, OperandInfo71 }, @@ -2238,137 +2236,137 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo55 }, { 2, OperandInfo85 }, { 2, OperandInfo47 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo100 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo98 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, { 4, OperandInfo61 }, - { 4, OperandInfo97 }, + { 4, OperandInfo95 }, { 4, OperandInfo62 }, - { 4, OperandInfo98 }, + { 4, OperandInfo96 }, { 4, OperandInfo61 }, - { 4, OperandInfo97 }, + { 4, OperandInfo95 }, { 4, OperandInfo62 }, - { 4, OperandInfo98 }, + { 4, OperandInfo96 }, { 4, OperandInfo62 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo99 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 5, OperandInfo96 }, - { 4, OperandInfo97 }, - { 4, OperandInfo98 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo97 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 5, OperandInfo94 }, + { 4, OperandInfo95 }, + { 4, OperandInfo96 }, { 4, OperandInfo61 }, - { 4, OperandInfo97 }, + { 4, OperandInfo95 }, { 4, OperandInfo62 }, - { 4, OperandInfo98 }, - { 2, OperandInfo102 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 3, OperandInfo104 }, + { 4, OperandInfo96 }, + { 2, OperandInfo100 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 3, OperandInfo102 }, { 3, OperandInfo69 }, - { 3, OperandInfo104 }, + { 3, OperandInfo102 }, { 3, OperandInfo69 }, { 3, OperandInfo69 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, { 3, OperandInfo45 }, { 4, OperandInfo61 }, { 4, OperandInfo61 }, - { 3, OperandInfo104 }, + { 3, OperandInfo102 }, { 3, OperandInfo69 }, { 3, OperandInfo69 }, { 3, OperandInfo46 }, @@ -2376,23 +2374,23 @@ static const MCInstrDesc TriCoreInsts[] = { { 3, OperandInfo45 }, { 3, OperandInfo45 }, { 3, OperandInfo69 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, { 3, OperandInfo69 }, { 4, OperandInfo61 }, { 4, OperandInfo61 }, { 4, OperandInfo61 }, { 4, OperandInfo61 }, - { 4, OperandInfo103 }, + { 4, OperandInfo101 }, { 4, OperandInfo61 }, - { 4, OperandInfo103 }, - { 4, OperandInfo103 }, - { 3, OperandInfo104 }, + { 4, OperandInfo101 }, + { 4, OperandInfo101 }, + { 3, OperandInfo102 }, { 3, OperandInfo69 }, { 3, OperandInfo46 }, - { 3, OperandInfo104 }, + { 3, OperandInfo102 }, { 3, OperandInfo45 }, { 3, OperandInfo69 }, { 3, OperandInfo45 }, @@ -2523,10 +2521,10 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo53 }, { 2, OperandInfo53 }, { 3, OperandInfo50 }, - { 3, OperandInfo93 }, + { 3, OperandInfo91 }, { 3, OperandInfo50 }, { 3, OperandInfo50 }, - { 2, OperandInfo105 }, + { 2, OperandInfo103 }, { 3, OperandInfo50 }, { 1, OperandInfo2 }, { 2, OperandInfo53 }, @@ -2538,72 +2536,72 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo53 }, { 2, OperandInfo53 }, { 2, OperandInfo55 }, - { 3, OperandInfo89 }, - { 3, OperandInfo106 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo107 }, + { 3, OperandInfo88 }, + { 3, OperandInfo104 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo105 }, { 3, OperandInfo51 }, { 2, OperandInfo53 }, { 2, OperandInfo53 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, { 2, OperandInfo55 }, { 2, OperandInfo55 }, { 2, OperandInfo58 }, - { 3, OperandInfo93 }, - { 3, OperandInfo94 }, - { 3, OperandInfo93 }, - { 3, OperandInfo93 }, - { 2, OperandInfo95 }, + { 3, OperandInfo91 }, + { 3, OperandInfo92 }, + { 3, OperandInfo91 }, + { 3, OperandInfo91 }, + { 2, OperandInfo93 }, { 2, OperandInfo85 }, { 3, OperandInfo63 }, - { 3, OperandInfo108 }, - { 3, OperandInfo63 }, - { 3, OperandInfo63 }, - { 2, OperandInfo109 }, - { 2, OperandInfo55 }, - { 3, OperandInfo89 }, { 3, OperandInfo106 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, + { 3, OperandInfo63 }, + { 3, OperandInfo63 }, { 2, OperandInfo107 }, + { 2, OperandInfo55 }, + { 3, OperandInfo88 }, + { 3, OperandInfo104 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo105 }, { 3, OperandInfo51 }, { 2, OperandInfo53 }, { 2, OperandInfo53 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, { 2, OperandInfo55 }, { 2, OperandInfo55 }, { 2, OperandInfo55 }, - { 3, OperandInfo89 }, - { 3, OperandInfo106 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo107 }, - { 3, OperandInfo110 }, + { 3, OperandInfo88 }, + { 3, OperandInfo104 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo105 }, + { 3, OperandInfo108 }, { 2, OperandInfo55 }, - { 3, OperandInfo89 }, - { 3, OperandInfo106 }, - { 3, OperandInfo89 }, - { 3, OperandInfo89 }, - { 2, OperandInfo107 }, + { 3, OperandInfo88 }, + { 3, OperandInfo104 }, + { 3, OperandInfo88 }, + { 3, OperandInfo88 }, + { 2, OperandInfo105 }, { 3, OperandInfo51 }, { 1, OperandInfo2 }, { 2, OperandInfo53 }, { 2, OperandInfo53 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, - { 2, OperandInfo101 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, + { 2, OperandInfo99 }, { 2, OperandInfo55 }, { 2, OperandInfo55 }, { 3, OperandInfo45 }, - { 4, OperandInfo111 }, + { 4, OperandInfo109 }, { 3, OperandInfo45 }, { 3, OperandInfo45 }, { 3, OperandInfo45 }, @@ -2624,28 +2622,28 @@ static const MCInstrDesc TriCoreInsts[] = { { 2, OperandInfo47 }, { 0, 0 }, { 3, OperandInfo63 }, - { 3, OperandInfo108 }, + { 3, OperandInfo106 }, { 3, OperandInfo63 }, { 3, OperandInfo63 }, - { 2, OperandInfo109 }, + { 2, OperandInfo107 }, { 2, OperandInfo53 }, { 3, OperandInfo50 }, - { 3, OperandInfo93 }, + { 3, OperandInfo91 }, { 3, OperandInfo50 }, { 3, OperandInfo50 }, - { 2, OperandInfo105 }, + { 2, OperandInfo103 }, { 2, OperandInfo53 }, { 3, OperandInfo50 }, - { 3, OperandInfo93 }, - { 3, OperandInfo89 }, + { 3, OperandInfo91 }, + { 3, OperandInfo88 }, { 3, OperandInfo50 }, { 3, OperandInfo50 }, - { 2, OperandInfo105 }, + { 2, OperandInfo103 }, { 1, OperandInfo2 }, { 1, OperandInfo68 }, { 0, 0 }, { 0, 0 }, - { 1, OperandInfo112 }, + { 1, OperandInfo110 }, { 1, OperandInfo68 }, { 1, OperandInfo68 }, { 0, 0 }, diff --git a/arch/TriCore/TriCoreInstrInfo.td b/arch/TriCore/TriCoreInstrInfo.td index cd8287ae..95ae6308 100644 --- a/arch/TriCore/TriCoreInstrInfo.td +++ b/arch/TriCore/TriCoreInstrInfo.td @@ -1126,7 +1126,7 @@ class IABS_OR op1, bits<2> op2, string asmstr, RegisterClass s1c> asmstr # " $off18, $s1", []>; class IBOL_RAaO op1, string asmstr, RegisterClass RC> - : BOL; class IBOL_AbOR op1, string asmstr, RegisterClass RC> diff --git a/suite/MC/TriCore/debug.s.cs b/suite/MC/TriCore/debug.s.cs index 366c3475..ce6cebb8 100644 --- a/suite/MC/TriCore/debug.s.cs +++ b/suite/MC/TriCore/debug.s.cs @@ -1,2 +1,2 @@ # CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None -0x60,0xf2 = mov.a %a2, %d15 +0xd9,0x33,0xc0,0x4f = lea %a3, [%a3]-768