Virtualization
/
capstone
mirror of https://gitlab.com/qemu-project/capstone.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

arm: correct the alias instruction id for MOVsi instructions. bug reported by @joelpx

This commit is contained in:
Nguyen Anh Quynh 2015-05-02 11:38:34 +08:00
parent 98a0b20df6
commit 91a1cb4b03
3 changed files with 25 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/ARM/ARMGenAsmWriter.inc
View File

@ -6072,6 +6072,7 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
}; };
#endif #endif
// printf(">>> opcode: %u\n", MCInst_getOpcode(MI));
// Emit the opcode for the instruction. // Emit the opcode for the instruction.
uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)]; uint64_t Bits1 = OpInfo[MCInst_getOpcode(MI)];
uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)]; uint64_t Bits2 = OpInfo2[MCInst_getOpcode(MI)];

24
arch/ARM/ARMInstPrinter.c
View File

@ -431,6 +431,7 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode; unsigned Opcode = MCInst_getOpcode(MI), tmp, i, pubOpcode;
// printf(">>> Opcode 0: %u\n", MCInst_getOpcode(MI));
switch(Opcode) { switch(Opcode) {
// Check for HINT instructions w/ canonical names. // Check for HINT instructions w/ canonical names.
case ARM_HINT: case ARM_HINT:
@ -507,11 +508,32 @@ void ARM_printInst(MCInst *MI, SStream *O, void *Info)
case ARM_MOVsi: { case ARM_MOVsi: {
// FIXME: Thumb variants? // FIXME: Thumb variants?
unsigned int opc;
MCOperand *Dst = MCInst_getOperand(MI, 0); MCOperand *Dst = MCInst_getOperand(MI, 0);
MCOperand *MO1 = MCInst_getOperand(MI, 1); MCOperand *MO1 = MCInst_getOperand(MI, 1);
MCOperand *MO2 = MCInst_getOperand(MI, 2); MCOperand *MO2 = MCInst_getOperand(MI, 2);
SStream_concat0(O, ARM_AM_getShiftOpcStr(ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2)))); opc = ARM_AM_getSORegShOp((unsigned int)MCOperand_getImm(MO2));
SStream_concat0(O, ARM_AM_getShiftOpcStr(opc));
switch(opc) {
default:
break;
case ARM_AM_asr:
MCInst_setOpcodePub(MI, ARM_INS_ASR);
break;
case ARM_AM_lsl:
MCInst_setOpcodePub(MI, ARM_INS_LSL);
break;
case ARM_AM_lsr:
MCInst_setOpcodePub(MI, ARM_INS_LSR);
break;
case ARM_AM_ror:
MCInst_setOpcodePub(MI, ARM_INS_ROR);
break;
case ARM_AM_rrx:
MCInst_setOpcodePub(MI, ARM_INS_RRX);
break;
}
printSBitModifierOperand(MI, 5, O); printSBitModifierOperand(MI, 5, O);
printPredicateOperand(MI, 3, O); printPredicateOperand(MI, 3, O);

2
bindings/python/test_arm.py
View File

@ -27,7 +27,7 @@ all_tests = (
def print_insn_detail(insn): def print_insn_detail(insn):
# print address, mnemonic and operands # print address, mnemonic and operands
print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) print("0x%x:\t%s\t%s" % (insn.id, insn.address, insn.mnemonic, insn.op_str))
# "data" instruction generated by SKIPDATA option has no detail # "data" instruction generated by SKIPDATA option has no detail
if insn.id == 0: if insn.id == 0: