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Merge pull request #281 from radare/indent 

Fix indent issue
This commit is contained in:
Nguyen Anh Quynh 2015-03-11 08:54:18 +08:00
parent 037e01f942 21b0bdd0e1
commit 956c24d760
7 changed files with 7 additions and 7 deletions
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2
arch/AArch64/AArch64MappingInsn.inc
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@ -4,7 +4,7 @@
{ {
AArch64_ABSv16i8, ARM64_INS_ABS, AArch64_ABSv16i8, ARM64_INS_ABS,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0 { 0 }, { 0 }, { ARM64_GRP_NEON, 0 }, 0, 0
#endif #endif
}, },
{ {

2
arch/ARM/ARMMappingInsn.inc
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@ -4,7 +4,7 @@
{ {
ARM_ADCri, ARM_INS_ADC, ARM_ADCri, ARM_INS_ADC,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0 { ARM_REG_CPSR, 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_ARM, 0 }, 0, 0
#endif #endif
}, },
{ {

2
arch/Mips/MipsMappingInsn.inc
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@ -4,7 +4,7 @@
{ {
Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S, Mips_ABSQ_S_PH, MIPS_INS_ABSQ_S,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0 { 0 }, { MIPS_REG_DSPOUTFLAG20, 0 }, { MIPS_GRP_DSP, 0 }, 0, 0
#endif #endif
}, },
{ {

2
arch/PowerPC/PPCMappingInsn.inc
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@ -4,7 +4,7 @@
{ {
PPC_ADD4, PPC_INS_ADD, PPC_ADD4, PPC_INS_ADD,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0 { 0 }, { 0 }, { 0 }, 0, 0
#endif #endif
}, },
{ {

2
arch/Sparc/SparcMappingInsn.inc
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@ -4,7 +4,7 @@
{ {
SP_ADDCCri, SPARC_INS_ADDCC, SP_ADDCCri, SPARC_INS_ADDCC,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0 { 0 }, { SPARC_REG_ICC, 0 }, { 0 }, 0, 0
#endif #endif
}, },
{ {

2
arch/SystemZ/SystemZMappingInsn.inc
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@ -4,7 +4,7 @@
{ {
SystemZ_A, SYSZ_INS_A, SystemZ_A, SYSZ_INS_A,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0 { 0 }, { SYSZ_REG_CC, 0 }, { 0 }, 0, 0
#endif #endif
}, },
{ {

2
arch/XCore/XCoreMappingInsn.inc
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@ -4,7 +4,7 @@
{ {
XCore_ADD_2rus, XCORE_INS_ADD, XCore_ADD_2rus, XCORE_INS_ADD,
#ifndef CAPSTONE_DIET #ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0 { 0 }, { 0 }, { 0 }, 0, 0
#endif #endif
}, },
{ {