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fix

This commit is contained in:
billow 2023-03-26 07:56:18 +08:00
parent e5b44ff47c
commit 98f0eb61a8
5 changed files with 62 additions and 58 deletions
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106
arch/TriCore/TriCoreDisassembler.c
View File

@ -324,8 +324,8 @@ static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
switch (MCInst_getOpcode(Inst)) {
case TriCore_ADD_src:
status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
if (status == MCDisassembler_Success)
status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
// if (status == MCDisassembler_Success)
// status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
break;
default:
status = DecodeDataRegsRegisterClass(Inst, s1_d, Address, Decoder);
@ -710,6 +710,7 @@ static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
case TriCore_MOV_rlcEc:
case TriCore_MOV_U_rlc:
case TriCore_MOV_H_rlc:
case TriCore_MOVH_A_rlc:
break;
}
if (status != MCDisassembler_Success)
@ -1063,6 +1064,11 @@ static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1078,11 +1084,6 @@ static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1098,6 +1099,11 @@ static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1116,11 +1122,6 @@ static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1136,6 +1137,11 @@ static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t A
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1152,11 +1158,6 @@ static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t A
// Decode pos2.
MCOperand_CreateImm0(Inst, pos2);
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1171,6 +1172,11 @@ static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t A
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1184,11 +1190,6 @@ static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t A
// Decode n.
MCOperand_CreateImm0(Inst, n);
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1203,6 +1204,11 @@ static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1216,11 +1222,6 @@ static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1236,6 +1237,11 @@ static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1254,11 +1260,6 @@ static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1273,6 +1274,12 @@ static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1286,11 +1293,6 @@ static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1305,6 +1307,11 @@ static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1320,11 +1327,6 @@ static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1390,6 +1392,11 @@ static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1408,11 +1415,6 @@ static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t A
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}
@ -1454,6 +1456,11 @@ static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (!is32Bit) // This instruction is 32-bit
return MCDisassembler_Fail;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
// Decode s1.
status = DecodeDataRegsRegisterClass(Inst, s1, Address, Decoder);
if (status != MCDisassembler_Success)
@ -1470,11 +1477,6 @@ static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t
if (status != MCDisassembler_Success)
return status;
// Decode d.
status = DecodeDataRegsRegisterClass(Inst, d, Address, Decoder);
if (status != MCDisassembler_Success)
return status;
return MCDisassembler_Success;
}

2
arch/TriCore/TriCoreGenAsmWriter.inc
View File

@ -2730,7 +2730,7 @@ void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
break;
case 10:
// MOVH_A_rlc, MOV_H_rlc, MOV_U_rlc, MOV_rlcDc, MOV_rlcEc
printSExtImm_16(MI, 1, O);
printZExtImm_16(MI, 1, O);
return;
break;
case 11:

8
arch/TriCore/TriCoreInstPrinter.c
View File

@ -163,8 +163,8 @@ static void sign_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int64_t imm = MCOperand_getImm(MO);
bool sign = imm >> (n - 1) & 0x1;
for (unsigned i = n + 1; i < 64; ++i) {
int64_t sign = imm >> (n - 1) & 0x1;
for (unsigned i = n; i < 64; ++i) {
imm = (imm & ~(1LL << i)) | (sign << i);
}
if (imm >= 0) {
@ -195,7 +195,7 @@ static void zero_ext(MCInst *MI, int OpNum, SStream *O, unsigned n) {
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int64_t imm = MCOperand_getImm(MO);
const bool sign = 0;
const int64_t sign = 0;
for (unsigned i = n + 1; i < 64; ++i) {
imm = (imm & ~(1LL << i)) | (sign << i);
}
@ -268,6 +268,8 @@ static inline void printZExtImm(MCInst *MI, int OpNum, SStream *O) {
zero_ext(MI, OpNum, O, n); \
}
printZExtImm_(16)
printZExtImm_(8)
printZExtImm_(4)

2
arch/TriCore/TriCoreInstrInfo.td
View File

@ -1349,7 +1349,7 @@ defm MIN_B : mIU__RR_ab<0x0B, 0x58, 0x0B, 0x59, "min.b">;
defm MIN_H : mIU__RR_ab<0x0B, 0x78, 0x0B, 0x79, "min.h">;
class IRLC_1<bits<8> op1, string asmstr, RegisterClass rc>
: RLC<op1, (outs rc:$d), (ins s16imm:$const16),
: RLC<op1, (outs rc:$d), (ins u16imm:$const16),
asmstr # " $d, $const16", []>;
class ISRC_1<bits<8> op1, string asmstr, RegisterClass rc>

2
suite/MC/TriCore/debug.s.cs
View File

@ -1,2 +1,2 @@
# CS_ARCH_TRICORE, CS_MODE_TRICORE, None
0x82,0xf1 = mov %d1, -1
0x91,0x00,0x00,0xf8 = movh.a %a15, 32768