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Relative branch group (#964) 

* Add a new group for relative branching instructions

* x86: Add relative branch group to appropiate instructions

* Rename RELATIVE_BRANCH to BRANCH_RELATIVE

* aarch64: Add relative branch group to appropiate instructions

* arm: Add relative branch group to appropiate instructions

* m68k: Add relative branch group to appropiate instructions

* mips: Add relative branch group to appropiate instructions
This commit is contained in:
Alfredo Beaumont 2017-07-30 13:05:03 +02:00 committed by Nguyen Anh Quynh
parent fef1c2920a
commit a09a81813c
11 changed files with 210 additions and 194 deletions
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24
arch/AArch64/AArch64MappingInsn.inc
View File

@ -430,7 +430,7 @@
{
AArch64_B, ARM64_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
@ -532,13 +532,13 @@
{
AArch64_BL, ARM64_INS_BL,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
AArch64_BLR, ARM64_INS_BLR,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, 0 }, 1, 1
{ 0 }, { ARM64_REG_LR, 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 1
#endif
},
{
@ -568,31 +568,31 @@
{
AArch64_Bcc, ARM64_INS_B,
#ifndef CAPSTONE_DIET
{ ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ ARM64_REG_NZCV, 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
AArch64_CBNZW, ARM64_INS_CBNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
AArch64_CBNZX, ARM64_INS_CBNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
AArch64_CBZW, ARM64_INS_CBZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
AArch64_CBZX, ARM64_INS_CBZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
@ -11632,13 +11632,13 @@
{
AArch64_TBNZW, ARM64_INS_TBNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
AArch64_TBNZX, ARM64_INS_TBNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
@ -11692,13 +11692,13 @@
{
AArch64_TBZW, ARM64_INS_TBZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
AArch64_TBZX, ARM64_INS_TBZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM64_GRP_JUMP, 0 }, 1, 0
{ 0 }, { 0 }, { ARM64_GRP_JUMP, ARM64_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{

24
arch/ARM/ARMMappingInsn.inc
View File

@ -148,7 +148,7 @@
{
ARM_BL, ARM_INS_BL,
#ifndef CAPSTONE_DIET
{ ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, 0 }, 1, 0
{ ARM_REG_PC, 0 }, { ARM_REG_LR, ARM_REG_PC, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0
#endif
},
{
@ -166,13 +166,13 @@
{
ARM_BLXi, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, ARM_GRP_V5T, 0 }, 1, 0
#endif
},
{
ARM_BL_pred, ARM_INS_BL,
#ifndef CAPSTONE_DIET
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_ARM, 0 }, 1, 0
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_CALL, ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0
#endif
},
{
@ -202,7 +202,7 @@
{
ARM_Bcc, ARM_INS_B,
#ifndef CAPSTONE_DIET
{ ARM_REG_PC, 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_ARM, 0 }, 1, 0
{ ARM_REG_PC, 0 }, { ARM_REG_PC, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_ARM, 0 }, 1, 0
#endif
},
{
@ -10732,7 +10732,7 @@
{
ARM_t2B, ARM_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
{ 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0
#endif
},
{
@ -10774,7 +10774,7 @@
{
ARM_t2Bcc, ARM_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
{ 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0
#endif
},
{
@ -12904,7 +12904,7 @@
{
ARM_tB, ARM_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
{ 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
#endif
},
{
@ -12922,13 +12922,13 @@
{
ARM_tBL, ARM_INS_BL,
#ifndef CAPSTONE_DIET
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_CALL, 0 }, 1, 0
#endif
},
{
ARM_tBLXi, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0
{ ARM_REG_PC, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, ARM_GRP_CALL, 0 }, 1, 0
#endif
},
{
@ -12946,19 +12946,19 @@
{
ARM_tBcc, ARM_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
{ 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 1, 0
#endif
},
{
ARM_tCBNZ, ARM_INS_CBNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
{ 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0
#endif
},
{
ARM_tCBZ, ARM_INS_CBZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 1, 0
{ 0 }, { 0 }, { ARM_GRP_BRANCH_RELATIVE, ARM_GRP_THUMB2, 0 }, 1, 0
#endif
},
{

8
arch/M68K/M68KDisassembler.c
View File

@ -771,6 +771,7 @@ static void build_bxx(m68k_info *info, int opcode, int size, int jump_offset)
op->imm = jump_offset;
set_insn_group(info, M68K_GRP_JUMP);
set_insn_group(info, M68K_GRP_BRANCH_RELATIVE);
}
static void build_bcc(m68k_info *info, int size, int jump_offset)
@ -800,6 +801,7 @@ static void build_dbxx(m68k_info *info, int opcode, int size, int jump_offset)
op1->imm = jump_offset;
set_insn_group(info, M68K_GRP_JUMP);
set_insn_group(info, M68K_GRP_BRANCH_RELATIVE);
}
static void build_dbcc(m68k_info *info, int size, int jump_offset)
@ -1806,6 +1808,8 @@ static void d68020_cpbcc_16(m68k_info *info)
op0->address_mode = M68K_AM_IMMEDIATE;
op0->type = M68K_OP_IMM;
op0->imm = new_pc;
set_insn_group(info, M68K_GRP_BRANCH_RELATIVE);
}
static void d68020_cpbcc_32(m68k_info *info)
@ -1830,6 +1834,8 @@ static void d68020_cpbcc_32(m68k_info *info)
op0->type = M68K_OP_IMM;
op0->address_mode = M68K_AM_IMMEDIATE;
op0->imm = new_pc;
set_insn_group(info, M68K_GRP_BRANCH_RELATIVE);
}
static void d68020_cpdbcc(m68k_info *info)
@ -1859,6 +1865,8 @@ static void d68020_cpdbcc(m68k_info *info)
op1->address_mode = M68K_AM_IMMEDIATE;
op1->type = M68K_OP_IMM;
op1->imm = new_pc;
set_insn_group(info, M68K_GRP_BRANCH_RELATIVE);
}
static void fmove_fpcr(m68k_info *info, uint extension)

216
arch/Mips/MipsMappingInsn.inc
View File

@ -634,7 +634,7 @@
{
Mips_B16_MM, MIPS_INS_B16,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
@ -646,13 +646,13 @@
{
Mips_BAL, MIPS_INS_BAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BALC, MIPS_INS_BALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
@ -664,163 +664,163 @@
{
Mips_BBIT0, MIPS_INS_BBIT0,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BBIT032, MIPS_INS_BBIT032,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BBIT1, MIPS_INS_BBIT1,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BBIT132, MIPS_INS_BBIT132,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_CNMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_CNMIPS, 0 }, 1, 0
#endif
},
{
Mips_BC, MIPS_INS_BC,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC0F, MIPS_INS_BC0F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC0FL, MIPS_INS_BC0FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC0T, MIPS_INS_BC0T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC0TL, MIPS_INS_BC0TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1EQZ, MIPS_INS_BC1EQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC1F, MIPS_INS_BC1F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1FL, MIPS_INS_BC1FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1F_MM, MIPS_INS_BC1F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BC1NEZ, MIPS_INS_BC1NEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC1T, MIPS_INS_BC1T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1TL, MIPS_INS_BC1TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC1T_MM, MIPS_INS_BC1T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BC2EQZ, MIPS_INS_BC2EQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC2F, MIPS_INS_BC2F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC2FL, MIPS_INS_BC2FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC2NEZ, MIPS_INS_BC2NEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BC2T, MIPS_INS_BC2T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC2TL, MIPS_INS_BC2TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3F, MIPS_INS_BC3F,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3FL, MIPS_INS_BC3FL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3T, MIPS_INS_BC3T,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BC3TL, MIPS_INS_BC3TL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
@ -874,163 +874,163 @@
{
Mips_BEQ, MIPS_INS_BEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BEQ64, MIPS_INS_BEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BEQC, MIPS_INS_BEQC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BEQL, MIPS_INS_BEQL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BEQZ16_MM, MIPS_INS_BEQZ16,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BEQZALC, MIPS_INS_BEQZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BEQZC, MIPS_INS_BEQZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BEQZC_MM, MIPS_INS_BEQZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BEQ_MM, MIPS_INS_BEQ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BGEC, MIPS_INS_BGEC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEUC, MIPS_INS_BGEUC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZ, MIPS_INS_BGEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGEZ64, MIPS_INS_BGEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGEZAL, MIPS_INS_BGEZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BGEZALC, MIPS_INS_BGEZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZALL, MIPS_INS_BGEZALL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BGEZALS_MM, MIPS_INS_BGEZALS,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BGEZAL_MM, MIPS_INS_BGEZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BGEZC, MIPS_INS_BGEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZL, MIPS_INS_BGEZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BGEZ_MM, MIPS_INS_BGEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BGTZ, MIPS_INS_BGTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGTZ64, MIPS_INS_BGTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BGTZALC, MIPS_INS_BGTZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGTZC, MIPS_INS_BGTZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BGTZL, MIPS_INS_BGTZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BGTZ_MM, MIPS_INS_BGTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
@ -1144,109 +1144,109 @@
{
Mips_BLEZ, MIPS_INS_BLEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLEZ64, MIPS_INS_BLEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLEZALC, MIPS_INS_BLEZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLEZC, MIPS_INS_BLEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLEZL, MIPS_INS_BLEZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BLEZ_MM, MIPS_INS_BLEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BLTC, MIPS_INS_BLTC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTUC, MIPS_INS_BLTUC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZ, MIPS_INS_BLTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLTZ64, MIPS_INS_BLTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BLTZAL, MIPS_INS_BLTZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BLTZALC, MIPS_INS_BLTZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZALL, MIPS_INS_BLTZALL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 0, 0
#endif
},
{
Mips_BLTZALS_MM, MIPS_INS_BLTZALS,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BLTZAL_MM, MIPS_INS_BLTZAL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 0, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 0, 0
#endif
},
{
Mips_BLTZC, MIPS_INS_BLTZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZL, MIPS_INS_BLTZL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BLTZ_MM, MIPS_INS_BLTZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
@ -1276,19 +1276,19 @@
{
Mips_BNE, MIPS_INS_BNE,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BNE64, MIPS_INS_BNE,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, 0 }, 1, 0
#endif
},
{
Mips_BNEC, MIPS_INS_BNEC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
@ -1342,85 +1342,85 @@
{
Mips_BNEL, MIPS_INS_BNEL,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS2, MIPS_GRP_NOTMIPS32R6, MIPS_GRP_NOTMIPS64R6, 0 }, 1, 0
#endif
},
{
Mips_BNEZ16_MM, MIPS_INS_BNEZ16,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BNEZALC, MIPS_INS_BNEZALC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_RA, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BNEZC, MIPS_INS_BNEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BNEZC_MM, MIPS_INS_BNEZC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BNE_MM, MIPS_INS_BNE,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MICROMIPS, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MICROMIPS, 0 }, 1, 0
#endif
},
{
Mips_BNVC, MIPS_INS_BNVC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BNZ_B, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_D, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_H, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_V, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BNZ_W, MIPS_INS_BNZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BOVC, MIPS_INS_BOVC,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_STDENC, MIPS_GRP_MIPS32R6, 0 }, 1, 0
#endif
},
{
Mips_BPOSGE32, MIPS_INS_BPOSGE32,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_DSP, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_DSP, 0 }, 1, 0
#endif
},
{
@ -1504,97 +1504,97 @@
{
Mips_BZ_B, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_D, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_H, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_V, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BZ_W, MIPS_INS_BZ,
#ifndef CAPSTONE_DIET
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_MSA, 0 }, 1, 0
{ 0 }, { MIPS_REG_AT, 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MSA, 0 }, 1, 0
#endif
},
{
Mips_BeqzRxImm16, MIPS_INS_BEQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BeqzRxImmX16, MIPS_INS_BEQZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_Bimm16, MIPS_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BimmX16, MIPS_INS_B,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BnezRxImm16, MIPS_INS_BNEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BnezRxImmX16, MIPS_INS_BNEZ,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_Break16, MIPS_INS_BREAK,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 0, 0
{ 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 0, 0
#endif
},
{
Mips_Bteqz16, MIPS_INS_BTEQZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BteqzX16, MIPS_INS_BTEQZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_Btnez16, MIPS_INS_BTNEZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{
Mips_BtnezX16, MIPS_INS_BTNEZ,
#ifndef CAPSTONE_DIET
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_MIPS16MODE, 0 }, 1, 0
{ MIPS_REG_T8, 0 }, { 0 }, { MIPS_GRP_BRANCH_RELATIVE, MIPS_GRP_MIPS16MODE, 0 }, 1, 0
#endif
},
{

124
arch/X86/X86MappingInsn.inc
View File

@ -1798,7 +1798,7 @@
{
X86_CALL64pcrel32, X86_INS_CALL,
#ifndef CAPSTONE_DIET
{ X86_REG_RSP, X86_REG_RIP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_MODE64, 0 }, 0, 0
{ X86_REG_RSP, X86_REG_RIP, 0 }, { X86_REG_RSP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, X86_GRP_MODE64, 0 }, 0, 0
#endif
},
{
@ -1810,13 +1810,13 @@
{
X86_CALLpcrel16, X86_INS_CALL,
#ifndef CAPSTONE_DIET
{ X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, 0 }, 0, 0
{ X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0
#endif
},
{
X86_CALLpcrel32, X86_INS_CALL,
#ifndef CAPSTONE_DIET
{ X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_NOT64BITMODE, 0 }, 0, 0
{ X86_REG_ESP, X86_REG_EIP, 0 }, { X86_REG_ESP, 0 }, { X86_GRP_CALL, X86_GRP_BRANCH_RELATIVE, X86_GRP_NOT64BITMODE, 0 }, 0, 0
#endif
},
{
@ -5440,175 +5440,175 @@
{
X86_JAE_1, X86_INS_JAE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JAE_2, X86_INS_JAE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JAE_4, X86_INS_JAE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JA_1, X86_INS_JA,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JA_2, X86_INS_JA,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JA_4, X86_INS_JA,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JBE_1, X86_INS_JBE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JBE_2, X86_INS_JBE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JBE_4, X86_INS_JBE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JB_1, X86_INS_JB,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JB_2, X86_INS_JB,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JB_4, X86_INS_JB,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JCXZ, X86_INS_JCXZ,
#ifndef CAPSTONE_DIET
{ X86_REG_CX, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_CX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JECXZ, X86_INS_JECXZ,
#ifndef CAPSTONE_DIET
{ X86_REG_ECX, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_ECX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JE_1, X86_INS_JE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JE_2, X86_INS_JE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JE_4, X86_INS_JE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JGE_1, X86_INS_JGE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JGE_2, X86_INS_JGE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JGE_4, X86_INS_JGE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JG_1, X86_INS_JG,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JG_2, X86_INS_JG,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JG_4, X86_INS_JG,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JLE_1, X86_INS_JLE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JLE_2, X86_INS_JLE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JLE_4, X86_INS_JLE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JL_1, X86_INS_JL,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JL_2, X86_INS_JL,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JL_4, X86_INS_JL,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
@ -5650,151 +5650,151 @@
{
X86_JMP_1, X86_INS_JMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JMP_2, X86_INS_JMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JMP_4, X86_INS_JMP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 1, 0
{ 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNE_1, X86_INS_JNE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNE_2, X86_INS_JNE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNE_4, X86_INS_JNE,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNO_1, X86_INS_JNO,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNO_2, X86_INS_JNO,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNO_4, X86_INS_JNO,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNP_1, X86_INS_JNP,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNP_2, X86_INS_JNP,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNP_4, X86_INS_JNP,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNS_1, X86_INS_JNS,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNS_2, X86_INS_JNS,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JNS_4, X86_INS_JNS,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JO_1, X86_INS_JO,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JO_2, X86_INS_JO,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JO_4, X86_INS_JO,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JP_1, X86_INS_JP,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JP_2, X86_INS_JP,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JP_4, X86_INS_JP,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JRCXZ, X86_INS_JRCXZ,
#ifndef CAPSTONE_DIET
{ X86_REG_RCX, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_RCX, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JS_1, X86_INS_JS,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JS_2, X86_INS_JS,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
X86_JS_4, X86_INS_JS,
#ifndef CAPSTONE_DIET
{ X86_REG_EFLAGS, 0 }, { 0 }, { 0 }, 1, 0
{ X86_REG_EFLAGS, 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 1, 0
#endif
},
{
@ -6832,19 +6832,19 @@
{
X86_LOOP, X86_INS_LOOP,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
{ 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0
#endif
},
{
X86_LOOPE, X86_INS_LOOPE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
{ 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0
#endif
},
{
X86_LOOPNE, X86_INS_LOOPNE,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { 0 }, 0, 0
{ 0 }, { 0 }, { X86_GRP_BRANCH_RELATIVE, 0 }, 0, 0
#endif
},
{
@ -50404,13 +50404,13 @@
{
X86_XBEGIN_2, X86_INS_XBEGIN,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EAX, 0 }, { X86_GRP_RTM, 0 }, 1, 0
{ 0 }, { X86_REG_EAX, 0 }, { X86_GRP_BRANCH_RELATIVE, X86_GRP_RTM, 0 }, 1, 0
#endif
},
{
X86_XBEGIN_4, X86_INS_XBEGIN,
#ifndef CAPSTONE_DIET
{ 0 }, { X86_REG_EAX, 0 }, { X86_GRP_RTM, 0 }, 1, 0
{ 0 }, { X86_REG_EAX, 0 }, { X86_GRP_BRANCH_RELATIVE, X86_GRP_RTM, 0 }, 1, 0
#endif
},
{

1
include/capstone/arm.h
View File

@ -888,6 +888,7 @@ typedef enum arm_insn_group {
ARM_GRP_CALL, // = CS_GRP_CALL
ARM_GRP_INT = 4, // = CS_GRP_INT
ARM_GRP_PRIVILEGE = 6, // = CS_GRP_PRIVILEGE
ARM_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE
//> Architecture-specific groups
ARM_GRP_CRYPTO = 128,

1
include/capstone/arm64.h
View File

@ -1146,6 +1146,7 @@ typedef enum arm64_insn_group {
ARM64_GRP_RET,
ARM64_GRP_INT,
ARM64_GRP_PRIVILEGE = 6, // = CS_GRP_PRIVILEGE
ARM64_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE
//> Architecture-specific groups
ARM64_GRP_CRYPTO = 128,

1
include/capstone/capstone.h
View File

@ -201,6 +201,7 @@ typedef enum cs_group_type {
CS_GRP_INT, // all interrupt instructions (int+syscall)
CS_GRP_IRET, // all interrupt return instructions
CS_GRP_PRIVILEGE, // all privileged instructions
CS_GRP_BRANCH_RELATIVE, // all relative branching instructions
} cs_group_type;
/*

1
include/capstone/m68k.h
View File

@ -581,6 +581,7 @@ typedef enum m68k_group_type {
M68K_GRP_JUMP, // = CS_GRP_JUMP
M68K_GRP_RET = 3, // = CS_GRP_RET
M68K_GRP_IRET = 5, // = CS_GRP_IRET
M68K_GRP_BRANCH_RELATIVE = 7, // = CS_GRP_BRANCH_RELATIVE
M68K_GRP_ENDING,// <-- mark the end of the list of groups
} m68k_group_type;

2
include/capstone/mips.h
View File

@ -908,6 +908,8 @@ typedef enum mips_insn_group {
MIPS_GRP_IRET, // = CS_GRP_IRET
// all privileged instructions
MIPS_GRP_PRIVILEGE, // = CS_GRP_PRIVILEGE
// all relative branching instructions
MIPS_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE
//> Architecture-specific groups
MIPS_GRP_BITCOUNT = 128,

2
include/capstone/x86.h
View File

@ -1899,6 +1899,8 @@ typedef enum x86_insn_group {
X86_GRP_IRET, // = CS_GRP_IRET
// all privileged instructions
X86_GRP_PRIVILEGE, // = CS_GRP_PRIVILEGE
// all relative branching instructions
X86_GRP_BRANCH_RELATIVE, // = CS_GRP_BRANCH_RELATIVE
//> Architecture-specific groups
X86_GRP_VM = 128, // all virtualization instructions (VT-x + AMD-V)