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mips: remove the confusing mode CS_MODE_MIPSGP64

This commit is contained in:
Nguyen Anh Quynh 2015-03-07 00:48:06 +08:00
parent b8b83482b7
commit ad42f16b14
6 changed files with 9 additions and 20 deletions
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6
arch/Mips/MipsDisassembler.c
View File

@ -460,7 +460,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
}
}
if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPSGP64)) {
if ((mode & CS_MODE_MIPS32R6) && (mode & CS_MODE_MIPS64)) {
// DEBUG(dbgs() << "Trying Mips32r6_64r6 (GPR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips32r6_64r6_GP6432, instr, Insn,
Address, MRI, mode);
@ -480,7 +480,7 @@ static DecodeStatus MipsDisassembler_getInstruction(int mode, MCInst *instr,
}
}
if (mode & CS_MODE_MIPSGP64) {
if (mode & CS_MODE_MIPS64) {
// DEBUG(dbgs() << "Trying Mips64 (GPR64) table (32-bit opcodes):\n");
Result = decodeInstruction(DecoderTableMips6432, instr, Insn,
Address, MRI, mode);
@ -886,7 +886,7 @@ static DecodeStatus DecodePtrRegisterClass(MCInst *Inst,
unsigned RegNo, uint64_t Address, MCRegisterInfo *Decoder)
{
// if (static_cast<const MipsDisassembler *>(Decoder)->isGP64())
if (Inst->csh->mode & CS_MODE_MIPSGP64) // FIXME
if (Inst->csh->mode & CS_MODE_MIPS64)
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);

1
bindings/java/capstone/Capstone.java
View File

@ -300,7 +300,6 @@ public class Capstone {
public static final int CS_MODE_MICRO = 1 << 4; // MicroMips mode (Mips arch)
public static final int CS_MODE_MIPS3 = 1 << 5; // Mips III ISA
public static final int CS_MODE_MIPS32R6 = 1 << 6; // Mips32r6 ISA
public static final int CS_MODE_MIPSGP64 = 1 << 7; // General Purpose Registers are 64-bit wide (MIPS arch)
public static final int CS_MODE_BIG_ENDIAN = 1 << 31; // big-endian mode
public static final int CS_MODE_V9 = 1 << 4; // SparcV9 mode (Sparc arch)
public static final int CS_MODE_MIPS32 = CS_MODE_32; // Mips32 ISA

1
bindings/ocaml/capstone.ml
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@ -35,7 +35,6 @@ type mode =
| CS_MODE_MICRO (* MicroMips mode (MIPS architecture) *)
| CS_MODE_MIPS3 (* Mips3 mode (MIPS architecture) *)
| CS_MODE_MIPS32R6 (* Mips32-R6 mode (MIPS architecture) *)
| CS_MODE_MIPSGP64 (* MipsGP64 mode (MIPS architecture) *)
| CS_MODE_V9 (* SparcV9 mode (Sparc architecture) *)
| CS_MODE_BIG_ENDIAN (* big-endian mode *)
| CS_MODE_MIPS32 (* Mips32 mode (for Mips) *)

18
bindings/ocaml/ocaml.c
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@ -699,18 +699,15 @@ CAMLprim value ocaml_cs_disasm(value _arch, value _mode, value _code, value _add
mode |= CS_MODE_MIPS32R6;
break;
case 11:
mode |= CS_MODE_MIPSGP64;
break;
case 12:
mode |= CS_MODE_V9;
break;
case 13:
case 12:
mode |= CS_MODE_BIG_ENDIAN;
break;
case 14:
case 13:
mode |= CS_MODE_MIPS32;
break;
case 15:
case 14:
mode |= CS_MODE_MIPS64;
break;
default:
@ -830,18 +827,15 @@ CAMLprim value ocaml_open(value _arch, value _mode)
mode |= CS_MODE_MIPS32R6;
break;
case 11:
mode |= CS_MODE_MIPSGP64;
break;
case 12:
mode |= CS_MODE_V9;
break;
case 13:
case 12:
mode |= CS_MODE_BIG_ENDIAN;
break;
case 14:
case 13:
mode |= CS_MODE_MIPS32;
break;
case 15:
case 14:
mode |= CS_MODE_MIPS64;
break;
default:

2
bindings/python/capstone/__init__.py
View File

@ -40,7 +40,6 @@ __all__ = [
'CS_MODE_MICRO',
'CS_MODE_MIPS3',
'CS_MODE_MIPS32R6',
'CS_MODE_MIPSGP64',
'CS_MODE_V8',
'CS_MODE_V9',
'CS_MODE_MIPS32',
@ -122,7 +121,6 @@ CS_MODE_V8 = (1 << 6) # ARMv8 A32 encodings for ARM
CS_MODE_MICRO = (1 << 4) # MicroMips mode (MIPS architecture)
CS_MODE_MIPS3 = (1 << 5) # Mips III ISA
CS_MODE_MIPS32R6 = (1 << 6) # Mips32r6 ISA
CS_MODE_MIPSGP64 = (1 << 7) # General Purpose Registers are 64-bit wide (MIPS arch)
CS_MODE_V9 = (1 << 4) # Sparc V9 mode (for Sparc)
CS_MODE_BIG_ENDIAN = (1 << 31) # big-endian mode
CS_MODE_MIPS32 = CS_MODE_32 # Mips32 ISA

1
include/capstone/capstone.h
View File

@ -88,7 +88,6 @@ typedef enum cs_mode {
CS_MODE_MICRO = 1 << 4, // MicroMips mode (MIPS)
CS_MODE_MIPS3 = 1 << 5, // Mips III ISA
CS_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA
CS_MODE_MIPSGP64 = 1 << 7, // General Purpose Registers are 64-bit wide (MIPS)
CS_MODE_V9 = 1 << 4, // SparcV9 mode (Sparc)
CS_MODE_QPX = 1 << 4, // Quad Processing eXtensions mode (PPC)
CS_MODE_BIG_ENDIAN = 1 << 31, // big-endian mode