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fix build

This commit is contained in:
billow 2023-03-23 23:50:16 +08:00
parent 30432c862d
commit b1f7cfeb84
9 changed files with 9054 additions and 4783 deletions
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117
arch/TriCore/TriCoreDisassembler.c
View File

@ -120,6 +120,30 @@ static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
uint64_t Address, void *Decoder);
static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder);
#include "TriCoreGenDisassemblerTables.inc"
#define GET_REGINFO_ENUM
@ -835,6 +859,99 @@ static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
return MCDisassembler_Success;
}
static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn, uint64_t Address, void *Decoder){
// TODO: DecodeBRNInstruction
return MCDisassembler_Fail;
}
#define GET_SUBTARGETINFO_ENUM
#include "TriCoreGenInstrInfo.inc"
bool TriCore_getInstruction(csh ud, const uint8_t *code, size_t code_len, MCInst *MI,

3483
arch/TriCore/TriCoreGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

3120
arch/TriCore/TriCoreGenDisassemblerTables.inc
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File diff suppressed because it is too large Load Diff

3075
arch/TriCore/TriCoreGenInstrInfo.inc
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File diff suppressed because it is too large Load Diff

118
arch/TriCore/TriCoreInstPrinter.c
View File

@ -30,11 +30,12 @@
#include "TriCoreMapping.h"
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
static void printInstruction(MCInst *, uint64_t, SStream *);
static void printOperand(MCInst *MI, int OpNum, SStream *O);
void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
{
void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci) {
/*
if (((cs_struct *)ud)->detail != CS_OPT_ON)
return;
@ -42,13 +43,14 @@ void TriCore_post_printer(csh ud, cs_insn *insn, char *insn_asm, MCInst *mci)
}
#define GET_INSTRINFO_ENUM
#include "TriCoreGenInstrInfo.inc"
#define GET_REGINFO_ENUM
#include "TriCoreGenRegisterInfo.inc"
static void printOperand(MCInst *MI, int OpNum, SStream *O)
{
static void printOperand(MCInst *MI, int OpNum, SStream *O) {
MCOperand *Op;
if (OpNum >= MI->size)
return;
@ -61,7 +63,8 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O)
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t)TriCore_map_register(reg);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
reg);
MI->flat_insn->detail->tricore.op_count++;
}
} else if (MCOperand_isImm(Op)) {
@ -88,56 +91,63 @@ static void printOperand(MCInst *MI, int OpNum, SStream *O)
}
static void printPairAddrRegsOperand(MCInst *MI, unsigned OpNum, SStream *O,
MCRegisterInfo *MRI)
{
MCRegisterInfo *MRI) {
unsigned Reg = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
SStream_concat0(O, "[");
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_even)));
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t)TriCore_map_register(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_even));
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_even));
MI->flat_insn->detail->tricore.op_count++;
}
SStream_concat0(O, "/");
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_odd)));
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t)TriCore_map_register(MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_odd));
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
MCRegisterInfo_getSubReg(MRI, Reg, TriCore_subreg_odd));
MI->flat_insn->detail->tricore.op_count++;
}
SStream_concat0(O, "]");
}
static void printSExtImm(MCInst *MI, int OpNum, SStream *O)
{
static void printSExtImm(MCInst *MI, int OpNum, SStream *O) {
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
int64_t imm = MCOperand_getImm(MO);
if (imm >= 0) {
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", (unsigned short int)imm);
SStream_concat(O, "0x%x", (unsigned short int) imm);
else
SStream_concat(O, "%u", (unsigned short int)imm);
SStream_concat(O, "%u", (unsigned short int) imm);
} else {
if (imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%x", (short int)-imm);
SStream_concat(O, "-0x%x", (short int) -imm);
else
SStream_concat(O, "-%u", (short int)-imm);
SStream_concat(O, "-%u", (short int) -imm);
}
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_IMM;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].imm = (unsigned short int)imm;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].imm = (unsigned short int) imm;
MI->flat_insn->detail->tricore.op_count++;
}
} else
printOperand(MI, OpNum, O);
}
static void printZExtImm(MCInst *MI, int OpNum, SStream *O)
{
static void printSExtImm_16(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
static void printSExtImm_10(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
static void printSExtImm_9(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
static void printSExtImm_4(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
static void printZExtImm(MCInst *MI, int OpNum, SStream *O) {
MCOperand *MO = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(MO)) {
unsigned imm = (unsigned)MCOperand_getImm(MO);
unsigned imm = (unsigned) MCOperand_getImm(MO);
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
@ -151,16 +161,22 @@ static void printZExtImm(MCInst *MI, int OpNum, SStream *O)
printOperand(MI, OpNum, O);
}
static void printZExtImm_8(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
static void printZExtImm_4(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
static void printZExtImm_2(MCInst *MI, int OpNum, SStream *O) { /*TODO: TriCore*/}
static void printPCRelImmOperand(MCInst *MI, int OpNum, SStream *O) {
MCOperand *Op = MCInst_getOperand(MI, OpNum);
if (MCOperand_isImm(Op)) {
unsigned imm = (unsigned)MCOperand_getImm(Op);
unsigned imm = (unsigned) MCOperand_getImm(Op);
if (imm > HEX_THRESHOLD)
SStream_concat(O, "0x%x", imm);
else
SStream_concat(O, "%u", imm);
}
else
} else
printOperand(MI, OpNum, O);
}
@ -169,7 +185,7 @@ static void printPCRelImmOperand(MCInst *MI, int OpNum, SStream *O) {
static void printAddrBO(MCInst *MI, int OpNum, SStream *O) {
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
SStream_concat(O, "[");
SStream_concat(O, "%%%s", getRegisterName(Base));
@ -182,7 +198,8 @@ static void printAddrBO(MCInst *MI, int OpNum, SStream *O) {
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t)TriCore_map_register(Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
MI->flat_insn->detail->tricore.op_count++;
}
@ -193,7 +210,7 @@ static void printAddrBO(MCInst *MI, int OpNum, SStream *O) {
static void printAddrPreIncBO(MCInst *MI, int OpNum, SStream *O) {
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
SStream_concat(O, "[+");
SStream_concat(O, "%%%s", getRegisterName(Base));
@ -206,7 +223,8 @@ static void printAddrPreIncBO(MCInst *MI, int OpNum, SStream *O) {
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t)TriCore_map_register(Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
MI->flat_insn->detail->tricore.op_count++;
}
@ -217,7 +235,7 @@ static void printAddrPreIncBO(MCInst *MI, int OpNum, SStream *O) {
static void printAddrPostIncBO(MCInst *MI, int OpNum, SStream *O) {
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
SStream_concat(O, "[");
SStream_concat(O, "%%%s", getRegisterName(Base));
@ -230,7 +248,8 @@ static void printAddrPostIncBO(MCInst *MI, int OpNum, SStream *O) {
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t)TriCore_map_register(Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
MI->flat_insn->detail->tricore.op_count++;
}
@ -239,23 +258,24 @@ static void printAddrPostIncBO(MCInst *MI, int OpNum, SStream *O) {
// Print a 'circbo' operand which is an addressing mode
// Circular Base+Offset
static void printAddrCircBO(MCInst *MI, unsigned OpNum, SStream *O,
MCRegisterInfo *MRI)
{
MCRegisterInfo *MRI) {
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
uint64_t Disp = (uint64_t)MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
uint64_t Disp = (uint64_t) MCOperand_getImm(MCInst_getOperand(MI, OpNum + 1));
SStream_concat0(O, "[");
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even)));
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t)TriCore_map_register(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
MI->flat_insn->detail->tricore.op_count++;
}
SStream_concat0(O, "/");
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd)));
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t)TriCore_map_register(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
MI->flat_insn->detail->tricore.op_count++;
}
SStream_concat0(O, "+c] ");
@ -267,7 +287,8 @@ static void printAddrCircBO(MCInst *MI, unsigned OpNum, SStream *O,
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_MEM;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t)TriCore_map_register(Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.base = (uint8_t) TriCore_map_register(
Base);
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].mem.disp = Disp;
MI->flat_insn->detail->tricore.op_count++;
}
@ -276,8 +297,7 @@ static void printAddrCircBO(MCInst *MI, unsigned OpNum, SStream *O,
// Print a 'bitrevbo' operand which is an addressing mode
// Bit-Reverse Base+Offset
static void printAddrBitRevBO(MCInst *MI, unsigned OpNum, SStream *O,
MCRegisterInfo *MRI)
{
MCRegisterInfo *MRI) {
unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, OpNum));
@ -285,25 +305,37 @@ static void printAddrBitRevBO(MCInst *MI, unsigned OpNum, SStream *O,
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even)));
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t)TriCore_map_register(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_even));
MI->flat_insn->detail->tricore.op_count++;
}
SStream_concat0(O, "/");
SStream_concat(O, "%%%s", getRegisterName(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd)));
if (MI->csh->detail) {
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].type = TRICORE_OP_REG;
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t)TriCore_map_register(MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
MI->flat_insn->detail->tricore.operands[MI->flat_insn->detail->tricore.op_count].reg = (uint8_t) TriCore_map_register(
MCRegisterInfo_getSubReg(MRI, Base, TriCore_subreg_odd));
MI->flat_insn->detail->tricore.op_count++;
}
SStream_concat0(O, "+r]");
}
/// Returned by getMnemonic() of the AsmPrinters.
typedef struct {
const char *first; // Menmonic
uint64_t second; // Bits
} MnemonicBitsInfo;
void set_mem_access(MCInst *MI, unsigned int access) {
// TODO: TriCore
}
#define PRINT_ALIAS_INSTR
#include "TriCoreGenAsmWriter.inc"
void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *)Info;
void TriCore_printInst(MCInst *MI, SStream *O, void *Info) {
MCRegisterInfo *MRI = (MCRegisterInfo *) Info;
unsigned Opcode = MCInst_getOpcode(MI), i;
@ -420,7 +452,7 @@ void TriCore_printInst(MCInst *MI, SStream *O, void *Info)
// }
// }
// }
printInstruction(MI, O, Info);
printInstruction(MI, Info, O);
}
#endif

3228
arch/TriCore/gen/TriCoreGenCSMappingInsn.inc
View File

File diff suppressed because it is too large Load Diff

21
arch/TriCore/gen/TriCoreGenCSMappingInsnName.inc
View File

@ -5,6 +5,7 @@
/* Auto generated file. Do not edit. */
/* Code generator: https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
"xor.t", // TriCore_INS_XOR.T
"absdifs.h", // TriCore_INS_ABSDIFS.H
"absdifs", // TriCore_INS_ABSDIFS
"absdif.b", // TriCore_INS_ABSDIF.B
@ -28,6 +29,7 @@
"addx", // TriCore_INS_ADDX
"add.a", // TriCore_INS_ADD.A
"add.b", // TriCore_INS_ADD.B
"add.f", // TriCore_INS_ADD.F
"add.h", // TriCore_INS_ADD.H
"add", // TriCore_INS_ADD
"andn.t", // TriCore_INS_ANDN.T
@ -67,6 +69,7 @@
"cmovn", // TriCore_INS_CMOVN
"cmov", // TriCore_INS_CMOV
"CMPSWAP.W", // TriCore_INS_CMPSWAP.W
"cmp.f", // TriCore_INS_CMP.F
"crc32b.w", // TriCore_INS_CRC32B.W
"crc32l.w", // TriCore_INS_CRC32L.W
"crc32.b", // TriCore_INS_CRC32.B
@ -75,6 +78,7 @@
"debug", // TriCore_INS_DEBUG
"dextr", // TriCore_INS_DEXTR
"disable", // TriCore_INS_DISABLE
"div.f", // TriCore_INS_DIV.F
"div.u", // TriCore_INS_DIV.U
"div", // TriCore_INS_DIV
"dsync", // TriCore_INS_DSYNC
@ -102,14 +106,23 @@
"fcalli", // TriCore_INS_FCALLI
"fcall", // TriCore_INS_FCALL
"fret", // TriCore_INS_FRET
"ftohp", // TriCore_INS_FTOHP
"ftoiz", // TriCore_INS_FTOIZ
"ftoi", // TriCore_INS_FTOI
"ftoq31z", // TriCore_INS_FTOQ31Z
"ftoq31", // TriCore_INS_FTOQ31
"ftouz", // TriCore_INS_FTOUZ
"ftou", // TriCore_INS_FTOU
"ge.a", // TriCore_INS_GE.A
"ge.u", // TriCore_INS_GE.U
"ge", // TriCore_INS_GE
"hptof", // TriCore_INS_HPTOF
"imask", // TriCore_INS_IMASK
"insert", // TriCore_INS_INSERT
"insn.t", // TriCore_INS_INSN.T
"ins.t", // TriCore_INS_INS.T
"isync", // TriCore_INS_ISYNC
"itof", // TriCore_INS_ITOF
"ixmax.u", // TriCore_INS_IXMAX.U
"ixmax", // TriCore_INS_IXMAX
"ixmin.u", // TriCore_INS_IXMIN.U
@ -181,6 +194,7 @@
"madds.q", // TriCore_INS_MADDS.Q
"madds.u", // TriCore_INS_MADDS.U
"madds", // TriCore_INS_MADDS
"madd.f", // TriCore_INS_MADD.F
"madd.h", // TriCore_INS_MADD.H
"madd.q", // TriCore_INS_MADD.Q
"madd.u", // TriCore_INS_MADD.U
@ -220,6 +234,7 @@
"msubs.h", // TriCore_INS_MSUBS.H
"msubs.q", // TriCore_INS_MSUBS.Q
"msubs", // TriCore_INS_MSUBS
"msub.f", // TriCore_INS_MSUB.F
"msub.h", // TriCore_INS_MSUB.H
"msub.q", // TriCore_INS_MSUB.Q
"msub", // TriCore_INS_MSUB
@ -258,6 +273,8 @@
"pack", // TriCore_INS_PACK
"parity", // TriCore_INS_PARITY
"popcnt.w", // TriCore_INS_POPCNT.W
"q31tof", // TriCore_INS_Q31TOF
"qseed.f", // TriCore_INS_QSEED.F
"restore", // TriCore_INS_RESTORE
"ret", // TriCore_INS_RET
"rfe", // TriCore_INS_RFE
@ -309,6 +326,7 @@
"subx", // TriCore_INS_SUBX
"sub.a", // TriCore_INS_SUB.A
"sub.b", // TriCore_INS_SUB.B
"sub.f", // TriCore_INS_SUB.F
"sub.h", // TriCore_INS_SUB.H
"sub", // TriCore_INS_SUB
"svlcx", // TriCore_INS_SVLCX
@ -318,6 +336,8 @@
"trapsv", // TriCore_INS_TRAPSV
"trapv", // TriCore_INS_TRAPV
"unpack", // TriCore_INS_UNPACK
"updfl", // TriCore_INS_UPDFL
"utof", // TriCore_INS_UTOF
"wait", // TriCore_INS_WAIT
"xnor.t", // TriCore_INS_XNOR.T
"xnor", // TriCore_INS_XNOR
@ -327,5 +347,4 @@
"xor.lt.u", // TriCore_INS_XOR.LT.U
"xor.lt", // TriCore_INS_XOR.LT
"xor.ne", // TriCore_INS_XOR.NE
"xor.t", // TriCore_INS_XOR.T
"xor", // TriCore_INS_XOR

350
include/capstone/inc/TriCoreGenCSInsnEnum.inc Normal file
View File

@ -0,0 +1,350 @@
/* Capstone Disassembly Engine, https://www_capstone-engine_org */
/* By Nguyen Anh Quynh <aquynh@gmail_com>, 2013-2019 */
/* By Rot127 <unisono@quyllur_org>, 2023 */
/* Auto generated file_ Do not edit_ */
/* Code generator: https://github_com/capstone-engine/capstone/tree/next/suite/auto-sync */
TriCore_INS_XOR_T,
TriCore_INS_ABSDIFS_H,
TriCore_INS_ABSDIFS,
TriCore_INS_ABSDIF_B,
TriCore_INS_ABSDIF_H,
TriCore_INS_ABSDIF,
TriCore_INS_ABSS_H,
TriCore_INS_ABSS,
TriCore_INS_ABS_B,
TriCore_INS_ABS_H,
TriCore_INS_ABS,
TriCore_INS_ADDC,
TriCore_INS_ADDIH_A,
TriCore_INS_ADDIH,
TriCore_INS_ADDI,
TriCore_INS_ADDSC_AT,
TriCore_INS_ADDSC_A,
TriCore_INS_ADDS_H,
TriCore_INS_ADDS_HU,
TriCore_INS_ADDS_U,
TriCore_INS_ADDS,
TriCore_INS_ADDX,
TriCore_INS_ADD_A,
TriCore_INS_ADD_B,
TriCore_INS_ADD_F,
TriCore_INS_ADD_H,
TriCore_INS_ADD,
TriCore_INS_ANDN_T,
TriCore_INS_ANDN,
TriCore_INS_AND_ANDN_T,
TriCore_INS_AND_AND_T,
TriCore_INS_AND_EQ,
TriCore_INS_AND_GE_U,
TriCore_INS_AND_GE,
TriCore_INS_AND_LT_U,
TriCore_INS_AND_LT,
TriCore_INS_AND_NE,
TriCore_INS_AND_NOR_T,
TriCore_INS_AND_OR_T,
TriCore_INS_AND_T,
TriCore_INS_AND,
TriCore_INS_BISR,
TriCore_INS_BMERGE,
TriCore_INS_BSPLIT,
TriCore_INS_CACHEI_I,
TriCore_INS_CACHEI_WI,
TriCore_INS_CACHEI_W,
TriCore_INS_CACHE_I,
TriCore_INS_CACHE_WI,
TriCore_INS_CACHE_W,
TriCore_INS_CADDN,
TriCore_INS_CADD,
TriCore_INS_CALLA,
TriCore_INS_CALLI,
TriCore_INS_CALL,
TriCore_INS_CLO_H,
TriCore_INS_CLO,
TriCore_INS_CLS_H,
TriCore_INS_CLS,
TriCore_INS_CLZ_H,
TriCore_INS_CLZ,
TriCore_INS_CMOVN,
TriCore_INS_CMOV,
TriCore_INS_CMPSWAP_W,
TriCore_INS_CMP_F,
TriCore_INS_CRC32B_W,
TriCore_INS_CRC32L_W,
TriCore_INS_CRC32_B,
TriCore_INS_CRCN,
TriCore_INS_CSUB,
TriCore_INS_DEBUG,
TriCore_INS_DEXTR,
TriCore_INS_DISABLE,
TriCore_INS_DIV_F,
TriCore_INS_DIV_U,
TriCore_INS_DIV,
TriCore_INS_DSYNC,
TriCore_INS_DVADJ,
TriCore_INS_DVINIT_BU,
TriCore_INS_DVINIT_B,
TriCore_INS_DVINIT_HU,
TriCore_INS_DVINIT_H,
TriCore_INS_DVINIT_U,
TriCore_INS_DVINIT,
TriCore_INS_DVSTEP_U,
TriCore_INS_DVSTEP,
TriCore_INS_ENABLE,
TriCore_INS_EQANY_B,
TriCore_INS_EQANY_H,
TriCore_INS_EQZ_A,
TriCore_INS_EQ_A,
TriCore_INS_EQ_B,
TriCore_INS_EQ_H,
TriCore_INS_EQ_W,
TriCore_INS_EQ,
TriCore_INS_EXTR_U,
TriCore_INS_EXTR,
TriCore_INS_FCALLA,
TriCore_INS_FCALLI,
TriCore_INS_FCALL,
TriCore_INS_FRET,
TriCore_INS_FTOHP,
TriCore_INS_FTOIZ,
TriCore_INS_FTOI,
TriCore_INS_FTOQ31Z,
TriCore_INS_FTOQ31,
TriCore_INS_FTOUZ,
TriCore_INS_FTOU,
TriCore_INS_GE_A,
TriCore_INS_GE_U,
TriCore_INS_GE,
TriCore_INS_HPTOF,
TriCore_INS_IMASK,
TriCore_INS_INSERT,
TriCore_INS_INSN_T,
TriCore_INS_INS_T,
TriCore_INS_ISYNC,
TriCore_INS_ITOF,
TriCore_INS_IXMAX_U,
TriCore_INS_IXMAX,
TriCore_INS_IXMIN_U,
TriCore_INS_IXMIN,
TriCore_INS_JA,
TriCore_INS_JEQ_A,
TriCore_INS_JEQ,
TriCore_INS_JGEZ,
TriCore_INS_JGE_U,
TriCore_INS_JGE,
TriCore_INS_JGTZ,
TriCore_INS_JI,
TriCore_INS_JLA,
TriCore_INS_JLEZ,
TriCore_INS_JLI,
TriCore_INS_JLTZ,
TriCore_INS_JLT_U,
TriCore_INS_JLT,
TriCore_INS_JL,
TriCore_INS_JNED,
TriCore_INS_JNEI,
TriCore_INS_JNE_A,
TriCore_INS_JNE,
TriCore_INS_JNZ_A,
TriCore_INS_JNZ_T,
TriCore_INS_JNZ,
TriCore_INS_JZ_A,
TriCore_INS_JZ_T,
TriCore_INS_JZ,
TriCore_INS_J,
TriCore_INS_LDLCX,
TriCore_INS_LDMST,
TriCore_INS_LDUCX,
TriCore_INS_LD_A,
TriCore_INS_LD_BU,
TriCore_INS_LD_B,
TriCore_INS_LD_DA,
TriCore_INS_LD_D,
TriCore_INS_LD_HU,
TriCore_INS_LD_H,
TriCore_INS_LD_Q,
TriCore_INS_LD_W,
TriCore_INS_LEA,
TriCore_INS_LHA,
TriCore_INS_LOOPU,
TriCore_INS_LOOP,
TriCore_INS_LT_A,
TriCore_INS_LT_B,
TriCore_INS_LT_BU,
TriCore_INS_LT_H,
TriCore_INS_LT_HU,
TriCore_INS_LT_U,
TriCore_INS_LT_W,
TriCore_INS_LT_WU,
TriCore_INS_LT,
TriCore_INS_MADDMS_H,
TriCore_INS_MADDM_H,
TriCore_INS_MADDRS_H,
TriCore_INS_MADDRS_Q,
TriCore_INS_MADDR_H,
TriCore_INS_MADDR_Q,
TriCore_INS_MADDSUMS_H,
TriCore_INS_MADDSUM_H,
TriCore_INS_MADDSURS_H,
TriCore_INS_MADDSUR_H,
TriCore_INS_MADDSUS_H,
TriCore_INS_MADDSU_H,
TriCore_INS_MADDS_H,
TriCore_INS_MADDS_Q,
TriCore_INS_MADDS_U,
TriCore_INS_MADDS,
TriCore_INS_MADD_F,
TriCore_INS_MADD_H,
TriCore_INS_MADD_Q,
TriCore_INS_MADD_U,
TriCore_INS_MADD,
TriCore_INS_MAX_B,
TriCore_INS_MAX_BU,
TriCore_INS_MAX_H,
TriCore_INS_MAX_HU,
TriCore_INS_MAX_U,
TriCore_INS_MAX,
TriCore_INS_MFCR,
TriCore_INS_MIN_B,
TriCore_INS_MIN_BU,
TriCore_INS_MIN_H,
TriCore_INS_MIN_HU,
TriCore_INS_MIN_U,
TriCore_INS_MIN,
TriCore_INS_MOVH_A,
TriCore_INS_MOV_AA,
TriCore_INS_MOV_A,
TriCore_INS_MOV_D,
TriCore_INS_MOV_H,
TriCore_INS_MOV_U,
TriCore_INS_MOV,
TriCore_INS_MSUBADMS_H,
TriCore_INS_MSUBADM_H,
TriCore_INS_MSUBADRS_H,
TriCore_INS_MSUBADR_H,
TriCore_INS_MSUBADS_H,
TriCore_INS_MSUBAD_H,
TriCore_INS_MSUBMS_H,
TriCore_INS_MSUBM_H,
TriCore_INS_MSUBRS_H,
TriCore_INS_MSUBRS_Q,
TriCore_INS_MSUBR_H,
TriCore_INS_MSUBR_Q,
TriCore_INS_MSUBS_H,
TriCore_INS_MSUBS_Q,
TriCore_INS_MSUBS,
TriCore_INS_MSUB_F,
TriCore_INS_MSUB_H,
TriCore_INS_MSUB_Q,
TriCore_INS_MSUB,
TriCore_INS_MULM_H,
TriCore_INS_MULR_H,
TriCore_INS_MULR_Q,
TriCore_INS_MULS_U,
TriCore_INS_MULS,
TriCore_INS_MUL_H,
TriCore_INS_MUL_Q,
TriCore_INS_MUL_U,
TriCore_INS_MUL,
TriCore_INS_NAND_T,
TriCore_INS_NAND,
TriCore_INS_NEZ_A,
TriCore_INS_NE_A,
TriCore_INS_NE,
TriCore_INS_NOP,
TriCore_INS_NOR_T,
TriCore_INS_NOR,
TriCore_INS_NOT,
TriCore_INS_ORN_T,
TriCore_INS_ORN,
TriCore_INS_OR_ANDN_T,
TriCore_INS_OR_AND_T,
TriCore_INS_OR_EQ,
TriCore_INS_OR_GE_U,
TriCore_INS_OR_GE,
TriCore_INS_OR_LT_U,
TriCore_INS_OR_LT,
TriCore_INS_OR_NE,
TriCore_INS_OR_NOR_T,
TriCore_INS_OR_OR_T,
TriCore_INS_OR_T,
TriCore_INS_OR,
TriCore_INS_PACK,
TriCore_INS_PARITY,
TriCore_INS_POPCNT_W,
TriCore_INS_Q31TOF,
TriCore_INS_QSEED_F,
TriCore_INS_RESTORE,
TriCore_INS_RET,
TriCore_INS_RFE,
TriCore_INS_RFM,
TriCore_INS_RELCK,
TriCore_INS_RSUBS_U,
TriCore_INS_RSUBS,
TriCore_INS_RSUB,
TriCore_INS_SAT_BU,
TriCore_INS_SAT_B,
TriCore_INS_SAT_HU,
TriCore_INS_SAT_H,
TriCore_INS_SELN,
TriCore_INS_SEL,
TriCore_INS_SHAS,
TriCore_INS_SHA_H,
TriCore_INS_SHA,
TriCore_INS_SHUFFLE,
TriCore_INS_SH_ANDN_T,
TriCore_INS_SH_AND_T,
TriCore_INS_SH_EQ,
TriCore_INS_SH_GE_U,
TriCore_INS_SH_GE,
TriCore_INS_SH_H,
TriCore_INS_SH_LT_U,
TriCore_INS_SH_LT,
TriCore_INS_SH_NAND_T,
TriCore_INS_SH_NOR_T,
TriCore_INS_SH_ORN_T,
TriCore_INS_SH_OR_T,
TriCore_INS_SH_XNOR_T,
TriCore_INS_SH_XOR_T,
TriCore_INS_SH,
TriCore_INS_STLCX,
TriCore_INS_STUCX,
TriCore_INS_ST_A,
TriCore_INS_ST_B,
TriCore_INS_ST_DA,
TriCore_INS_ST_D,
TriCore_INS_ST_H,
TriCore_INS_ST_Q,
TriCore_INS_ST_T,
TriCore_INS_ST_W,
TriCore_INS_SUBC,
TriCore_INS_SUBS_HU,
TriCore_INS_SUBS_H,
TriCore_INS_SUBS_U,
TriCore_INS_SUBS,
TriCore_INS_SUBX,
TriCore_INS_SUB_A,
TriCore_INS_SUB_B,
TriCore_INS_SUB_F,
TriCore_INS_SUB_H,
TriCore_INS_SUB,
TriCore_INS_SVLCX,
TriCore_INS_SWAPMSK_W,
TriCore_INS_SWAP_W,
TriCore_INS_SYSCALL,
TriCore_INS_TRAPSV,
TriCore_INS_TRAPV,
TriCore_INS_UNPACK,
TriCore_INS_UPDFL,
TriCore_INS_UTOF,
TriCore_INS_WAIT,
TriCore_INS_XNOR_T,
TriCore_INS_XNOR,
TriCore_INS_XOR_EQ,
TriCore_INS_XOR_GE_U,
TriCore_INS_XOR_GE,
TriCore_INS_XOR_LT_U,
TriCore_INS_XOR_LT,
TriCore_INS_XOR_NE,
TriCore_INS_XOR,

325
include/capstone/tricore.h
View File

@ -122,330 +122,7 @@ typedef enum tricore_reg {
typedef enum tricore_insn {
TriCore_INS_INVALID = 0,
TriCore_INS_ABSDIFS_H,
TriCore_INS_ABSDIFS,
TriCore_INS_ABSDIF_B,
TriCore_INS_ABSDIF_H,
TriCore_INS_ABSDIF,
TriCore_INS_ABSS_H,
TriCore_INS_ABSS,
TriCore_INS_ABS_B,
TriCore_INS_ABS_H,
TriCore_INS_ABS,
TriCore_INS_ADDC,
TriCore_INS_ADDIH_A,
TriCore_INS_ADDIH,
TriCore_INS_ADDI,
TriCore_INS_ADDSC_AT,
TriCore_INS_ADDSC_A,
TriCore_INS_ADDS_H,
TriCore_INS_ADDS_HU,
TriCore_INS_ADDS_U,
TriCore_INS_ADDS,
TriCore_INS_ADDX,
TriCore_INS_ADD_A,
TriCore_INS_ADD_B,
TriCore_INS_ADD_H,
TriCore_INS_ADD,
TriCore_INS_ANDN_T,
TriCore_INS_ANDN,
TriCore_INS_AND_ANDN_T,
TriCore_INS_AND_AND_T,
TriCore_INS_AND_EQ,
TriCore_INS_AND_GE_U,
TriCore_INS_AND_GE,
TriCore_INS_AND_LT_U,
TriCore_INS_AND_LT,
TriCore_INS_AND_NE,
TriCore_INS_AND_NOR_T,
TriCore_INS_AND_OR_T,
TriCore_INS_AND_T,
TriCore_INS_AND,
TriCore_INS_BISR,
TriCore_INS_BMERGE,
TriCore_INS_BSPLIT,
TriCore_INS_CACHEI_I,
TriCore_INS_CACHEI_WI,
TriCore_INS_CACHEI_W,
TriCore_INS_CACHE_I,
TriCore_INS_CACHE_WI,
TriCore_INS_CACHE_W,
TriCore_INS_CADDN,
TriCore_INS_CADD,
TriCore_INS_CALLA,
TriCore_INS_CALLI,
TriCore_INS_CALL,
TriCore_INS_CLO_H,
TriCore_INS_CLO,
TriCore_INS_CLS_H,
TriCore_INS_CLS,
TriCore_INS_CLZ_H,
TriCore_INS_CLZ,
TriCore_INS_CMOVN,
TriCore_INS_CMOV,
TriCore_INS_CMPSWAP_W,
TriCore_INS_CRC32B_W,
TriCore_INS_CRC32L_W,
TriCore_INS_CRC32_B,
TriCore_INS_CRCN,
TriCore_INS_CSUB,
TriCore_INS_DEBUG,
TriCore_INS_DEXTR,
TriCore_INS_DISABLE,
TriCore_INS_DIV_U,
TriCore_INS_DIV,
TriCore_INS_DSYNC,
TriCore_INS_DVADJ,
TriCore_INS_DVINIT_BU,
TriCore_INS_DVINIT_B,
TriCore_INS_DVINIT_HU,
TriCore_INS_DVINIT_H,
TriCore_INS_DVINIT_U,
TriCore_INS_DVINIT,
TriCore_INS_DVSTEP_U,
TriCore_INS_DVSTEP,
TriCore_INS_ENABLE,
TriCore_INS_EQANY_B,
TriCore_INS_EQANY_H,
TriCore_INS_EQZ_A,
TriCore_INS_EQ_A,
TriCore_INS_EQ_B,
TriCore_INS_EQ_H,
TriCore_INS_EQ_W,
TriCore_INS_EQ,
TriCore_INS_EXTR_U,
TriCore_INS_EXTR,
TriCore_INS_FCALLA,
TriCore_INS_FCALLI,
TriCore_INS_FCALL,
TriCore_INS_FRET,
TriCore_INS_GE_A,
TriCore_INS_GE_U,
TriCore_INS_GE,
TriCore_INS_IMASK,
TriCore_INS_INSERT,
TriCore_INS_INSN_T,
TriCore_INS_INS_T,
TriCore_INS_ISYNC,
TriCore_INS_IXMAX_U,
TriCore_INS_IXMAX,
TriCore_INS_IXMIN_U,
TriCore_INS_IXMIN,
TriCore_INS_JA,
TriCore_INS_JEQ_A,
TriCore_INS_JEQ,
TriCore_INS_JGEZ,
TriCore_INS_JGE_U,
TriCore_INS_JGE,
TriCore_INS_JGTZ,
TriCore_INS_JI,
TriCore_INS_JLA,
TriCore_INS_JLEZ,
TriCore_INS_JLI,
TriCore_INS_JLTZ,
TriCore_INS_JLT_U,
TriCore_INS_JLT,
TriCore_INS_JL,
TriCore_INS_JNED,
TriCore_INS_JNEI,
TriCore_INS_JNE_A,
TriCore_INS_JNE,
TriCore_INS_JNZ_A,
TriCore_INS_JNZ_T,
TriCore_INS_JNZ,
TriCore_INS_JZ_A,
TriCore_INS_JZ_T,
TriCore_INS_JZ,
TriCore_INS_J,
TriCore_INS_LDLCX,
TriCore_INS_LDMST,
TriCore_INS_LDUCX,
TriCore_INS_LD_A,
TriCore_INS_LD_BU,
TriCore_INS_LD_B,
TriCore_INS_LD_DA,
TriCore_INS_LD_D,
TriCore_INS_LD_HU,
TriCore_INS_LD_H,
TriCore_INS_LD_Q,
TriCore_INS_LD_W,
TriCore_INS_LEA,
TriCore_INS_LHA,
TriCore_INS_LOOPU,
TriCore_INS_LOOP,
TriCore_INS_LT_A,
TriCore_INS_LT_B,
TriCore_INS_LT_BU,
TriCore_INS_LT_H,
TriCore_INS_LT_HU,
TriCore_INS_LT_U,
TriCore_INS_LT_W,
TriCore_INS_LT_WU,
TriCore_INS_LT,
TriCore_INS_MADDMS_H,
TriCore_INS_MADDM_H,
TriCore_INS_MADDRS_H,
TriCore_INS_MADDRS_Q,
TriCore_INS_MADDR_H,
TriCore_INS_MADDR_Q,
TriCore_INS_MADDSUMS_H,
TriCore_INS_MADDSUM_H,
TriCore_INS_MADDSURS_H,
TriCore_INS_MADDSUR_H,
TriCore_INS_MADDSUS_H,
TriCore_INS_MADDSU_H,
TriCore_INS_MADDS_H,
TriCore_INS_MADDS_Q,
TriCore_INS_MADDS_U,
TriCore_INS_MADDS,
TriCore_INS_MADD_H,
TriCore_INS_MADD_Q,
TriCore_INS_MADD_U,
TriCore_INS_MADD,
TriCore_INS_MAX_B,
TriCore_INS_MAX_BU,
TriCore_INS_MAX_H,
TriCore_INS_MAX_HU,
TriCore_INS_MAX_U,
TriCore_INS_MAX,
TriCore_INS_MFCR,
TriCore_INS_MIN_B,
TriCore_INS_MIN_BU,
TriCore_INS_MIN_H,
TriCore_INS_MIN_HU,
TriCore_INS_MIN_U,
TriCore_INS_MIN,
TriCore_INS_MOVH_A,
TriCore_INS_MOV_AA,
TriCore_INS_MOV_A,
TriCore_INS_MOV_D,
TriCore_INS_MOV_H,
TriCore_INS_MOV_U,
TriCore_INS_MOV,
TriCore_INS_MSUBADMS_H,
TriCore_INS_MSUBADM_H,
TriCore_INS_MSUBADRS_H,
TriCore_INS_MSUBADR_H,
TriCore_INS_MSUBADS_H,
TriCore_INS_MSUBAD_H,
TriCore_INS_MSUBMS_H,
TriCore_INS_MSUBM_H,
TriCore_INS_MSUBRS_H,
TriCore_INS_MSUBRS_Q,
TriCore_INS_MSUBR_H,
TriCore_INS_MSUBR_Q,
TriCore_INS_MSUBS_H,
TriCore_INS_MSUBS_Q,
TriCore_INS_MSUBS,
TriCore_INS_MSUB_H,
TriCore_INS_MSUB_Q,
TriCore_INS_MSUB,
TriCore_INS_MULM_H,
TriCore_INS_MULR_H,
TriCore_INS_MULR_Q,
TriCore_INS_MULS_U,
TriCore_INS_MULS,
TriCore_INS_MUL_H,
TriCore_INS_MUL_Q,
TriCore_INS_MUL_U,
TriCore_INS_MUL,
TriCore_INS_NAND_T,
TriCore_INS_NAND,
TriCore_INS_NEZ_A,
TriCore_INS_NE_A,
TriCore_INS_NE,
TriCore_INS_NOP,
TriCore_INS_NOR_T,
TriCore_INS_NOR,
TriCore_INS_NOT,
TriCore_INS_ORN_T,
TriCore_INS_ORN,
TriCore_INS_OR_ANDN_T,
TriCore_INS_OR_AND_T,
TriCore_INS_OR_EQ,
TriCore_INS_OR_GE_U,
TriCore_INS_OR_GE,
TriCore_INS_OR_LT_U,
TriCore_INS_OR_LT,
TriCore_INS_OR_NE,
TriCore_INS_OR_NOR_T,
TriCore_INS_OR_OR_T,
TriCore_INS_OR_T,
TriCore_INS_OR,
TriCore_INS_PACK,
TriCore_INS_PARITY,
TriCore_INS_POPCNT_W,
TriCore_INS_RESTORE,
TriCore_INS_RET,
TriCore_INS_RFE,
TriCore_INS_RFM,
TriCore_INS_RELCK,
TriCore_INS_RSUBS_U,
TriCore_INS_RSUBS,
TriCore_INS_RSUB,
TriCore_INS_SAT_BU,
TriCore_INS_SAT_B,
TriCore_INS_SAT_HU,
TriCore_INS_SAT_H,
TriCore_INS_SELN,
TriCore_INS_SEL,
TriCore_INS_SHAS,
TriCore_INS_SHA_H,
TriCore_INS_SHA,
TriCore_INS_SHUFFLE,
TriCore_INS_SH_ANDN_T,
TriCore_INS_SH_AND_T,
TriCore_INS_SH_EQ,
TriCore_INS_SH_GE_U,
TriCore_INS_SH_GE,
TriCore_INS_SH_H,
TriCore_INS_SH_LT_U,
TriCore_INS_SH_LT,
TriCore_INS_SH_NAND_T,
TriCore_INS_SH_NOR_T,
TriCore_INS_SH_ORN_T,
TriCore_INS_SH_OR_T,
TriCore_INS_SH_XNOR_T,
TriCore_INS_SH_XOR_T,
TriCore_INS_SH,
TriCore_INS_STLCX,
TriCore_INS_STUCX,
TriCore_INS_ST_A,
TriCore_INS_ST_B,
TriCore_INS_ST_DA,
TriCore_INS_ST_D,
TriCore_INS_ST_H,
TriCore_INS_ST_Q,
TriCore_INS_ST_T,
TriCore_INS_ST_W,
TriCore_INS_SUBC,
TriCore_INS_SUBS_HU,
TriCore_INS_SUBS_H,
TriCore_INS_SUBS_U,
TriCore_INS_SUBS,
TriCore_INS_SUBX,
TriCore_INS_SUB_A,
TriCore_INS_SUB_B,
TriCore_INS_SUB_H,
TriCore_INS_SUB,
TriCore_INS_SVLCX,
TriCore_INS_SWAPMSK_W,
TriCore_INS_SWAP_W,
TriCore_INS_SYSCALL,
TriCore_INS_TRAPSV,
TriCore_INS_TRAPV,
TriCore_INS_UNPACK,
TriCore_INS_WAIT,
TriCore_INS_XNOR_T,
TriCore_INS_XNOR,
TriCore_INS_XOR_EQ,
TriCore_INS_XOR_GE_U,
TriCore_INS_XOR_GE,
TriCore_INS_XOR_LT_U,
TriCore_INS_XOR_LT,
TriCore_INS_XOR_NE,
TriCore_INS_XOR_T,
TriCore_INS_XOR,
#include "./inc/TriCoreGenCSInsnEnum.inc"
TriCore_INS_ENDING, // <-- mark the end of the list of instructions