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arm: update core. this added a new instruction UDF. also updated Python+Java bindings accordingly

This commit is contained in:
Nguyen Anh Quynh 2014-08-13 22:38:15 +08:00
parent fd0f798343
commit b52f11f636
12 changed files with 20457 additions and 17719 deletions
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3
MCInstrDesc.h
View File

@ -109,7 +109,8 @@ enum {
MCID_Rematerializable,
MCID_CheapAsAMove,
MCID_ExtraSrcRegAllocReq,
MCID_ExtraDefRegAllocReq
MCID_ExtraDefRegAllocReq,
MCID_RegSequence,
};
/// MCInstrDesc - Describe properties that are true of each instruction in the

52
arch/ARM/ARMDisassembler.c
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@ -364,7 +364,7 @@ static DecodeStatus DecodeMRRC2(MCInst *Inst, unsigned Val,
uint64_t Address, const void *Decoder);
// Hacky: enable all features for disassembler
static uint64_t getFeatureBits(int mode)
uint64_t ARM_getFeatureBits(int mode)
{
uint64_t Bits = (uint64_t)-1; // everything by default
@ -377,7 +377,7 @@ static uint64_t getFeatureBits(int mode)
//Bits &= ~ARM_HasV8Ops;
//Bits &= ~ARM_HasV6Ops;
//Bits &= (~ARM_FeatureMClass);
Bits &= (~ARM_FeatureMClass);
// some features are mutually exclusive
if (mode & CS_MODE_THUMB) {
@ -4047,7 +4047,53 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst *Inst, unsigned Val,
static DecodeStatus DecodeMSRMask(MCInst *Inst, unsigned Val,
uint64_t Address, const void *Decoder)
{
if (!Val) return MCDisassembler_Fail;
uint64_t FeatureBits = ARM_getFeatureBits(Inst->csh->mode);
if (FeatureBits & ARM_FeatureMClass) {
unsigned ValLow = Val & 0xff;
// Validate the SYSm value first.
switch (ValLow) {
case 0: // apsr
case 1: // iapsr
case 2: // eapsr
case 3: // xpsr
case 5: // ipsr
case 6: // epsr
case 7: // iepsr
case 8: // msp
case 9: // psp
case 16: // primask
case 20: // control
break;
case 17: // basepri
case 18: // basepri_max
case 19: // faultmask
if (!(FeatureBits & ARM_HasV7Ops))
// Values basepri, basepri_max and faultmask are only valid for v7m.
return MCDisassembler_Fail;
break;
default:
return MCDisassembler_Fail;
}
// The ARMv7-M architecture has an additional 2-bit mask value in the MSR
// instruction (bits {11,10}). The mask is used only with apsr, iapsr,
// eapsr and xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates
// if the NZCVQ bits should be moved by the instruction. Bit mask{0}
// indicates the move for the GE{3:0} bits, the mask{0} bit can be set
// only if the processor includes the DSP extension.
if ((FeatureBits & ARM_HasV7Ops) && MCInst_getOpcode(Inst) == ARM_t2MSR_M) {
unsigned Mask = (Val >> 10) & 3;
if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
(!(FeatureBits & ARM_FeatureDSPThumb2) && Mask == 1))
return MCDisassembler_Fail;
}
} else {
// A/R class
if (Val == 0)
return MCDisassembler_Fail;
}
MCOperand_CreateImm0(Inst, Val);
return MCDisassembler_Success;
}

9250
arch/ARM/ARMGenAsmWriter.inc
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File diff suppressed because it is too large Load Diff

16005
arch/ARM/ARMGenDisassemblerTables.inc
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File diff suppressed because it is too large Load Diff

11927
arch/ARM/ARMGenInstrInfo.inc
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File diff suppressed because it is too large Load Diff

4
arch/ARM/ARMGenRegisterInfo.inc
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@ -7,7 +7,7 @@
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef GET_REGINFO_ENUM
@ -483,7 +483,7 @@ enum {
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef GET_REGINFO_MC_DESC

43
arch/ARM/ARMGenSubtargetInfo.inc
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@ -7,7 +7,7 @@
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
#ifdef GET_SUBTARGETINFO_ENUM
@ -48,26 +48,27 @@
#define ARM_FeatureVFPOnlySP (1ULL << 32)
#define ARM_FeatureVMLxForwarding (1ULL << 33)
#define ARM_FeatureVirtualization (1ULL << 34)
#define ARM_HasV4TOps (1ULL << 35)
#define ARM_HasV5TEOps (1ULL << 36)
#define ARM_HasV5TOps (1ULL << 37)
#define ARM_HasV6MOps (1ULL << 38)
#define ARM_HasV6Ops (1ULL << 39)
#define ARM_HasV6T2Ops (1ULL << 40)
#define ARM_HasV7Ops (1ULL << 41)
#define ARM_HasV8Ops (1ULL << 42)
#define ARM_ModeThumb (1ULL << 43)
#define ARM_ProcA5 (1ULL << 44)
#define ARM_ProcA7 (1ULL << 45)
#define ARM_ProcA8 (1ULL << 46)
#define ARM_ProcA9 (1ULL << 47)
#define ARM_ProcA12 (1ULL << 48)
#define ARM_ProcA15 (1ULL << 49)
#define ARM_ProcA53 (1ULL << 50)
#define ARM_ProcA57 (1ULL << 51)
#define ARM_ProcKrait (1ULL << 52)
#define ARM_ProcR5 (1ULL << 53)
#define ARM_ProcSwift (1ULL << 54)
#define ARM_FeatureZCZeroing (1ULL << 35)
#define ARM_HasV4TOps (1ULL << 36)
#define ARM_HasV5TEOps (1ULL << 37)
#define ARM_HasV5TOps (1ULL << 38)
#define ARM_HasV6MOps (1ULL << 39)
#define ARM_HasV6Ops (1ULL << 40)
#define ARM_HasV6T2Ops (1ULL << 41)
#define ARM_HasV7Ops (1ULL << 42)
#define ARM_HasV8Ops (1ULL << 43)
#define ARM_ModeThumb (1ULL << 44)
#define ARM_ProcA5 (1ULL << 45)
#define ARM_ProcA7 (1ULL << 46)
#define ARM_ProcA8 (1ULL << 47)
#define ARM_ProcA9 (1ULL << 48)
#define ARM_ProcA12 (1ULL << 49)
#define ARM_ProcA15 (1ULL << 50)
#define ARM_ProcA53 (1ULL << 51)
#define ARM_ProcA57 (1ULL << 52)
#define ARM_ProcKrait (1ULL << 53)
#define ARM_ProcR5 (1ULL << 54)
#define ARM_ProcSwift (1ULL << 55)
#endif // GET_SUBTARGETINFO_ENUM

27
arch/ARM/ARMInstPrinter.c
View File

@ -1335,27 +1335,21 @@ static void printCPSIFlag(MCInst *MI, unsigned OpNum, SStream *O)
}
}
// TODO
static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
{
MCOperand *Op = MCInst_getOperand(MI, OpNum);
#if 0 // TODO once below is fixed
unsigned SpecRegRBit = (unsigned int)MCOperand_getImm(Op) >> 4;
unsigned Mask = (unsigned int)MCOperand_getImm(Op) & 0xf;
#endif
unsigned SpecRegRBit = MCOperand_getImm(Op) >> 4;
unsigned Mask = MCOperand_getImm(Op) & 0xf;
// FIXME: FeatureMClass becomes mode??
//if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
//if (true)
{
unsigned SYSm = (unsigned int)MCOperand_getImm(Op);
if (ARM_getFeatureBits(MI->csh->mode) & ARM_FeatureMClass) {
unsigned SYSm = MCOperand_getImm(Op);
unsigned Opcode = MCInst_getOpcode(MI);
// For reads of the special registers ignore the "mask encoding" bits
// which are only for writes.
if (Opcode == ARM_t2MRS_M)
SYSm &= 0xff;
switch (SYSm) {
default: return; //llvm_unreachable("Unexpected mask value!");
default: //llvm_unreachable("Unexpected mask value!");
case 0:
case 0x800: SStream_concat0(O, "apsr"); return; // with _nzcvq bits is an alias for aspr
case 0x400: SStream_concat0(O, "apsr_g"); return;
@ -1394,13 +1388,13 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
case 0x814: SStream_concat0(O, "control"); return;
}
}
#if 0 // TODO once above is fixed
// As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
// APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
SStream_concat0(O, "apsr_");
SStream_concat0(O, "APSR_");
switch (Mask) {
default: return; //llvm_unreachable("Unexpected mask value!");
default: // llvm_unreachable("Unexpected mask value!");
case 4: SStream_concat0(O, "g"); return;
case 8: SStream_concat0(O, "nzcvq"); return;
case 12: SStream_concat0(O, "nzcvqg"); return;
@ -1408,9 +1402,9 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
}
if (SpecRegRBit)
SStream_concat0(O, "spsr");
SStream_concat0(O, "SPSR");
else
SStream_concat0(O, "cpsr");
SStream_concat0(O, "CPSR");
if (Mask) {
SStream_concat0(O, "_");
@ -1419,7 +1413,6 @@ static void printMSRMaskOperand(MCInst *MI, unsigned OpNum, SStream *O)
if (Mask & 2) SStream_concat0(O, "x");
if (Mask & 1) SStream_concat0(O, "c");
}
#endif
}
static void printPredicateOperand(MCInst *MI, unsigned OpNum, SStream *O)

74
arch/ARM/ARMMapping.c
View File

@ -832,12 +832,6 @@ static insn_map insns[] = {
ARM_LDRD, ARM_INS_LDRD,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
#endif
},
{
ARM_LDRD_PAIR, ARM_INS_LDRD,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
#endif
},
{
@ -2134,12 +2128,6 @@ static insn_map insns[] = {
ARM_STRD, ARM_INS_STRD,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
#endif
},
{
ARM_STRD_PAIR, ARM_INS_STRD,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V5TE, 0 }, 0, 0
#endif
},
{
@ -2416,6 +2404,12 @@ static insn_map insns[] = {
ARM_UBFX, ARM_INS_UBFX,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, ARM_GRP_V6T2, 0 }, 0, 0
#endif
},
{
ARM_UDF, ARM_INS_UDF,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_ARM, 0 }, 0, 0
#endif
},
{
@ -11049,13 +11043,13 @@ static insn_map insns[] = {
{
ARM_t2DMB, ARM_INS_DMB,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0
#endif
},
{
ARM_t2DSB, ARM_INS_DSB,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0
#endif
},
{
@ -11085,7 +11079,7 @@ static insn_map insns[] = {
{
ARM_t2ISB, ARM_INS_ISB,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_DATABARRIER, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_DATABARRIER, 0 }, 0, 0
#endif
},
{
@ -11139,49 +11133,49 @@ static insn_map insns[] = {
{
ARM_t2LDC2L_OFFSET, ARM_INS_LDC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2LDC2L_OPTION, ARM_INS_LDC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2LDC2L_POST, ARM_INS_LDC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2LDC2L_PRE, ARM_INS_LDC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2LDC2_OFFSET, ARM_INS_LDC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2LDC2_OPTION, ARM_INS_LDC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2LDC2_POST, ARM_INS_LDC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2LDC2_PRE, ARM_INS_LDC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
@ -12309,49 +12303,49 @@ static insn_map insns[] = {
{
ARM_t2STC2L_OFFSET, ARM_INS_STC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2STC2L_OPTION, ARM_INS_STC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2STC2L_POST, ARM_INS_STC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2STC2L_PRE, ARM_INS_STC2L,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2STC2_OFFSET, ARM_INS_STC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2STC2_OPTION, ARM_INS_STC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2STC2_POST, ARM_INS_STC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2STC2_PRE, ARM_INS_STC2,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_PREV8, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_PREV8, ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
@ -12754,6 +12748,12 @@ static insn_map insns[] = {
ARM_t2UBFX, ARM_INS_UBFX,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
ARM_t2UDF, ARM_INS_UDF,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB2, 0 }, 0, 0
#endif
},
{
@ -13035,7 +13035,7 @@ static insn_map insns[] = {
{
ARM_tBLXi, ARM_INS_BLX,
#ifndef CAPSTONE_DIET
{ ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, 0 }, 0, 0
{ ARM_REG_SP, 0 }, { ARM_REG_LR, 0 }, { ARM_GRP_THUMB, ARM_GRP_V5T, ARM_GRP_NOTMCLASS, 0 }, 0, 0
#endif
},
{
@ -13293,7 +13293,7 @@ static insn_map insns[] = {
{
ARM_tSETEND, ARM_INS_SETEND,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
{ 0 }, { 0 }, { ARM_GRP_NOTMCLASS, 0 }, 0, 0
#endif
},
{
@ -13396,6 +13396,12 @@ static insn_map insns[] = {
ARM_tTST, ARM_INS_TST,
#ifndef CAPSTONE_DIET
{ 0 }, { ARM_REG_CPSR, 0 }, { ARM_GRP_THUMB, ARM_GRP_THUMB1ONLY, 0 }, 0, 0
#endif
},
{
ARM_tUDF, ARM_INS_UDF,
#ifndef CAPSTONE_DIET
{ 0 }, { 0 }, { ARM_GRP_THUMB, 0 }, 0, 0
#endif
},
{
@ -13677,6 +13683,7 @@ static name_map insn_name_maps[] = {
{ ARM_INS_UADD8, "uadd8" },
{ ARM_INS_UASX, "uasx" },
{ ARM_INS_UBFX, "ubfx" },
{ ARM_INS_UDF, "udf" },
{ ARM_INS_UDIV, "udiv" },
{ ARM_INS_UHADD16, "uhadd16" },
{ ARM_INS_UHADD8, "uhadd8" },
@ -13954,7 +13961,6 @@ static unsigned int insn_rel[] = {
ARM_BL_pred,
ARM_BLXi,
ARM_tBL,
ARM_tB,
ARM_tBLXi,
0
};

395
bindings/java/capstone/Arm_const.java
View File

@ -402,203 +402,204 @@ public class Arm_const {
public static final int ARM_INS_UADD8 = 227;
public static final int ARM_INS_UASX = 228;
public static final int ARM_INS_UBFX = 229;
public static final int ARM_INS_UDIV = 230;
public static final int ARM_INS_UHADD16 = 231;
public static final int ARM_INS_UHADD8 = 232;
public static final int ARM_INS_UHASX = 233;
public static final int ARM_INS_UHSAX = 234;
public static final int ARM_INS_UHSUB16 = 235;
public static final int ARM_INS_UHSUB8 = 236;
public static final int ARM_INS_UMAAL = 237;
public static final int ARM_INS_UMLAL = 238;
public static final int ARM_INS_UMULL = 239;
public static final int ARM_INS_UQADD16 = 240;
public static final int ARM_INS_UQADD8 = 241;
public static final int ARM_INS_UQASX = 242;
public static final int ARM_INS_UQSAX = 243;
public static final int ARM_INS_UQSUB16 = 244;
public static final int ARM_INS_UQSUB8 = 245;
public static final int ARM_INS_USAD8 = 246;
public static final int ARM_INS_USADA8 = 247;
public static final int ARM_INS_USAT = 248;
public static final int ARM_INS_USAT16 = 249;
public static final int ARM_INS_USAX = 250;
public static final int ARM_INS_USUB16 = 251;
public static final int ARM_INS_USUB8 = 252;
public static final int ARM_INS_UXTAB = 253;
public static final int ARM_INS_UXTAB16 = 254;
public static final int ARM_INS_UXTAH = 255;
public static final int ARM_INS_UXTB = 256;
public static final int ARM_INS_UXTB16 = 257;
public static final int ARM_INS_UXTH = 258;
public static final int ARM_INS_VABAL = 259;
public static final int ARM_INS_VABA = 260;
public static final int ARM_INS_VABDL = 261;
public static final int ARM_INS_VABD = 262;
public static final int ARM_INS_VABS = 263;
public static final int ARM_INS_VACGE = 264;
public static final int ARM_INS_VACGT = 265;
public static final int ARM_INS_VADD = 266;
public static final int ARM_INS_VADDHN = 267;
public static final int ARM_INS_VADDL = 268;
public static final int ARM_INS_VADDW = 269;
public static final int ARM_INS_VAND = 270;
public static final int ARM_INS_VBIC = 271;
public static final int ARM_INS_VBIF = 272;
public static final int ARM_INS_VBIT = 273;
public static final int ARM_INS_VBSL = 274;
public static final int ARM_INS_VCEQ = 275;
public static final int ARM_INS_VCGE = 276;
public static final int ARM_INS_VCGT = 277;
public static final int ARM_INS_VCLE = 278;
public static final int ARM_INS_VCLS = 279;
public static final int ARM_INS_VCLT = 280;
public static final int ARM_INS_VCLZ = 281;
public static final int ARM_INS_VCMP = 282;
public static final int ARM_INS_VCMPE = 283;
public static final int ARM_INS_VCNT = 284;
public static final int ARM_INS_VCVTA = 285;
public static final int ARM_INS_VCVTB = 286;
public static final int ARM_INS_VCVT = 287;
public static final int ARM_INS_VCVTM = 288;
public static final int ARM_INS_VCVTN = 289;
public static final int ARM_INS_VCVTP = 290;
public static final int ARM_INS_VCVTT = 291;
public static final int ARM_INS_VDIV = 292;
public static final int ARM_INS_VDUP = 293;
public static final int ARM_INS_VEOR = 294;
public static final int ARM_INS_VEXT = 295;
public static final int ARM_INS_VFMA = 296;
public static final int ARM_INS_VFMS = 297;
public static final int ARM_INS_VFNMA = 298;
public static final int ARM_INS_VFNMS = 299;
public static final int ARM_INS_VHADD = 300;
public static final int ARM_INS_VHSUB = 301;
public static final int ARM_INS_VLD1 = 302;
public static final int ARM_INS_VLD2 = 303;
public static final int ARM_INS_VLD3 = 304;
public static final int ARM_INS_VLD4 = 305;
public static final int ARM_INS_VLDMDB = 306;
public static final int ARM_INS_VLDMIA = 307;
public static final int ARM_INS_VLDR = 308;
public static final int ARM_INS_VMAXNM = 309;
public static final int ARM_INS_VMAX = 310;
public static final int ARM_INS_VMINNM = 311;
public static final int ARM_INS_VMIN = 312;
public static final int ARM_INS_VMLA = 313;
public static final int ARM_INS_VMLAL = 314;
public static final int ARM_INS_VMLS = 315;
public static final int ARM_INS_VMLSL = 316;
public static final int ARM_INS_VMOVL = 317;
public static final int ARM_INS_VMOVN = 318;
public static final int ARM_INS_VMSR = 319;
public static final int ARM_INS_VMUL = 320;
public static final int ARM_INS_VMULL = 321;
public static final int ARM_INS_VMVN = 322;
public static final int ARM_INS_VNEG = 323;
public static final int ARM_INS_VNMLA = 324;
public static final int ARM_INS_VNMLS = 325;
public static final int ARM_INS_VNMUL = 326;
public static final int ARM_INS_VORN = 327;
public static final int ARM_INS_VORR = 328;
public static final int ARM_INS_VPADAL = 329;
public static final int ARM_INS_VPADDL = 330;
public static final int ARM_INS_VPADD = 331;
public static final int ARM_INS_VPMAX = 332;
public static final int ARM_INS_VPMIN = 333;
public static final int ARM_INS_VQABS = 334;
public static final int ARM_INS_VQADD = 335;
public static final int ARM_INS_VQDMLAL = 336;
public static final int ARM_INS_VQDMLSL = 337;
public static final int ARM_INS_VQDMULH = 338;
public static final int ARM_INS_VQDMULL = 339;
public static final int ARM_INS_VQMOVUN = 340;
public static final int ARM_INS_VQMOVN = 341;
public static final int ARM_INS_VQNEG = 342;
public static final int ARM_INS_VQRDMULH = 343;
public static final int ARM_INS_VQRSHL = 344;
public static final int ARM_INS_VQRSHRN = 345;
public static final int ARM_INS_VQRSHRUN = 346;
public static final int ARM_INS_VQSHL = 347;
public static final int ARM_INS_VQSHLU = 348;
public static final int ARM_INS_VQSHRN = 349;
public static final int ARM_INS_VQSHRUN = 350;
public static final int ARM_INS_VQSUB = 351;
public static final int ARM_INS_VRADDHN = 352;
public static final int ARM_INS_VRECPE = 353;
public static final int ARM_INS_VRECPS = 354;
public static final int ARM_INS_VREV16 = 355;
public static final int ARM_INS_VREV32 = 356;
public static final int ARM_INS_VREV64 = 357;
public static final int ARM_INS_VRHADD = 358;
public static final int ARM_INS_VRINTA = 359;
public static final int ARM_INS_VRINTM = 360;
public static final int ARM_INS_VRINTN = 361;
public static final int ARM_INS_VRINTP = 362;
public static final int ARM_INS_VRINTR = 363;
public static final int ARM_INS_VRINTX = 364;
public static final int ARM_INS_VRINTZ = 365;
public static final int ARM_INS_VRSHL = 366;
public static final int ARM_INS_VRSHRN = 367;
public static final int ARM_INS_VRSHR = 368;
public static final int ARM_INS_VRSQRTE = 369;
public static final int ARM_INS_VRSQRTS = 370;
public static final int ARM_INS_VRSRA = 371;
public static final int ARM_INS_VRSUBHN = 372;
public static final int ARM_INS_VSELEQ = 373;
public static final int ARM_INS_VSELGE = 374;
public static final int ARM_INS_VSELGT = 375;
public static final int ARM_INS_VSELVS = 376;
public static final int ARM_INS_VSHLL = 377;
public static final int ARM_INS_VSHL = 378;
public static final int ARM_INS_VSHRN = 379;
public static final int ARM_INS_VSHR = 380;
public static final int ARM_INS_VSLI = 381;
public static final int ARM_INS_VSQRT = 382;
public static final int ARM_INS_VSRA = 383;
public static final int ARM_INS_VSRI = 384;
public static final int ARM_INS_VST1 = 385;
public static final int ARM_INS_VST2 = 386;
public static final int ARM_INS_VST3 = 387;
public static final int ARM_INS_VST4 = 388;
public static final int ARM_INS_VSTMDB = 389;
public static final int ARM_INS_VSTMIA = 390;
public static final int ARM_INS_VSTR = 391;
public static final int ARM_INS_VSUB = 392;
public static final int ARM_INS_VSUBHN = 393;
public static final int ARM_INS_VSUBL = 394;
public static final int ARM_INS_VSUBW = 395;
public static final int ARM_INS_VSWP = 396;
public static final int ARM_INS_VTBL = 397;
public static final int ARM_INS_VTBX = 398;
public static final int ARM_INS_VCVTR = 399;
public static final int ARM_INS_VTRN = 400;
public static final int ARM_INS_VTST = 401;
public static final int ARM_INS_VUZP = 402;
public static final int ARM_INS_VZIP = 403;
public static final int ARM_INS_ADDW = 404;
public static final int ARM_INS_ASR = 405;
public static final int ARM_INS_DCPS1 = 406;
public static final int ARM_INS_DCPS2 = 407;
public static final int ARM_INS_DCPS3 = 408;
public static final int ARM_INS_IT = 409;
public static final int ARM_INS_LSL = 410;
public static final int ARM_INS_LSR = 411;
public static final int ARM_INS_ASRS = 412;
public static final int ARM_INS_LSRS = 413;
public static final int ARM_INS_ORN = 414;
public static final int ARM_INS_ROR = 415;
public static final int ARM_INS_RRX = 416;
public static final int ARM_INS_SUBS = 417;
public static final int ARM_INS_SUBW = 418;
public static final int ARM_INS_TBB = 419;
public static final int ARM_INS_TBH = 420;
public static final int ARM_INS_CBNZ = 421;
public static final int ARM_INS_CBZ = 422;
public static final int ARM_INS_MOVS = 423;
public static final int ARM_INS_POP = 424;
public static final int ARM_INS_PUSH = 425;
public static final int ARM_INS_MAX = 426;
public static final int ARM_INS_UDF = 230;
public static final int ARM_INS_UDIV = 231;
public static final int ARM_INS_UHADD16 = 232;
public static final int ARM_INS_UHADD8 = 233;
public static final int ARM_INS_UHASX = 234;
public static final int ARM_INS_UHSAX = 235;
public static final int ARM_INS_UHSUB16 = 236;
public static final int ARM_INS_UHSUB8 = 237;
public static final int ARM_INS_UMAAL = 238;
public static final int ARM_INS_UMLAL = 239;
public static final int ARM_INS_UMULL = 240;
public static final int ARM_INS_UQADD16 = 241;
public static final int ARM_INS_UQADD8 = 242;
public static final int ARM_INS_UQASX = 243;
public static final int ARM_INS_UQSAX = 244;
public static final int ARM_INS_UQSUB16 = 245;
public static final int ARM_INS_UQSUB8 = 246;
public static final int ARM_INS_USAD8 = 247;
public static final int ARM_INS_USADA8 = 248;
public static final int ARM_INS_USAT = 249;
public static final int ARM_INS_USAT16 = 250;
public static final int ARM_INS_USAX = 251;
public static final int ARM_INS_USUB16 = 252;
public static final int ARM_INS_USUB8 = 253;
public static final int ARM_INS_UXTAB = 254;
public static final int ARM_INS_UXTAB16 = 255;
public static final int ARM_INS_UXTAH = 256;
public static final int ARM_INS_UXTB = 257;
public static final int ARM_INS_UXTB16 = 258;
public static final int ARM_INS_UXTH = 259;
public static final int ARM_INS_VABAL = 260;
public static final int ARM_INS_VABA = 261;
public static final int ARM_INS_VABDL = 262;
public static final int ARM_INS_VABD = 263;
public static final int ARM_INS_VABS = 264;
public static final int ARM_INS_VACGE = 265;
public static final int ARM_INS_VACGT = 266;
public static final int ARM_INS_VADD = 267;
public static final int ARM_INS_VADDHN = 268;
public static final int ARM_INS_VADDL = 269;
public static final int ARM_INS_VADDW = 270;
public static final int ARM_INS_VAND = 271;
public static final int ARM_INS_VBIC = 272;
public static final int ARM_INS_VBIF = 273;
public static final int ARM_INS_VBIT = 274;
public static final int ARM_INS_VBSL = 275;
public static final int ARM_INS_VCEQ = 276;
public static final int ARM_INS_VCGE = 277;
public static final int ARM_INS_VCGT = 278;
public static final int ARM_INS_VCLE = 279;
public static final int ARM_INS_VCLS = 280;
public static final int ARM_INS_VCLT = 281;
public static final int ARM_INS_VCLZ = 282;
public static final int ARM_INS_VCMP = 283;
public static final int ARM_INS_VCMPE = 284;
public static final int ARM_INS_VCNT = 285;
public static final int ARM_INS_VCVTA = 286;
public static final int ARM_INS_VCVTB = 287;
public static final int ARM_INS_VCVT = 288;
public static final int ARM_INS_VCVTM = 289;
public static final int ARM_INS_VCVTN = 290;
public static final int ARM_INS_VCVTP = 291;
public static final int ARM_INS_VCVTT = 292;
public static final int ARM_INS_VDIV = 293;
public static final int ARM_INS_VDUP = 294;
public static final int ARM_INS_VEOR = 295;
public static final int ARM_INS_VEXT = 296;
public static final int ARM_INS_VFMA = 297;
public static final int ARM_INS_VFMS = 298;
public static final int ARM_INS_VFNMA = 299;
public static final int ARM_INS_VFNMS = 300;
public static final int ARM_INS_VHADD = 301;
public static final int ARM_INS_VHSUB = 302;
public static final int ARM_INS_VLD1 = 303;
public static final int ARM_INS_VLD2 = 304;
public static final int ARM_INS_VLD3 = 305;
public static final int ARM_INS_VLD4 = 306;
public static final int ARM_INS_VLDMDB = 307;
public static final int ARM_INS_VLDMIA = 308;
public static final int ARM_INS_VLDR = 309;
public static final int ARM_INS_VMAXNM = 310;
public static final int ARM_INS_VMAX = 311;
public static final int ARM_INS_VMINNM = 312;
public static final int ARM_INS_VMIN = 313;
public static final int ARM_INS_VMLA = 314;
public static final int ARM_INS_VMLAL = 315;
public static final int ARM_INS_VMLS = 316;
public static final int ARM_INS_VMLSL = 317;
public static final int ARM_INS_VMOVL = 318;
public static final int ARM_INS_VMOVN = 319;
public static final int ARM_INS_VMSR = 320;
public static final int ARM_INS_VMUL = 321;
public static final int ARM_INS_VMULL = 322;
public static final int ARM_INS_VMVN = 323;
public static final int ARM_INS_VNEG = 324;
public static final int ARM_INS_VNMLA = 325;
public static final int ARM_INS_VNMLS = 326;
public static final int ARM_INS_VNMUL = 327;
public static final int ARM_INS_VORN = 328;
public static final int ARM_INS_VORR = 329;
public static final int ARM_INS_VPADAL = 330;
public static final int ARM_INS_VPADDL = 331;
public static final int ARM_INS_VPADD = 332;
public static final int ARM_INS_VPMAX = 333;
public static final int ARM_INS_VPMIN = 334;
public static final int ARM_INS_VQABS = 335;
public static final int ARM_INS_VQADD = 336;
public static final int ARM_INS_VQDMLAL = 337;
public static final int ARM_INS_VQDMLSL = 338;
public static final int ARM_INS_VQDMULH = 339;
public static final int ARM_INS_VQDMULL = 340;
public static final int ARM_INS_VQMOVUN = 341;
public static final int ARM_INS_VQMOVN = 342;
public static final int ARM_INS_VQNEG = 343;
public static final int ARM_INS_VQRDMULH = 344;
public static final int ARM_INS_VQRSHL = 345;
public static final int ARM_INS_VQRSHRN = 346;
public static final int ARM_INS_VQRSHRUN = 347;
public static final int ARM_INS_VQSHL = 348;
public static final int ARM_INS_VQSHLU = 349;
public static final int ARM_INS_VQSHRN = 350;
public static final int ARM_INS_VQSHRUN = 351;
public static final int ARM_INS_VQSUB = 352;
public static final int ARM_INS_VRADDHN = 353;
public static final int ARM_INS_VRECPE = 354;
public static final int ARM_INS_VRECPS = 355;
public static final int ARM_INS_VREV16 = 356;
public static final int ARM_INS_VREV32 = 357;
public static final int ARM_INS_VREV64 = 358;
public static final int ARM_INS_VRHADD = 359;
public static final int ARM_INS_VRINTA = 360;
public static final int ARM_INS_VRINTM = 361;
public static final int ARM_INS_VRINTN = 362;
public static final int ARM_INS_VRINTP = 363;
public static final int ARM_INS_VRINTR = 364;
public static final int ARM_INS_VRINTX = 365;
public static final int ARM_INS_VRINTZ = 366;
public static final int ARM_INS_VRSHL = 367;
public static final int ARM_INS_VRSHRN = 368;
public static final int ARM_INS_VRSHR = 369;
public static final int ARM_INS_VRSQRTE = 370;
public static final int ARM_INS_VRSQRTS = 371;
public static final int ARM_INS_VRSRA = 372;
public static final int ARM_INS_VRSUBHN = 373;
public static final int ARM_INS_VSELEQ = 374;
public static final int ARM_INS_VSELGE = 375;
public static final int ARM_INS_VSELGT = 376;
public static final int ARM_INS_VSELVS = 377;
public static final int ARM_INS_VSHLL = 378;
public static final int ARM_INS_VSHL = 379;
public static final int ARM_INS_VSHRN = 380;
public static final int ARM_INS_VSHR = 381;
public static final int ARM_INS_VSLI = 382;
public static final int ARM_INS_VSQRT = 383;
public static final int ARM_INS_VSRA = 384;
public static final int ARM_INS_VSRI = 385;
public static final int ARM_INS_VST1 = 386;
public static final int ARM_INS_VST2 = 387;
public static final int ARM_INS_VST3 = 388;
public static final int ARM_INS_VST4 = 389;
public static final int ARM_INS_VSTMDB = 390;
public static final int ARM_INS_VSTMIA = 391;
public static final int ARM_INS_VSTR = 392;
public static final int ARM_INS_VSUB = 393;
public static final int ARM_INS_VSUBHN = 394;
public static final int ARM_INS_VSUBL = 395;
public static final int ARM_INS_VSUBW = 396;
public static final int ARM_INS_VSWP = 397;
public static final int ARM_INS_VTBL = 398;
public static final int ARM_INS_VTBX = 399;
public static final int ARM_INS_VCVTR = 400;
public static final int ARM_INS_VTRN = 401;
public static final int ARM_INS_VTST = 402;
public static final int ARM_INS_VUZP = 403;
public static final int ARM_INS_VZIP = 404;
public static final int ARM_INS_ADDW = 405;
public static final int ARM_INS_ASR = 406;
public static final int ARM_INS_DCPS1 = 407;
public static final int ARM_INS_DCPS2 = 408;
public static final int ARM_INS_DCPS3 = 409;
public static final int ARM_INS_IT = 410;
public static final int ARM_INS_LSL = 411;
public static final int ARM_INS_LSR = 412;
public static final int ARM_INS_ASRS = 413;
public static final int ARM_INS_LSRS = 414;
public static final int ARM_INS_ORN = 415;
public static final int ARM_INS_ROR = 416;
public static final int ARM_INS_RRX = 417;
public static final int ARM_INS_SUBS = 418;
public static final int ARM_INS_SUBW = 419;
public static final int ARM_INS_TBB = 420;
public static final int ARM_INS_TBH = 421;
public static final int ARM_INS_CBNZ = 422;
public static final int ARM_INS_CBZ = 423;
public static final int ARM_INS_MOVS = 424;
public static final int ARM_INS_POP = 425;
public static final int ARM_INS_PUSH = 426;
public static final int ARM_INS_MAX = 427;
// Group of ARM instructions

395
bindings/python/capstone/arm_const.py
View File

@ -399,203 +399,204 @@ ARM_INS_UADD16 = 226
ARM_INS_UADD8 = 227
ARM_INS_UASX = 228
ARM_INS_UBFX = 229
ARM_INS_UDIV = 230
ARM_INS_UHADD16 = 231
ARM_INS_UHADD8 = 232
ARM_INS_UHASX = 233
ARM_INS_UHSAX = 234
ARM_INS_UHSUB16 = 235
ARM_INS_UHSUB8 = 236
ARM_INS_UMAAL = 237
ARM_INS_UMLAL = 238
ARM_INS_UMULL = 239
ARM_INS_UQADD16 = 240
ARM_INS_UQADD8 = 241
ARM_INS_UQASX = 242
ARM_INS_UQSAX = 243
ARM_INS_UQSUB16 = 244
ARM_INS_UQSUB8 = 245
ARM_INS_USAD8 = 246
ARM_INS_USADA8 = 247
ARM_INS_USAT = 248
ARM_INS_USAT16 = 249
ARM_INS_USAX = 250
ARM_INS_USUB16 = 251
ARM_INS_USUB8 = 252
ARM_INS_UXTAB = 253
ARM_INS_UXTAB16 = 254
ARM_INS_UXTAH = 255
ARM_INS_UXTB = 256
ARM_INS_UXTB16 = 257
ARM_INS_UXTH = 258
ARM_INS_VABAL = 259
ARM_INS_VABA = 260
ARM_INS_VABDL = 261
ARM_INS_VABD = 262
ARM_INS_VABS = 263
ARM_INS_VACGE = 264
ARM_INS_VACGT = 265
ARM_INS_VADD = 266
ARM_INS_VADDHN = 267
ARM_INS_VADDL = 268
ARM_INS_VADDW = 269
ARM_INS_VAND = 270
ARM_INS_VBIC = 271
ARM_INS_VBIF = 272
ARM_INS_VBIT = 273
ARM_INS_VBSL = 274
ARM_INS_VCEQ = 275
ARM_INS_VCGE = 276
ARM_INS_VCGT = 277
ARM_INS_VCLE = 278
ARM_INS_VCLS = 279
ARM_INS_VCLT = 280
ARM_INS_VCLZ = 281
ARM_INS_VCMP = 282
ARM_INS_VCMPE = 283
ARM_INS_VCNT = 284
ARM_INS_VCVTA = 285
ARM_INS_VCVTB = 286
ARM_INS_VCVT = 287
ARM_INS_VCVTM = 288
ARM_INS_VCVTN = 289
ARM_INS_VCVTP = 290
ARM_INS_VCVTT = 291
ARM_INS_VDIV = 292
ARM_INS_VDUP = 293
ARM_INS_VEOR = 294
ARM_INS_VEXT = 295
ARM_INS_VFMA = 296
ARM_INS_VFMS = 297
ARM_INS_VFNMA = 298
ARM_INS_VFNMS = 299
ARM_INS_VHADD = 300
ARM_INS_VHSUB = 301
ARM_INS_VLD1 = 302
ARM_INS_VLD2 = 303
ARM_INS_VLD3 = 304
ARM_INS_VLD4 = 305
ARM_INS_VLDMDB = 306
ARM_INS_VLDMIA = 307
ARM_INS_VLDR = 308
ARM_INS_VMAXNM = 309
ARM_INS_VMAX = 310
ARM_INS_VMINNM = 311
ARM_INS_VMIN = 312
ARM_INS_VMLA = 313
ARM_INS_VMLAL = 314
ARM_INS_VMLS = 315
ARM_INS_VMLSL = 316
ARM_INS_VMOVL = 317
ARM_INS_VMOVN = 318
ARM_INS_VMSR = 319
ARM_INS_VMUL = 320
ARM_INS_VMULL = 321
ARM_INS_VMVN = 322
ARM_INS_VNEG = 323
ARM_INS_VNMLA = 324
ARM_INS_VNMLS = 325
ARM_INS_VNMUL = 326
ARM_INS_VORN = 327
ARM_INS_VORR = 328
ARM_INS_VPADAL = 329
ARM_INS_VPADDL = 330
ARM_INS_VPADD = 331
ARM_INS_VPMAX = 332
ARM_INS_VPMIN = 333
ARM_INS_VQABS = 334
ARM_INS_VQADD = 335
ARM_INS_VQDMLAL = 336
ARM_INS_VQDMLSL = 337
ARM_INS_VQDMULH = 338
ARM_INS_VQDMULL = 339
ARM_INS_VQMOVUN = 340
ARM_INS_VQMOVN = 341
ARM_INS_VQNEG = 342
ARM_INS_VQRDMULH = 343
ARM_INS_VQRSHL = 344
ARM_INS_VQRSHRN = 345
ARM_INS_VQRSHRUN = 346
ARM_INS_VQSHL = 347
ARM_INS_VQSHLU = 348
ARM_INS_VQSHRN = 349
ARM_INS_VQSHRUN = 350
ARM_INS_VQSUB = 351
ARM_INS_VRADDHN = 352
ARM_INS_VRECPE = 353
ARM_INS_VRECPS = 354
ARM_INS_VREV16 = 355
ARM_INS_VREV32 = 356
ARM_INS_VREV64 = 357
ARM_INS_VRHADD = 358
ARM_INS_VRINTA = 359
ARM_INS_VRINTM = 360
ARM_INS_VRINTN = 361
ARM_INS_VRINTP = 362
ARM_INS_VRINTR = 363
ARM_INS_VRINTX = 364
ARM_INS_VRINTZ = 365
ARM_INS_VRSHL = 366
ARM_INS_VRSHRN = 367
ARM_INS_VRSHR = 368
ARM_INS_VRSQRTE = 369
ARM_INS_VRSQRTS = 370
ARM_INS_VRSRA = 371
ARM_INS_VRSUBHN = 372
ARM_INS_VSELEQ = 373
ARM_INS_VSELGE = 374
ARM_INS_VSELGT = 375
ARM_INS_VSELVS = 376
ARM_INS_VSHLL = 377
ARM_INS_VSHL = 378
ARM_INS_VSHRN = 379
ARM_INS_VSHR = 380
ARM_INS_VSLI = 381
ARM_INS_VSQRT = 382
ARM_INS_VSRA = 383
ARM_INS_VSRI = 384
ARM_INS_VST1 = 385
ARM_INS_VST2 = 386
ARM_INS_VST3 = 387
ARM_INS_VST4 = 388
ARM_INS_VSTMDB = 389
ARM_INS_VSTMIA = 390
ARM_INS_VSTR = 391
ARM_INS_VSUB = 392
ARM_INS_VSUBHN = 393
ARM_INS_VSUBL = 394
ARM_INS_VSUBW = 395
ARM_INS_VSWP = 396
ARM_INS_VTBL = 397
ARM_INS_VTBX = 398
ARM_INS_VCVTR = 399
ARM_INS_VTRN = 400
ARM_INS_VTST = 401
ARM_INS_VUZP = 402
ARM_INS_VZIP = 403
ARM_INS_ADDW = 404
ARM_INS_ASR = 405
ARM_INS_DCPS1 = 406
ARM_INS_DCPS2 = 407
ARM_INS_DCPS3 = 408
ARM_INS_IT = 409
ARM_INS_LSL = 410
ARM_INS_LSR = 411
ARM_INS_ASRS = 412
ARM_INS_LSRS = 413
ARM_INS_ORN = 414
ARM_INS_ROR = 415
ARM_INS_RRX = 416
ARM_INS_SUBS = 417
ARM_INS_SUBW = 418
ARM_INS_TBB = 419
ARM_INS_TBH = 420
ARM_INS_CBNZ = 421
ARM_INS_CBZ = 422
ARM_INS_MOVS = 423
ARM_INS_POP = 424
ARM_INS_PUSH = 425
ARM_INS_MAX = 426
ARM_INS_UDF = 230
ARM_INS_UDIV = 231
ARM_INS_UHADD16 = 232
ARM_INS_UHADD8 = 233
ARM_INS_UHASX = 234
ARM_INS_UHSAX = 235
ARM_INS_UHSUB16 = 236
ARM_INS_UHSUB8 = 237
ARM_INS_UMAAL = 238
ARM_INS_UMLAL = 239
ARM_INS_UMULL = 240
ARM_INS_UQADD16 = 241
ARM_INS_UQADD8 = 242
ARM_INS_UQASX = 243
ARM_INS_UQSAX = 244
ARM_INS_UQSUB16 = 245
ARM_INS_UQSUB8 = 246
ARM_INS_USAD8 = 247
ARM_INS_USADA8 = 248
ARM_INS_USAT = 249
ARM_INS_USAT16 = 250
ARM_INS_USAX = 251
ARM_INS_USUB16 = 252
ARM_INS_USUB8 = 253
ARM_INS_UXTAB = 254
ARM_INS_UXTAB16 = 255
ARM_INS_UXTAH = 256
ARM_INS_UXTB = 257
ARM_INS_UXTB16 = 258
ARM_INS_UXTH = 259
ARM_INS_VABAL = 260
ARM_INS_VABA = 261
ARM_INS_VABDL = 262
ARM_INS_VABD = 263
ARM_INS_VABS = 264
ARM_INS_VACGE = 265
ARM_INS_VACGT = 266
ARM_INS_VADD = 267
ARM_INS_VADDHN = 268
ARM_INS_VADDL = 269
ARM_INS_VADDW = 270
ARM_INS_VAND = 271
ARM_INS_VBIC = 272
ARM_INS_VBIF = 273
ARM_INS_VBIT = 274
ARM_INS_VBSL = 275
ARM_INS_VCEQ = 276
ARM_INS_VCGE = 277
ARM_INS_VCGT = 278
ARM_INS_VCLE = 279
ARM_INS_VCLS = 280
ARM_INS_VCLT = 281
ARM_INS_VCLZ = 282
ARM_INS_VCMP = 283
ARM_INS_VCMPE = 284
ARM_INS_VCNT = 285
ARM_INS_VCVTA = 286
ARM_INS_VCVTB = 287
ARM_INS_VCVT = 288
ARM_INS_VCVTM = 289
ARM_INS_VCVTN = 290
ARM_INS_VCVTP = 291
ARM_INS_VCVTT = 292
ARM_INS_VDIV = 293
ARM_INS_VDUP = 294
ARM_INS_VEOR = 295
ARM_INS_VEXT = 296
ARM_INS_VFMA = 297
ARM_INS_VFMS = 298
ARM_INS_VFNMA = 299
ARM_INS_VFNMS = 300
ARM_INS_VHADD = 301
ARM_INS_VHSUB = 302
ARM_INS_VLD1 = 303
ARM_INS_VLD2 = 304
ARM_INS_VLD3 = 305
ARM_INS_VLD4 = 306
ARM_INS_VLDMDB = 307
ARM_INS_VLDMIA = 308
ARM_INS_VLDR = 309
ARM_INS_VMAXNM = 310
ARM_INS_VMAX = 311
ARM_INS_VMINNM = 312
ARM_INS_VMIN = 313
ARM_INS_VMLA = 314
ARM_INS_VMLAL = 315
ARM_INS_VMLS = 316
ARM_INS_VMLSL = 317
ARM_INS_VMOVL = 318
ARM_INS_VMOVN = 319
ARM_INS_VMSR = 320
ARM_INS_VMUL = 321
ARM_INS_VMULL = 322
ARM_INS_VMVN = 323
ARM_INS_VNEG = 324
ARM_INS_VNMLA = 325
ARM_INS_VNMLS = 326
ARM_INS_VNMUL = 327
ARM_INS_VORN = 328
ARM_INS_VORR = 329
ARM_INS_VPADAL = 330
ARM_INS_VPADDL = 331
ARM_INS_VPADD = 332
ARM_INS_VPMAX = 333
ARM_INS_VPMIN = 334
ARM_INS_VQABS = 335
ARM_INS_VQADD = 336
ARM_INS_VQDMLAL = 337
ARM_INS_VQDMLSL = 338
ARM_INS_VQDMULH = 339
ARM_INS_VQDMULL = 340
ARM_INS_VQMOVUN = 341
ARM_INS_VQMOVN = 342
ARM_INS_VQNEG = 343
ARM_INS_VQRDMULH = 344
ARM_INS_VQRSHL = 345
ARM_INS_VQRSHRN = 346
ARM_INS_VQRSHRUN = 347
ARM_INS_VQSHL = 348
ARM_INS_VQSHLU = 349
ARM_INS_VQSHRN = 350
ARM_INS_VQSHRUN = 351
ARM_INS_VQSUB = 352
ARM_INS_VRADDHN = 353
ARM_INS_VRECPE = 354
ARM_INS_VRECPS = 355
ARM_INS_VREV16 = 356
ARM_INS_VREV32 = 357
ARM_INS_VREV64 = 358
ARM_INS_VRHADD = 359
ARM_INS_VRINTA = 360
ARM_INS_VRINTM = 361
ARM_INS_VRINTN = 362
ARM_INS_VRINTP = 363
ARM_INS_VRINTR = 364
ARM_INS_VRINTX = 365
ARM_INS_VRINTZ = 366
ARM_INS_VRSHL = 367
ARM_INS_VRSHRN = 368
ARM_INS_VRSHR = 369
ARM_INS_VRSQRTE = 370
ARM_INS_VRSQRTS = 371
ARM_INS_VRSRA = 372
ARM_INS_VRSUBHN = 373
ARM_INS_VSELEQ = 374
ARM_INS_VSELGE = 375
ARM_INS_VSELGT = 376
ARM_INS_VSELVS = 377
ARM_INS_VSHLL = 378
ARM_INS_VSHL = 379
ARM_INS_VSHRN = 380
ARM_INS_VSHR = 381
ARM_INS_VSLI = 382
ARM_INS_VSQRT = 383
ARM_INS_VSRA = 384
ARM_INS_VSRI = 385
ARM_INS_VST1 = 386
ARM_INS_VST2 = 387
ARM_INS_VST3 = 388
ARM_INS_VST4 = 389
ARM_INS_VSTMDB = 390
ARM_INS_VSTMIA = 391
ARM_INS_VSTR = 392
ARM_INS_VSUB = 393
ARM_INS_VSUBHN = 394
ARM_INS_VSUBL = 395
ARM_INS_VSUBW = 396
ARM_INS_VSWP = 397
ARM_INS_VTBL = 398
ARM_INS_VTBX = 399
ARM_INS_VCVTR = 400
ARM_INS_VTRN = 401
ARM_INS_VTST = 402
ARM_INS_VUZP = 403
ARM_INS_VZIP = 404
ARM_INS_ADDW = 405
ARM_INS_ASR = 406
ARM_INS_DCPS1 = 407
ARM_INS_DCPS2 = 408
ARM_INS_DCPS3 = 409
ARM_INS_IT = 410
ARM_INS_LSL = 411
ARM_INS_LSR = 412
ARM_INS_ASRS = 413
ARM_INS_LSRS = 414
ARM_INS_ORN = 415
ARM_INS_ROR = 416
ARM_INS_RRX = 417
ARM_INS_SUBS = 418
ARM_INS_SUBW = 419
ARM_INS_TBB = 420
ARM_INS_TBH = 421
ARM_INS_CBNZ = 422
ARM_INS_CBZ = 423
ARM_INS_MOVS = 424
ARM_INS_POP = 425
ARM_INS_PUSH = 426
ARM_INS_MAX = 427
# Group of ARM instructions

1
include/arm.h
View File

@ -458,6 +458,7 @@ typedef enum arm_insn {
ARM_INS_UADD8,
ARM_INS_UASX,
ARM_INS_UBFX,
ARM_INS_UDF,
ARM_INS_UDIV,
ARM_INS_UHADD16,
ARM_INS_UHADD8,