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capstone
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done fix

This commit is contained in:
hardtobelieve 2019-02-09 22:41:56 -08:00
parent 3a106cfed9
commit b6a52359f4
18 changed files with 248 additions and 248 deletions
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4
suite/cstest/include/capstone_test.h
View File

@ -53,8 +53,8 @@ extern char *(*function)(csh *, cs_mode, cs_insn*);
int getIndex(double_dict d[], unsigned size, const char *str);
int getValue(single_dict d[], unsigned size, const char *str);
void test_single(csh *handle, char *line);
void test_single_issues(csh *handle, cs_mode mode, char *line, int detail);
void test_single_MC(csh *handle, char *line);
void test_single_issue(csh *handle, cs_mode mode, char *line, int detail);
int setFunction(int arch);
#endif /* CAPSTONE_TEST_H */

2
suite/cstest/include/helper.h
View File

@ -12,7 +12,7 @@ char **split(char *str, char *delim, int *size);
void print_strs(char **list_str, int size);
char *readfile(const char *filename);
void free_strs(char **list_str, int size);
void addStr(char **src, const char *format, ...);
void add_str(char **src, const char *format, ...);
void replaceHex(char **src);
void listdir(const char *name, char ***files, int *num_files);
const char *get_filename_ext(const char *filename);

62
suite/cstest/src/arm64_detail.c
View File

@ -19,7 +19,7 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
arm64 = &(ins->detail->arm64);
if (arm64->op_count)
addStr(&result, " ; op_count: %u", arm64->op_count);
add_str(&result, " ; op_count: %u", arm64->op_count);
for (i = 0; i < arm64->op_count; i++) {
cs_arm64_op *op = &(arm64->operands[i]);
@ -27,49 +27,49 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case ARM64_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case ARM64_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
break;
case ARM64_OP_FP:
#if defined(_KERNEL_MODE)
// Issue #681: Windows kernel does not support formatting float point
addStr(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
add_str(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
#else
addStr(&result, " ; operands[%u].type: FP = %f", i, op->fp);
add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp);
#endif
break;
case ARM64_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != ARM64_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
if (op->mem.index != ARM64_REG_INVALID)
addStr(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
break;
case ARM64_OP_CIMM:
addStr(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm);
add_str(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm);
break;
case ARM64_OP_REG_MRS:
addStr(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg);
add_str(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg);
break;
case ARM64_OP_REG_MSR:
addStr(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg);
add_str(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg);
break;
case ARM64_OP_PSTATE:
addStr(&result, " ; operands[%u].type: PSTATE = 0x%x", i, op->pstate);
add_str(&result, " ; operands[%u].type: PSTATE = 0x%x", i, op->pstate);
break;
case ARM64_OP_SYS:
addStr(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys);
add_str(&result, " ; operands[%u].type: SYS = 0x%x", i, op->sys);
break;
case ARM64_OP_PREFETCH:
addStr(&result, " ; operands[%u].type: PREFETCH = 0x%x", i, op->prefetch);
add_str(&result, " ; operands[%u].type: PREFETCH = 0x%x", i, op->prefetch);
break;
case ARM64_OP_BARRIER:
addStr(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier);
add_str(&result, " ; operands[%u].type: BARRIER = 0x%x", i, op->barrier);
break;
}
@ -78,55 +78,55 @@ char *get_detail_arm64(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case CS_AC_READ:
addStr(&result, " ; operands[%u].access: READ", i);
add_str(&result, " ; operands[%u].access: READ", i);
break;
case CS_AC_WRITE:
addStr(&result, " ; operands[%u].access: WRITE", i);
add_str(&result, " ; operands[%u].access: WRITE", i);
break;
case CS_AC_READ | CS_AC_WRITE:
addStr(&result, " ; operands[%u].access: READ | WRITE", i);
add_str(&result, " ; operands[%u].access: READ | WRITE", i);
break;
}
if (op->shift.type != ARM64_SFT_INVALID &&
op->shift.value)
addStr(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value);
add_str(&result, " ; Shift: type = %u, value = %u", op->shift.type, op->shift.value);
if (op->ext != ARM64_EXT_INVALID)
addStr(&result, " ; Ext: %u", op->ext);
add_str(&result, " ; Ext: %u", op->ext);
if (op->vas != ARM64_VAS_INVALID)
addStr(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas);
add_str(&result, " ; Vector Arrangement Specifier: 0x%x", op->vas);
if (op->vess != ARM64_VESS_INVALID)
addStr(&result, " ; Vector Element Size Specifier: %u", op->vess);
add_str(&result, " ; Vector Element Size Specifier: %u", op->vess);
if (op->vector_index != -1)
addStr(&result, " ; Vector Index: %u", op->vector_index);
add_str(&result, " ; Vector Index: %u", op->vector_index);
}
if (arm64->update_flags)
addStr(&result, " ; Update-flags: True");
add_str(&result, " ; Update-flags: True");
if (arm64->writeback)
addStr(&result, " ; Write-back: True");
add_str(&result, " ; Write-back: True");
if (arm64->cc)
addStr(&result, " ; Code-condition: %u", arm64->cc);
add_str(&result, " ; Code-condition: %u", arm64->cc);
// Print out all registers accessed by this instruction (either implicit or explicit)
if (!cs_regs_access(*handle, ins, regs_read, &regs_read_count, regs_write, &regs_write_count)) {
if (regs_read_count) {
addStr(&result, " ; Registers read:");
add_str(&result, " ; Registers read:");
for(i = 0; i < regs_read_count; i++) {
addStr(&result, " %s", cs_reg_name(*handle, regs_read[i]));
add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
}
}
if (regs_write_count) {
addStr(&result, " ; Registers modified:");
add_str(&result, " ; Registers modified:");
for(i = 0; i < regs_write_count; i++) {
addStr(&result, " %s", cs_reg_name(*handle, regs_write[i]));
add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));
}
}
}

72
suite/cstest/src/arm_detail.c
View File

@ -17,7 +17,7 @@ char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins)
arm = &(ins->detail->arm);
if (arm->op_count)
addStr(&result, " ; op_count: %u", arm->op_count);
add_str(&result, " ; op_count: %u", arm->op_count);
for (i = 0; i < arm->op_count; i++) {
cs_arm_op *op = &(arm->operands[i]);
@ -25,122 +25,122 @@ char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case ARM_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case ARM_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
break;
case ARM_OP_FP:
#if defined(_KERNEL_MODE)
// Issue #681: Windows kernel does not support formatting float point
addStr(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
add_str(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
#else
addStr(&result, " ; operands[%u].type: FP = %f", i, op->fp);
add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp);
#endif
break;
case ARM_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != ARM_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
if (op->mem.index != ARM_REG_INVALID)
addStr(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
if (op->mem.scale != 1)
addStr(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale);
add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale);
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
if (op->mem.lshift != 0)
addStr(&result, " ; operands[%u].mem.lshift: 0x%x", i, op->mem.lshift);
add_str(&result, " ; operands[%u].mem.lshift: 0x%x", i, op->mem.lshift);
break;
case ARM_OP_PIMM:
addStr(&result, " ; operands[%u].type: P-IMM = %u", i, op->imm);
add_str(&result, " ; operands[%u].type: P-IMM = %u", i, op->imm);
break;
case ARM_OP_CIMM:
addStr(&result, " ; operands[%u].type: C-IMM = %u", i, op->imm);
add_str(&result, " ; operands[%u].type: C-IMM = %u", i, op->imm);
break;
case ARM_OP_SETEND:
addStr(&result, " ; operands[%u].type: SETEND = %s", i, op->setend == ARM_SETEND_BE? "be" : "le");
add_str(&result, " ; operands[%u].type: SETEND = %s", i, op->setend == ARM_SETEND_BE? "be" : "le");
break;
case ARM_OP_SYSREG:
addStr(&result, " ; operands[%u].type: SYSREG = %u", i, op->reg);
add_str(&result, " ; operands[%u].type: SYSREG = %u", i, op->reg);
break;
}
if (op->neon_lane != -1) {
addStr(&result, " ; operands[%u].neon_lane = %u", i, op->neon_lane);
add_str(&result, " ; operands[%u].neon_lane = %u", i, op->neon_lane);
}
switch(op->access) {
default:
break;
case CS_AC_READ:
addStr(&result, " ; operands[%u].access: READ", i);
add_str(&result, " ; operands[%u].access: READ", i);
break;
case CS_AC_WRITE:
addStr(&result, " ; operands[%u].access: WRITE", i);
add_str(&result, " ; operands[%u].access: WRITE", i);
break;
case CS_AC_READ | CS_AC_WRITE:
addStr(&result, " ; operands[%u].access: READ | WRITE", i);
add_str(&result, " ; operands[%u].access: READ | WRITE", i);
break;
}
if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
if (op->shift.type < ARM_SFT_ASR_REG)
// shift with constant value
addStr(&result, " ; Shift: %u = %u", op->shift.type, op->shift.value);
add_str(&result, " ; Shift: %u = %u", op->shift.type, op->shift.value);
else
// shift with register
addStr(&result, " ; Shift: %u = %s", op->shift.type, cs_reg_name(*handle, op->shift.value));
add_str(&result, " ; Shift: %u = %s", op->shift.type, cs_reg_name(*handle, op->shift.value));
}
if (op->vector_index != -1) {
addStr(&result, " ; operands[%u].vector_index = %u", i, op->vector_index);
add_str(&result, " ; operands[%u].vector_index = %u", i, op->vector_index);
}
if (op->subtracted)
addStr(&result, " ; Subtracted: True");
add_str(&result, " ; Subtracted: True");
}
if (arm->cc != ARM_CC_AL && arm->cc != ARM_CC_INVALID)
addStr(&result, " ; Code condition: %u", arm->cc);
add_str(&result, " ; Code condition: %u", arm->cc);
if (arm->update_flags)
addStr(&result, " ; Update-flags: True");
add_str(&result, " ; Update-flags: True");
if (arm->writeback)
addStr(&result, " ; Write-back: True");
add_str(&result, " ; Write-back: True");
if (arm->cps_mode)
addStr(&result, " ; CPSI-mode: %u", arm->cps_mode);
add_str(&result, " ; CPSI-mode: %u", arm->cps_mode);
if (arm->cps_flag)
addStr(&result, " ; CPSI-flag: %u", arm->cps_flag);
add_str(&result, " ; CPSI-flag: %u", arm->cps_flag);
if (arm->vector_data)
addStr(&result, " ; Vector-data: %u", arm->vector_data);
add_str(&result, " ; Vector-data: %u", arm->vector_data);
if (arm->vector_size)
addStr(&result, " ; Vector-size: %u", arm->vector_size);
add_str(&result, " ; Vector-size: %u", arm->vector_size);
if (arm->usermode)
addStr(&result, " ; User-mode: True");
add_str(&result, " ; User-mode: True");
if (arm->mem_barrier)
addStr(&result, " ; Memory-barrier: %u", arm->mem_barrier);
add_str(&result, " ; Memory-barrier: %u", arm->mem_barrier);
// Print out all registers accessed by this instruction (either implicit or explicit)
if (!cs_regs_access(*handle, ins, regs_read, &regs_read_count, regs_write, &regs_write_count)) {
if (regs_read_count) {
addStr(&result, " ; Registers read:");
add_str(&result, " ; Registers read:");
for(i = 0; i < regs_read_count; i++) {
addStr(&result, " %s", cs_reg_name(*handle, regs_read[i]));
add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
}
}
if (regs_write_count) {
addStr(&result, " ; Registers modified:");
add_str(&result, " ; Registers modified:");
for(i = 0; i < regs_write_count; i++) {
addStr(&result, " %s", cs_reg_name(*handle, regs_write[i]));
add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));
}
}
}

12
suite/cstest/src/capstone_test.c
View File

@ -96,7 +96,7 @@ int triple_compare(const char *src1, const char *src2, const char *des)
return 1;
}
void test_single(csh *handle, char *line)
void test_single_MC(csh *handle, char *line)
{
char **list_part, **list_byte, **list_data;
int size_part, size_byte, size_data, size_insn;
@ -243,23 +243,23 @@ void test_single_issue(csh *handle, cs_mode mode, char *line, int detail)
tmp[strlen(insn[i].mnemonic)] = ' ';
strcpy(tmp + strlen(insn[i].mnemonic) + 1, insn[i].op_str);
}
addStr(&cs_result, tmp);
add_str(&cs_result, tmp);
/*
if (i < count - 1)
addStr(&cs_result, ";");
add_str(&cs_result, ";");
*/
free(tmp);
}
if (detail == 1) {
tmp = (*function)(handle, mode, insn);
addStr(&cs_result, tmp);
add_str(&cs_result, tmp);
free(tmp);
if (insn->detail->groups_count) {
addStr(&cs_result, " ; Groups: ");
add_str(&cs_result, " ; Groups: ");
for (j = 0; j < insn->detail->groups_count; j++) {
addStr(&cs_result, "%s ", cs_group_name(*handle, insn->detail->groups[j]));
add_str(&cs_result, "%s ", cs_group_name(*handle, insn->detail->groups[j]));
}
}
}

6
suite/cstest/src/evm_detail.c
View File

@ -15,13 +15,13 @@ char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins)
evm = &(ins->detail->evm);
if (evm->pop)
addStr(&result, " ; Pop: %u", evm->pop);
add_str(&result, " ; Pop: %u", evm->pop);
if (evm->push)
addStr(&result, " ; Push: %u", evm->push);
add_str(&result, " ; Push: %u", evm->push);
if (evm->fee)
addStr(&result, " ; Gas fee: %u", evm->fee);
add_str(&result, " ; Gas fee: %u", evm->fee);
return result;
}

6
suite/cstest/src/helper.c
View File

@ -78,7 +78,7 @@ char *readfile(const char *filename)
return result;
}
void addStr(char **src, const char *format, ...)
void add_str(char **src, const char *format, ...)
{
char *tmp;
size_t len1, len2;
@ -121,10 +121,10 @@ void replaceHex(char **src)
found++;
}
addStr(&result, "%s%llu", tmp, value);
add_str(&result, "%s%llu", tmp, value);
tmp = found;
}
addStr(&result, "%s", tmp);
add_str(&result, "%s", tmp);
free(*src);
*src = result;
}

44
suite/cstest/src/m680x_detail.c
View File

@ -9,24 +9,24 @@ void print_read_write_regs(char *result, csh *handle, cs_detail *detail)
int i;
if (detail->regs_read_count > 0) {
addStr(&result, "\treading from regs: ");
add_str(&result, "\treading from regs: ");
for (i = 0; i < detail->regs_read_count; ++i) {
if (i > 0)
addStr(&result, ", ");
add_str(&result, ", ");
addStr(&result, "%s", cs_reg_name(*handle, detail->regs_read[i]));
add_str(&result, "%s", cs_reg_name(*handle, detail->regs_read[i]));
}
}
if (detail->regs_write_count > 0) {
addStr(&result, "\twriting to regs: ");
add_str(&result, "\twriting to regs: ");
for (i = 0; i < detail->regs_write_count; ++i) {
if (i > 0)
addStr(&result, ", ");
add_str(&result, ", ");
addStr(&result, "%s", cs_reg_name(*handle, detail->regs_write[i]));
add_str(&result, "%s", cs_reg_name(*handle, detail->regs_write[i]));
}
}
}
@ -49,7 +49,7 @@ char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *insn)
m680x = &detail->m680x;
if (m680x->op_count)
addStr(&result, " ; op_count: %u", m680x->op_count);
add_str(&result, " ; op_count: %u", m680x->op_count);
for (i = 0; i < m680x->op_count; i++) {
cs_m680x_op *op = &(m680x->operands[i]);
@ -67,47 +67,47 @@ char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *insn)
M680X_SECOND_OP_IN_MNEM))
comment = " (in mnemonic)";
addStr(&result, " ; operands[%u].type: REGISTER = %s%s", i, cs_reg_name(*handle, op->reg), comment);
add_str(&result, " ; operands[%u].type: REGISTER = %s%s", i, cs_reg_name(*handle, op->reg), comment);
break;
case M680X_OP_CONSTANT:
addStr(&result, " ; operands[%u].type: CONSTANT = %u", i, op->const_val);
add_str(&result, " ; operands[%u].type: CONSTANT = %u", i, op->const_val);
break;
case M680X_OP_IMMEDIATE:
addStr(&result, " ; operands[%u].type: IMMEDIATE = #%d", i, op->imm);
add_str(&result, " ; operands[%u].type: IMMEDIATE = #%d", i, op->imm);
break;
case M680X_OP_DIRECT:
addStr(&result, " ; operands[%u].type: DIRECT = 0x%02X", i, op->direct_addr);
add_str(&result, " ; operands[%u].type: DIRECT = 0x%02X", i, op->direct_addr);
break;
case M680X_OP_EXTENDED:
addStr(&result, " ; operands[%u].type: EXTENDED %s = 0x%04X", i, op->ext.indirect ? "INDIRECT" : "", op->ext.address);
add_str(&result, " ; operands[%u].type: EXTENDED %s = 0x%04X", i, op->ext.indirect ? "INDIRECT" : "", op->ext.address);
break;
case M680X_OP_RELATIVE:
addStr(&result, " ; operands[%u].type: RELATIVE = 0x%04X", i, op->rel.address);
add_str(&result, " ; operands[%u].type: RELATIVE = 0x%04X", i, op->rel.address);
break;
case M680X_OP_INDEXED:
addStr(&result, " ; operands[%u].type: INDEXED%s", i, (op->idx.flags & M680X_IDX_INDIRECT) ? " INDIRECT" : "");
add_str(&result, " ; operands[%u].type: INDEXED%s", i, (op->idx.flags & M680X_IDX_INDIRECT) ? " INDIRECT" : "");
if (op->idx.base_reg != M680X_REG_INVALID)
addStr(&result, " ; base register: %s", cs_reg_name(*handle, op->idx.base_reg));
add_str(&result, " ; base register: %s", cs_reg_name(*handle, op->idx.base_reg));
if (op->idx.offset_reg != M680X_REG_INVALID)
addStr(&result, " ; offset register: %s", cs_reg_name(*handle, op->idx.offset_reg));
add_str(&result, " ; offset register: %s", cs_reg_name(*handle, op->idx.offset_reg));
if ((op->idx.offset_bits != 0) &&
(op->idx.offset_reg == M680X_REG_INVALID) &&
!op->idx.inc_dec) {
addStr(&result, " ; offset: %d", op->idx.offset);
add_str(&result, " ; offset: %d", op->idx.offset);
if (op->idx.base_reg == M680X_REG_PC)
addStr(&result, " ; offset address: 0x%X", op->idx.offset_addr);
add_str(&result, " ; offset address: 0x%X", op->idx.offset_addr);
addStr(&result, " ; offset bits: %u", op->idx.offset_bits);
add_str(&result, " ; offset bits: %u", op->idx.offset_bits);
}
if (op->idx.inc_dec) {
@ -116,17 +116,17 @@ char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *insn)
const char *inc_dec = (op->idx.inc_dec > 0) ?
"increment" : "decrement";
addStr(&result, " ; %s %s: %d", post_pre, inc_dec, abs(op->idx.inc_dec));
add_str(&result, " ; %s %s: %d", post_pre, inc_dec, abs(op->idx.inc_dec));
}
break;
}
if (op->size != 0)
addStr(&result, " ; size: %u", op->size);
add_str(&result, " ; size: %u", op->size);
if (op->access != CS_AC_INVALID)
addStr(&result, " ; access: %s", s_access[op->access]);
add_str(&result, " ; access: %s", s_access[op->access]);
}
print_read_write_regs(result, handle, detail);

34
suite/cstest/src/m68k_detail.c
View File

@ -37,13 +37,13 @@ static void print_read_write_regs(char *result, cs_detail* detail, csh *handle)
for (i = 0; i < detail->regs_read_count; ++i) {
uint16_t reg_id = detail->regs_read[i];
const char* reg_name = cs_reg_name(*handle, reg_id);
addStr(&result, " ; reading from reg: %s", reg_name);
add_str(&result, " ; reading from reg: %s", reg_name);
}
for (i = 0; i < detail->regs_write_count; ++i) {
uint16_t reg_id = detail->regs_write[i];
const char* reg_name = cs_reg_name(*handle, reg_id);
addStr(&result, " ; writing to reg: %s", reg_name);
add_str(&result, " ; writing to reg: %s", reg_name);
}
}
@ -65,11 +65,11 @@ char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins)
detail = ins->detail;
m68k = &detail->m68k;
if (m68k->op_count)
addStr(&result, " ; op_count: %u", m68k->op_count);
add_str(&result, " ; op_count: %u", m68k->op_count);
print_read_write_regs(result, detail, handle);
addStr(&result, " ; groups_count: %u", detail->groups_count);
add_str(&result, " ; groups_count: %u", detail->groups_count);
for (i = 0; i < m68k->op_count; i++) {
cs_m68k_op* op = &(m68k->operands[i]);
@ -78,33 +78,33 @@ char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case M68K_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case M68K_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%x", i, (int)op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, (int)op->imm);
break;
case M68K_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base_reg != M68K_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base_reg));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base_reg));
if (op->mem.index_reg != M68K_REG_INVALID) {
addStr(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index_reg));
addStr(&result, " ; operands[%u].mem.index: size = %c", i, op->mem.index_size ? 'l' : 'w');
add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index_reg));
add_str(&result, " ; operands[%u].mem.index: size = %c", i, op->mem.index_size ? 'l' : 'w');
}
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
if (op->mem.scale != 0)
addStr(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale);
add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale);
addStr(&result, " ; address mode: %s", s_addressing_modes[op->address_mode]);
add_str(&result, " ; address mode: %s", s_addressing_modes[op->address_mode]);
break;
case M68K_OP_FP_SINGLE:
addStr(&result, " ; operands[%u].type: FP_SINGLE", i);
addStr(&result, " ; operands[%u].simm: %f", i, op->simm);
add_str(&result, " ; operands[%u].type: FP_SINGLE", i);
add_str(&result, " ; operands[%u].simm: %f", i, op->simm);
break;
case M68K_OP_FP_DOUBLE:
addStr(&result, " ; operands[%u].type: FP_DOUBLE", i);
addStr(&result, " ; operands[%u].dimm: %lf", i, op->dimm);
add_str(&result, " ; operands[%u].type: FP_DOUBLE", i);
add_str(&result, " ; operands[%u].dimm: %lf", i, op->dimm);
break;
}
}

2
suite/cstest/src/main.c
View File

@ -51,7 +51,7 @@ static int setup_MC(void **state)
static void test_MC(void **state)
{
test_single((csh *)*state, list_lines[counter]);
test_single_MC((csh *)*state, list_lines[counter]);
return;
}

12
suite/cstest/src/mips_detail.c
View File

@ -14,7 +14,7 @@ char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins)
mips = &(ins->detail->mips);
if (mips->op_count)
addStr(&result, " ; op_count: %u", mips->op_count);
add_str(&result, " ; op_count: %u", mips->op_count);
for (i = 0; i < mips->op_count; i++) {
cs_mips_op *op = &(mips->operands[i]);
@ -22,17 +22,17 @@ char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case MIPS_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case MIPS_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
break;
case MIPS_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != MIPS_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
break;
}

12
suite/cstest/src/mos65xx_detail.c
View File

@ -50,11 +50,11 @@ char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins)
return result;
mos65xx = &(ins->detail->mos65xx);
addStr(&result, " ; address mode: %s", get_am_name(mos65xx->am));
addStr(&result, " ; modifies flags: %s", mos65xx->modifies_flags ? "true": "false");
add_str(&result, " ; address mode: %s", get_am_name(mos65xx->am));
add_str(&result, " ; modifies flags: %s", mos65xx->modifies_flags ? "true": "false");
if (mos65xx->op_count)
addStr(&result, " ; op_count: %u", mos65xx->op_count);
add_str(&result, " ; op_count: %u", mos65xx->op_count);
for (i = 0; i < mos65xx->op_count; i++) {
cs_mos65xx_op *op = &(mos65xx->operands[i]);
@ -62,13 +62,13 @@ char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case MOS65XX_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case MOS65XX_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
break;
case MOS65XX_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM = 0x%x", i, op->mem);
add_str(&result, " ; operands[%u].type: MEM = 0x%x", i, op->mem);
break;
}
}

26
suite/cstest/src/ppc_detail.c
View File

@ -44,7 +44,7 @@ char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins)
ppc = &(ins->detail->ppc);
if (ppc->op_count)
addStr(&result, " ; op_count: %u", ppc->op_count);
add_str(&result, " ; op_count: %u", ppc->op_count);
for (i = 0; i < ppc->op_count; i++) {
cs_ppc_op *op = &(ppc->operands[i]);
@ -52,36 +52,36 @@ char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case PPC_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case PPC_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%"PRIx64"", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%"PRIx64"", i, op->imm);
break;
case PPC_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != PPC_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
break;
case PPC_OP_CRX:
addStr(&result, " ; operands[%u].type: CRX", i);
addStr(&result, " ; operands[%u].crx.scale: %d", i, op->crx.scale);
addStr(&result, " ; operands[%u].crx.reg: %s", i, cs_reg_name(*handle, op->crx.reg));
addStr(&result, " ; operands[%u].crx.cond: %s", i, get_bc_name(op->crx.cond));
add_str(&result, " ; operands[%u].type: CRX", i);
add_str(&result, " ; operands[%u].crx.scale: %d", i, op->crx.scale);
add_str(&result, " ; operands[%u].crx.reg: %s", i, cs_reg_name(*handle, op->crx.reg));
add_str(&result, " ; operands[%u].crx.cond: %s", i, get_bc_name(op->crx.cond));
break;
}
}
if (ppc->bc != 0)
addStr(&result, " ; Branch code: %u", ppc->bc);
add_str(&result, " ; Branch code: %u", ppc->bc);
if (ppc->bh != 0)
addStr(&result, " ; Branch hint: %u", ppc->bh);
add_str(&result, " ; Branch hint: %u", ppc->bh);
if (ppc->update_cr0)
addStr(&result, " ; Update-CR0: True");
add_str(&result, " ; Update-CR0: True");
return result;
}

18
suite/cstest/src/sparc_detail.c
View File

@ -15,7 +15,7 @@ char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins)
sparc = &(ins->detail->sparc);
if (sparc->op_count)
addStr(&result, " ; op_count: %u", sparc->op_count);
add_str(&result, " ; op_count: %u", sparc->op_count);
for (i = 0; i < sparc->op_count; i++) {
cs_sparc_op *op = &(sparc->operands[i]);
@ -23,29 +23,29 @@ char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case SPARC_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case SPARC_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
break;
case SPARC_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != X86_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
if (op->mem.index != X86_REG_INVALID)
addStr(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
break;
}
}
if (sparc->cc != 0)
addStr(&result, " ; Code condition: %u", sparc->cc);
add_str(&result, " ; Code condition: %u", sparc->cc);
if (sparc->hint != 0)
addStr(&result, " ; Hint code: %u", sparc->hint);
add_str(&result, " ; Hint code: %u", sparc->hint);
return result;
}

20
suite/cstest/src/systemz_detail.c
View File

@ -15,7 +15,7 @@ char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins)
sysz = &(ins->detail->sysz);
if (sysz->op_count)
addStr(&result, " ; op_count: %u", sysz->op_count);
add_str(&result, " ; op_count: %u", sysz->op_count);
for (i = 0; i < sysz->op_count; i++) {
cs_sysz_op *op = &(sysz->operands[i]);
@ -23,31 +23,31 @@ char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case SYSZ_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case SYSZ_OP_ACREG:
addStr(&result, " ; operands[%u].type: ACREG = %u", i, op->reg);
add_str(&result, " ; operands[%u].type: ACREG = %u", i, op->reg);
break;
case SYSZ_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
break;
case SYSZ_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != SYSZ_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
if (op->mem.index != SYSZ_REG_INVALID)
addStr(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
if (op->mem.length != 0)
addStr(&result, " ; operands[%u].mem.length: 0x%" PRIx64 "", i, op->mem.length);
add_str(&result, " ; operands[%u].mem.length: 0x%" PRIx64 "", i, op->mem.length);
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
break;
}
}
if (sysz->cc != 0)
addStr(&result, " ; Code condition: %u", sysz->cc);
add_str(&result, " ; Code condition: %u", sysz->cc);
return result;
}

68
suite/cstest/src/tms320c64x_detail.c
View File

@ -15,7 +15,7 @@ char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins)
tms320c64x = &(ins->detail->tms320c64x);
if (tms320c64x->op_count)
addStr(&result, " ; op_count: %u", tms320c64x->op_count);
add_str(&result, " ; op_count: %u", tms320c64x->op_count);
for (i = 0; i < tms320c64x->op_count; i++) {
cs_tms320c64x_op *op = &(tms320c64x->operands[i]);
@ -23,81 +23,81 @@ char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case TMS320C64X_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case TMS320C64X_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
break;
case TMS320C64X_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != TMS320C64X_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
addStr(&result, " ; operands[%u].mem.disptype: ", i);
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.disptype: ", i);
if(op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) {
addStr(&result, "Invalid");
addStr(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp);
add_str(&result, "Invalid");
add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp);
}
if(op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) {
addStr(&result, "Constant");
addStr(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp);
add_str(&result, "Constant");
add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp);
}
if(op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) {
addStr(&result, "Register");
addStr(&result, " ; operands[%u].mem.disp: %s", i, cs_reg_name(*handle, op->mem.disp));
add_str(&result, "Register");
add_str(&result, " ; operands[%u].mem.disp: %s", i, cs_reg_name(*handle, op->mem.disp));
}
addStr(&result, " ; operands[%u].mem.unit: %u", i, op->mem.unit);
addStr(&result, " ; operands[%u].mem.direction: ", i);
add_str(&result, " ; operands[%u].mem.unit: %u", i, op->mem.unit);
add_str(&result, " ; operands[%u].mem.direction: ", i);
if(op->mem.direction == TMS320C64X_MEM_DIR_INVALID)
addStr(&result, "Invalid");
add_str(&result, "Invalid");
if(op->mem.direction == TMS320C64X_MEM_DIR_FW)
addStr(&result, "Forward");
add_str(&result, "Forward");
if(op->mem.direction == TMS320C64X_MEM_DIR_BW)
addStr(&result, "Backward");
addStr(&result, " ; operands[%u].mem.modify: ", i);
add_str(&result, "Backward");
add_str(&result, " ; operands[%u].mem.modify: ", i);
if(op->mem.modify == TMS320C64X_MEM_MOD_INVALID)
addStr(&result, "Invalid");
add_str(&result, "Invalid");
if(op->mem.modify == TMS320C64X_MEM_MOD_NO)
addStr(&result, "No");
add_str(&result, "No");
if(op->mem.modify == TMS320C64X_MEM_MOD_PRE)
addStr(&result, "Pre");
add_str(&result, "Pre");
if(op->mem.modify == TMS320C64X_MEM_MOD_POST)
addStr(&result, "Post");
addStr(&result, " ; operands[%u].mem.scaled: %u", i, op->mem.scaled);
add_str(&result, "Post");
add_str(&result, " ; operands[%u].mem.scaled: %u", i, op->mem.scaled);
break;
case TMS320C64X_OP_REGPAIR:
addStr(&result, " ; operands[%u].type: REGPAIR = %s:%s", i, cs_reg_name(*handle, op->reg + 1), cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REGPAIR = %s:%s", i, cs_reg_name(*handle, op->reg + 1), cs_reg_name(*handle, op->reg));
break;
}
}
addStr(&result, " ; Functional unit: ");
add_str(&result, " ; Functional unit: ");
switch(tms320c64x->funit.unit) {
case TMS320C64X_FUNIT_D:
addStr(&result, "D%u", tms320c64x->funit.side);
add_str(&result, "D%u", tms320c64x->funit.side);
break;
case TMS320C64X_FUNIT_L:
addStr(&result, "L%u", tms320c64x->funit.side);
add_str(&result, "L%u", tms320c64x->funit.side);
break;
case TMS320C64X_FUNIT_M:
addStr(&result, "M%u", tms320c64x->funit.side);
add_str(&result, "M%u", tms320c64x->funit.side);
break;
case TMS320C64X_FUNIT_S:
addStr(&result, "S%u", tms320c64x->funit.side);
add_str(&result, "S%u", tms320c64x->funit.side);
break;
case TMS320C64X_FUNIT_NO:
addStr(&result, "No Functional Unit");
add_str(&result, "No Functional Unit");
break;
default:
addStr(&result, "Unknown (Unit %u, Side %u)", tms320c64x->funit.unit, tms320c64x->funit.side);
add_str(&result, "Unknown (Unit %u, Side %u)", tms320c64x->funit.unit, tms320c64x->funit.side);
break;
}
if(tms320c64x->funit.crosspath == 1)
addStr(&result, " ; Crosspath: 1");
add_str(&result, " ; Crosspath: 1");
if(tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
addStr(&result, " ; Condition: [%c%s]", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(*handle, tms320c64x->condition.reg));
addStr(&result, " ; Parallel: %s", (tms320c64x->parallel == 1) ? "true" : "false");
add_str(&result, " ; Condition: [%c%s]", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(*handle, tms320c64x->condition.reg));
add_str(&result, " ; Parallel: %s", (tms320c64x->parallel == 1) ? "true" : "false");
return result;
}

80
suite/cstest/src/x86_detail.c
View File

@ -4,9 +4,9 @@ void print_string_hex(char **result, const char *comment, unsigned char *str, si
{
unsigned char *c;
addStr(result, "%s", comment);
add_str(result, "%s", comment);
for (c = str; c < str + len; c++) {
addStr(result, "0x%02x ", *c & 0xff);
add_str(result, "0x%02x ", *c & 0xff);
}
}
@ -200,59 +200,59 @@ char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins)
print_string_hex(&result, " ; Prefix:", x86->prefix, 4);
print_string_hex(&result, " ; Opcode:", x86->opcode, 4);
addStr(&result, " ; rex: 0x%x", x86->rex);
addStr(&result, " ; addr_size: %u", x86->addr_size);
addStr(&result, " ; modrm: 0x%x", x86->modrm);
addStr(&result, " ; disp: 0x%" PRIx64 "", x86->disp);
add_str(&result, " ; rex: 0x%x", x86->rex);
add_str(&result, " ; addr_size: %u", x86->addr_size);
add_str(&result, " ; modrm: 0x%x", x86->modrm);
add_str(&result, " ; disp: 0x%" PRIx64 "", x86->disp);
// SIB is not available in 16-bit mode
if ((mode & CS_MODE_16) == 0) {
addStr(&result, " ; sib: 0x%x", x86->sib);
add_str(&result, " ; sib: 0x%x", x86->sib);
if (x86->sib_base != X86_REG_INVALID)
addStr(&result, " ; sib_base: %s", cs_reg_name(*ud, x86->sib_base));
add_str(&result, " ; sib_base: %s", cs_reg_name(*ud, x86->sib_base));
if (x86->sib_index != X86_REG_INVALID)
addStr(&result, " ; sib_index: %s", cs_reg_name(*ud, x86->sib_index));
add_str(&result, " ; sib_index: %s", cs_reg_name(*ud, x86->sib_index));
if (x86->sib_scale != 0)
addStr(&result, " ; sib_scale: %d", x86->sib_scale);
add_str(&result, " ; sib_scale: %d", x86->sib_scale);
}
// XOP code condition
if (x86->xop_cc != X86_XOP_CC_INVALID) {
addStr(&result, " ; xop_cc: %u", x86->xop_cc);
add_str(&result, " ; xop_cc: %u", x86->xop_cc);
}
// SSE code condition
if (x86->sse_cc != X86_SSE_CC_INVALID) {
addStr(&result, " ; sse_cc: %u", x86->sse_cc);
add_str(&result, " ; sse_cc: %u", x86->sse_cc);
}
// AVX code condition
if (x86->avx_cc != X86_AVX_CC_INVALID) {
addStr(&result, " ; avx_cc: %u", x86->avx_cc);
add_str(&result, " ; avx_cc: %u", x86->avx_cc);
}
// AVX Suppress All Exception
if (x86->avx_sae) {
addStr(&result, " ; avx_sae: %u", x86->avx_sae);
add_str(&result, " ; avx_sae: %u", x86->avx_sae);
}
// AVX Rounding Mode
if (x86->avx_rm != X86_AVX_RM_INVALID) {
addStr(&result, " ; avx_rm: %u", x86->avx_rm);
add_str(&result, " ; avx_rm: %u", x86->avx_rm);
}
// Print out all immediate operands
count = cs_op_count(*ud, ins, X86_OP_IMM);
if (count > 0) {
addStr(&result, " ; imm_count: %u", count);
add_str(&result, " ; imm_count: %u", count);
for (i = 1; i < count + 1; i++) {
int index = cs_op_index(*ud, ins, X86_OP_IMM, i);
addStr(&result, " ; imms[%u]: 0x%" PRIx64 "", i, x86->operands[index].imm);
add_str(&result, " ; imms[%u]: 0x%" PRIx64 "", i, x86->operands[index].imm);
}
}
if (x86->op_count)
addStr(&result, " ; op_count: %u", x86->op_count);
add_str(&result, " ; op_count: %u", x86->op_count);
// Print out all operands
for (i = 0; i < x86->op_count; i++) {
@ -260,23 +260,23 @@ char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins)
switch((int)op->type) {
case X86_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*ud, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*ud, op->reg));
break;
case X86_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
break;
case X86_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.segment != X86_REG_INVALID)
addStr(&result, " ; operands[%u].mem.segment: REG = %s", i, cs_reg_name(*ud, op->mem.segment));
add_str(&result, " ; operands[%u].mem.segment: REG = %s", i, cs_reg_name(*ud, op->mem.segment));
if (op->mem.base != X86_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*ud, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*ud, op->mem.base));
if (op->mem.index != X86_REG_INVALID)
addStr(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*ud, op->mem.index));
add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*ud, op->mem.index));
if (op->mem.scale != 1)
addStr(&result, " ; operands[%u].mem.scale: %u", i, op->mem.scale);
add_str(&result, " ; operands[%u].mem.scale: %u", i, op->mem.scale);
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
break;
default:
break;
@ -284,25 +284,25 @@ char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins)
// AVX broadcast type
if (op->avx_bcast != X86_AVX_BCAST_INVALID)
addStr(&result, " ; operands[%u].avx_bcast: %u", i, op->avx_bcast);
add_str(&result, " ; operands[%u].avx_bcast: %u", i, op->avx_bcast);
// AVX zero opmask {z}
if (op->avx_zero_opmask != false)
addStr(&result, " ; operands[%u].avx_zero_opmask: TRUE", i);
add_str(&result, " ; operands[%u].avx_zero_opmask: TRUE", i);
addStr(&result, " ; operands[%u].size: %u", i, op->size);
add_str(&result, " ; operands[%u].size: %u", i, op->size);
switch(op->access) {
default:
break;
case CS_AC_READ:
addStr(&result, " ; operands[%u].access: READ", i);
add_str(&result, " ; operands[%u].access: READ", i);
break;
case CS_AC_WRITE:
addStr(&result, " ; operands[%u].access: WRITE", i);
add_str(&result, " ; operands[%u].access: WRITE", i);
break;
case CS_AC_READ | CS_AC_WRITE:
addStr(&result, " ; operands[%u].access: READ | WRITE", i);
add_str(&result, " ; operands[%u].access: READ | WRITE", i);
break;
}
}
@ -310,16 +310,16 @@ char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins)
// Print out all registers accessed by this instruction (either implicit or explicit)
if (!cs_regs_access(*ud, ins, regs_read, &regs_read_count, regs_write, &regs_write_count)) {
if (regs_read_count) {
addStr(&result, " ; Registers read:");
add_str(&result, " ; Registers read:");
for(i = 0; i < regs_read_count; i++) {
addStr(&result, " %s", cs_reg_name(*ud, regs_read[i]));
add_str(&result, " %s", cs_reg_name(*ud, regs_read[i]));
}
}
if (regs_write_count) {
addStr(&result, " ; Registers modified:");
add_str(&result, " ; Registers modified:");
for(i = 0; i < regs_write_count; i++) {
addStr(&result, " %s", cs_reg_name(*ud, regs_write[i]));
add_str(&result, " %s", cs_reg_name(*ud, regs_write[i]));
}
}
}
@ -327,20 +327,20 @@ char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins)
if (x86->eflags || x86->fpu_flags) {
for(i = 0; i < ins->detail->groups_count; i++) {
if (ins->detail->groups[i] == X86_GRP_FPU) {
addStr(&result, " ; FPU_FLAGS:");
add_str(&result, " ; FPU_FLAGS:");
for(i = 0; i <= 63; i++)
if (x86->fpu_flags & ((uint64_t)1 << i)) {
addStr(&result, " %s", get_fpu_flag_name((uint64_t)1 << i));
add_str(&result, " %s", get_fpu_flag_name((uint64_t)1 << i));
}
break;
}
}
if (i == ins->detail->groups_count) {
addStr(&result, " ; EFLAGS:");
add_str(&result, " ; EFLAGS:");
for(i = 0; i <= 63; i++)
if (x86->eflags & ((uint64_t)1 << i)) {
addStr(&result, " %s", get_eflag_name((uint64_t)1 << i));
add_str(&result, " %s", get_eflag_name((uint64_t)1 << i));
}
}
}

16
suite/cstest/src/xcore_detail.c
View File

@ -15,7 +15,7 @@ char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins)
xcore = &(ins->detail->xcore);
if (xcore->op_count)
addStr(&result, " ; op_count: %u", xcore->op_count);
add_str(&result, " ; op_count: %u", xcore->op_count);
for (i = 0; i < xcore->op_count; i++) {
cs_xcore_op *op = &(xcore->operands[i]);
@ -23,21 +23,21 @@ char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins)
default:
break;
case XCORE_OP_REG:
addStr(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
break;
case XCORE_OP_IMM:
addStr(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
break;
case XCORE_OP_MEM:
addStr(&result, " ; operands[%u].type: MEM", i);
add_str(&result, " ; operands[%u].type: MEM", i);
if (op->mem.base != XCORE_REG_INVALID)
addStr(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
if (op->mem.index != XCORE_REG_INVALID)
addStr(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
if (op->mem.disp != 0)
addStr(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
if (op->mem.direct != 1)
addStr(&result, " ; operands[%u].mem.direct: -1", i);
add_str(&result, " ; operands[%u].mem.direct: -1", i);
break;