From d91f964d400d00ca35db1300d94c162fbdbc26e4 Mon Sep 17 00:00:00 2001 From: flyingsymbols Date: Wed, 22 Oct 2014 03:21:43 -0400 Subject: [PATCH] * Fixed bug in Thumb2 pop caused by me incorrectly assuming that ARM_SP == 13, ARM_LR == 14, and ARM_PC == 15, which is not the case * updated CMakeLists to include building arm regression test * added explicit casts for 64 bit visual studio 2012 build to get around truncation warnings from size_t conversion --- CMakeLists.txt | 12 ++++++-- SStream.c | 2 +- arch/ARM/ARMDisassembler.c | 3 +- cs.c | 2 +- inttypes.h | 2 +- suite/arm/test_arm_regression.c | 52 +++++++++++++++++++++------------ 6 files changed, 46 insertions(+), 27 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 29de601e..2110feb8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -182,10 +182,16 @@ endif () if (CAPSTONE_BUILD_TESTS) foreach (TSRC ${TEST_SOURCES}) - STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC}) - add_executable(${TBIN} "tests/${TSRC}") - target_link_libraries(${TBIN} ${default-target}) + STRING(REGEX REPLACE ".c$" "" TBIN ${TSRC}) + add_executable(${TBIN} "tests/${TSRC}") + target_link_libraries(${TBIN} ${default-target}) endforeach () + if (CAPSTONE_ARM_SUPPORT) + set(ARM_REGRESS_TEST test_arm_regression.c) + STRING(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST}) + add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}") + target_link_libraries(${ARM_REGRESS_BIN} ${default-target}) + endif() endif () ## installation diff --git a/SStream.c b/SStream.c index c8cf7c8d..4cc60d71 100644 --- a/SStream.c +++ b/SStream.c @@ -24,7 +24,7 @@ void SStream_Init(SStream *ss) void SStream_concat0(SStream *ss, char *s) { #ifndef CAPSTONE_DIET - unsigned int len = strlen(s); + unsigned int len = (unsigned int) strlen(s); memcpy(ss->buffer + ss->index, s, len); ss->index += len; diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index 3f087ff3..6ef37b01 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -1272,8 +1272,7 @@ static DecodeStatus DecodeRegListOperand(MCInst *Inst, unsigned Val, } if (opcode == ARM_t2LDMIA_UPD && WritebackReg == ARM_SP) { - if (Val & (1 << ARM_SP) - || ((Val & (1 << ARM_PC)) && (Val & (1 << ARM_LR)))) { + if (Val & (1 << 13) || ((Val & (1 << 15)) && (Val & (1 << 14)))) { // invalid thumb2 pop // needs no sp in reglist and not both pc and lr set at the same time return MCDisassembler_Fail; diff --git a/cs.c b/cs.c index 320768dc..ea5e325f 100644 --- a/cs.c +++ b/cs.c @@ -437,7 +437,7 @@ size_t cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, si #ifdef CAPSTONE_USE_SYS_DYN_MEM if (count > 0 && count <= INSN_CACHE_SIZE) - cache_size = count; + cache_size = (unsigned int) count; #endif // save the original offset for SKIPDATA diff --git a/inttypes.h b/inttypes.h index be36f11c..b02129a1 100644 --- a/inttypes.h +++ b/inttypes.h @@ -1,4 +1,4 @@ -#if defined(_MSC_VER) && _MSC_VER < 1700 +#if defined(_MSC_VER) && _MSC_VER <= 1700 #include "msvc/headers/inttypes.h" #else #include diff --git a/suite/arm/test_arm_regression.c b/suite/arm/test_arm_regression.c index 562c70f4..3e093bb3 100644 --- a/suite/arm/test_arm_regression.c +++ b/suite/arm/test_arm_regression.c @@ -11,7 +11,7 @@ #include #include "../../inttypes.h" -#include +#include static csh handle; @@ -192,6 +192,7 @@ static void test_invalids() } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME); for (j = 0; j < invalid->num_invalid_codes; ++j) { struct invalid_code * invalid_code = NULL; @@ -252,24 +253,36 @@ static void test_valids() CS_ARCH_ARM, CS_MODE_THUMB, "Thumb", - 2, + 3, {{ (unsigned char *)"\x00\xf0\x26\xe8", 4, 0x352, + "0x352:\tblx\t#0x3a0\n" + "\top_count: 1\n" + "\t\toperands[0].type: IMM = 0x3a0\n", - "0x352:\tblx\t#0x3a0\n" - "\top_count: 1\n" - "\t\toperands[0].type: IMM = 0x3a0\n", + "thumb2 blx with misaligned immediate" + }, { (unsigned char *)"\x05\xdd", 2, 0x1f0, + "0x1f0:\tble\t#0x1fe\n" + "\top_count: 1\n" + "\t\toperands[0].type: IMM = 0x1fe\n" + "\tCode condition: 14\n", - "thumb2 blx with misaligned immediate" + "thumb b cc with thumb-aligned target" + }, { (unsigned char *)"\xbd\xe8\xf0\x8f", 4, 0, + "0x0:\tpop.w\t{r4, r5, r6, r7, r8, r9, r10, r11, pc}\n" + "\top_count: 9\n" + "\t\toperands[0].type: REG = r4\n" + "\t\toperands[1].type: REG = r5\n" + "\t\toperands[2].type: REG = r6\n" + "\t\toperands[3].type: REG = r7\n" + "\t\toperands[4].type: REG = r8\n" + "\t\toperands[5].type: REG = r9\n" + "\t\toperands[6].type: REG = r10\n" + "\t\toperands[7].type: REG = r11\n" + "\t\toperands[8].type: REG = pc\n", - }, { (unsigned char *)"\x05\xdd", 2, 0x1f0, - - "0x1f0:\tble\t#0x1fe\n" - "\top_count: 1\n" - "\t\toperands[0].type: IMM = 0x1fe\n" - "\tCode condition: 14\n", - - "thumb b cc with thumb-aligned target" - }} + "thumb2 pop that should be valid" + }, + } }}; struct valid_instructions * valid = NULL; @@ -293,6 +306,7 @@ static void test_valids() } cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME); #define _this_printf(...) \ { \ @@ -349,10 +363,10 @@ static void test_valids() if (memcmp(tmp_buf, valid_code->expected_out, max_len)) { printf( - " ERROR: '''\n%s''' does not match" - " expected '''\n%s'''\n", - tmp_buf, valid_code->expected_out - ); + " ERROR: '''\n%s''' does not match" + " expected '''\n%s'''\n", + tmp_buf, valid_code->expected_out + ); } else { printf(" SUCCESS: valid\n"); }