[M68K] Added basic groups
Added support for basic groups in the M68K backend. Also did some minor cleanups/whitespace fixes while at it. Relates to this issue https://github.com/aquynh/capstone/issues/494
This commit is contained in:
Daniel Collin
parent
3eae96de19
commit
d994c74b02
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@ -28,7 +28,7 @@
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*/
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/* The code bellow is based on MUSASHI but has been heavily modified for capstore by
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* Daniel Collin <daniel@collin.com> 2015 */
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* Daniel Collin <daniel@collin.com> 2015-2016 */
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/* ======================================================================== */
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/* ================================ INCLUDES ============================== */
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@ -152,12 +152,11 @@ enum {
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///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
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static unsigned int m68k_read_disassembler_16(const m68k_info *info, const uint64_t addr)
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{
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const uint16_t v0 = info->code[addr + 0];
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const uint16_t v1 = info->code[addr + 1];
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return (v0 << 8) | v1;
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return (v0 << 8) | v1;
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}
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static unsigned int m68k_read_disassembler_32(const m68k_info *info, const uint64_t addr)
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@ -380,7 +379,7 @@ static void get_with_index_address_mode(m68k_info *info, cs_m68k_op* op, uint in
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if (preindex) {
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op->address_mode = is_pc ? M68K_AM_PC_MEMI_PRE_INDEX : M68K_AM_MEMI_PRE_INDEX;
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} else if (postindex) {
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} else if (postindex) {
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op->address_mode = is_pc ? M68K_AM_PC_MEMI_POST_INDEX : M68K_AM_MEMI_POST_INDEX;
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}
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@ -388,21 +387,21 @@ static void get_with_index_address_mode(m68k_info *info, cs_m68k_op* op, uint in
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}
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op->mem.index_reg = (EXT_INDEX_AR(extension) ? M68K_REG_A0 : M68K_REG_D0) + EXT_INDEX_REGISTER(extension);
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op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0;
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op->mem.index_size = EXT_INDEX_LONG(extension) ? 1 : 0;
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if (EXT_8BIT_DISPLACEMENT(extension) == 0) {
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if (is_pc) {
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op->mem.base_reg = M68K_REG_PC;
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op->mem.base_reg = M68K_REG_PC;
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op->address_mode = M68K_AM_PCI_INDEX_BASE_DISP;
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} else {
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op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
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op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
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}
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} else {
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if (is_pc) {
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op->mem.base_reg = M68K_REG_PC;
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op->mem.base_reg = M68K_REG_PC;
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op->address_mode = M68K_AM_PCI_INDEX_8_BIT_DISP;
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} else {
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op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
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op->mem.base_reg = M68K_REG_A0 + (instruction & 7);
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op->address_mode = M68K_AM_AREGI_INDEX_8_BIT_DISP;
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}
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@ -509,6 +508,11 @@ void get_ea_mode_op(m68k_info *info, cs_m68k_op* op, uint instruction, uint size
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}
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}
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static void set_insn_group(m68k_info *info, m68k_group_type group)
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{
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info->groups[info->groups_count++] = (uint8_t)group;
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}
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static cs_m68k* build_init_op(m68k_info *info, int opcode, int count, int size)
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{
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cs_m68k* ext;
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@ -621,7 +625,7 @@ static void build_imm_ea(m68k_info *info, int opcode, uint8_t size, int imm)
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op0->type = M68K_OP_IMM;
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op0->address_mode = M68K_AM_IMMIDIATE;
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op0->imm = imm;
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op0->imm = imm;
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get_ea_mode_op(info, op1, info->ir, size);
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}
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@ -745,10 +749,10 @@ static void build_imm_special_reg(m68k_info *info, int opcode, int imm, int size
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op0->type = M68K_OP_IMM;
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op0->address_mode = M68K_AM_IMMIDIATE;
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op0->imm = imm;
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op0->imm = imm;
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op1->address_mode = M68K_AM_NONE;
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op1->reg = reg;
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op1->reg = reg;
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}
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static void build_bxx(m68k_info *info, int opcode, int size, int jump_offset)
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@ -761,6 +765,8 @@ static void build_bxx(m68k_info *info, int opcode, int size, int jump_offset)
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op->type = M68K_OP_IMM;
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op->address_mode = M68K_AM_IMMIDIATE;
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op->imm = jump_offset;
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set_insn_group(info, M68K_GRP_JUMP);
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}
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static void build_bcc(m68k_info *info, int size, int jump_offset)
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@ -788,6 +794,8 @@ static void build_dbxx(m68k_info *info, int opcode, int size, int jump_offset)
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op1->type = M68K_OP_IMM;
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op1->address_mode = M68K_AM_IMMIDIATE;
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op1->imm = jump_offset;
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set_insn_group(info, M68K_GRP_JUMP);
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}
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static void build_dbcc(m68k_info *info, int size, int jump_offset)
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@ -867,7 +875,7 @@ static uint16_t reverse_bits(uint v)
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uint r = v; // r will be reversed bits of v; first get LSB of v
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uint s = 16 - 1; // extra shift needed at end
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for (v >>= 1; v; v >>= 1) {
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for (v >>= 1; v; v >>= 1) {
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r <<= 1;
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r |= v & 1;
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s--;
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@ -881,7 +889,7 @@ static uint8_t reverse_bits_8(uint v)
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uint r = v; // r will be reversed bits of v; first get LSB of v
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uint s = 8 - 1; // extra shift needed at end
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for (v >>= 1; v; v >>= 1) {
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for (v >>= 1; v; v >>= 1) {
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r <<= 1;
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r |= v & 1;
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s--;
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@ -1056,7 +1064,7 @@ static void build_cpush_cinv(m68k_info *info, int op_offset)
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switch ((info->ir >> 3) & 3) { // scope
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// Invalid
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case 0:
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case 0:
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d68000_invalid(info);
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return;
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// Line
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@ -1868,11 +1876,11 @@ static void fmove_fpcr(m68k_info *info, uint extension)
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get_ea_mode_op(info, op_ea, info->ir, 4);
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if (regsel & 4)
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if (regsel & 4)
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special->reg = M68K_REG_FPCR;
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else if (regsel & 2)
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else if (regsel & 2)
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special->reg = M68K_REG_FPSR;
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else if (regsel & 1)
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else if (regsel & 1)
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special->reg = M68K_REG_FPIAR;
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}
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@ -1903,7 +1911,7 @@ static void fmovem(m68k_info *info, uint extension)
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op_reglist->reg = M68K_REG_D0 + ((reglist >> 4) & 7);
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break;
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case 0 :
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case 0 :
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op_reglist->address_mode = M68K_AM_NONE;
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op_reglist->type = M68K_OP_REG_BITS;
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op_reglist->register_bits = reglist << 16;
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@ -2018,7 +2026,7 @@ static void d68020_cpgen(m68k_info *info)
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case 0x28: MCInst_setOpcode(info->inst, M68K_INS_FSUB); supports_single_op = false; break;
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case 0x38: MCInst_setOpcode(info->inst, M68K_INS_FCMP); supports_single_op = false; break;
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case 0x3a: MCInst_setOpcode(info->inst, M68K_INS_FTST); break;
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default:
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default:
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break;
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}
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@ -2050,22 +2058,22 @@ static void d68020_cpgen(m68k_info *info)
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if (rm == 1) {
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switch (src) {
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case 0x00 :
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case 0x00 :
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ext->op_size.cpu_size = M68K_CPU_SIZE_LONG;
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get_ea_mode_op(info, op0, info->ir, 4);
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break;
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case 0x06 :
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case 0x06 :
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ext->op_size.cpu_size = M68K_CPU_SIZE_BYTE;
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get_ea_mode_op(info, op0, info->ir, 1);
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break;
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case 0x04 :
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case 0x04 :
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ext->op_size.cpu_size = M68K_CPU_SIZE_WORD;
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get_ea_mode_op(info, op0, info->ir, 2);
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break;
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case 0x01 :
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case 0x01 :
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ext->op_size.type = M68K_SIZE_TYPE_FPU;
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ext->op_size.fpu_size = M68K_FPU_SIZE_SINGLE;
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get_ea_mode_op(info, op0, info->ir, 4);
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@ -2339,12 +2347,14 @@ static void d68020_extb_32(m68k_info *info)
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static void d68000_jmp(m68k_info *info)
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{
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set_insn_group(info, M68K_GRP_JUMP);
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cs_m68k* ext = build_init_op(info, M68K_INS_JMP, 1, 0);
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get_ea_mode_op(info, &ext->operands[0], info->ir, 4);
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}
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static void d68000_jsr(m68k_info *info)
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{
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set_insn_group(info, M68K_GRP_JUMP);
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cs_m68k* ext = build_init_op(info, M68K_INS_JSR, 1, 0);
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get_ea_mode_op(info, &ext->operands[0], info->ir, 4);
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}
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@ -3065,12 +3075,14 @@ static void d68000_roxl_ea(m68k_info *info)
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static void d68010_rtd(m68k_info *info)
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{
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set_insn_group(info, M68K_GRP_RET);
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LIMIT_CPU_TYPES(info, M68010_PLUS);
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build_bxx(info, M68K_INS_RTD, 0, read_imm_16(info));
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}
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static void d68000_rte(m68k_info *info)
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{
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set_insn_group(info, M68K_GRP_IRET);
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MCInst_setOpcode(info->inst, M68K_INS_RTE);
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}
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@ -3079,6 +3091,7 @@ static void d68020_rtm(m68k_info *info)
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cs_m68k* ext;
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cs_m68k_op* op;
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set_insn_group(info, M68K_GRP_RET);
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LIMIT_CPU_TYPES(info, M68020_ONLY);
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@ -3099,11 +3112,13 @@ static void d68020_rtm(m68k_info *info)
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static void d68000_rtr(m68k_info *info)
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{
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set_insn_group(info, M68K_GRP_RET);
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MCInst_setOpcode(info->inst, M68K_INS_RTR);
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}
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static void d68000_rts(m68k_info *info)
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{
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set_insn_group(info, M68K_GRP_RET);
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MCInst_setOpcode(info->inst, M68K_INS_RTS);
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}
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@ -3861,14 +3876,14 @@ static unsigned int m68k_disassemble(m68k_info *info, uint64_t pc)
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MCInst *inst = info->inst;
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cs_m68k* ext = &info->extension;
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int i;
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inst->Opcode = M68K_INS_INVALID;
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build_opcode_table();
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memset(ext, 0, sizeof(cs_m68k));
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ext->op_size.type = M68K_SIZE_TYPE_CPU;
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for (i = 0; i < M68K_OPERAND_COUNT; ++i)
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ext->operands[i].type = M68K_OP_REG;
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@ -3889,7 +3904,7 @@ bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* i
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int s;
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int cpu_type = M68K_CPU_TYPE_68000;
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cs_struct* handle = instr->csh;
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m68k_info *info = (m68k_info *)handle->printer_info;
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m68k_info *info = (m68k_info*)handle->printer_info;
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info->code = code;
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info->code_len = code_len;
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@ -3919,7 +3934,7 @@ bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* i
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M68K_printInst(instr, &ss, info);
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#endif
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// Make sure we always stay within range
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// Make sure we always stay within range
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if (s > (int)code_len)
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*size = (uint16_t)code_len;
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else
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@ -1,5 +1,5 @@
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/* Capstone Disassembly Engine */
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/* M68K Backend by Daniel Collin <daniel@collin.com> 2015 */
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/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
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#ifndef CS_M68KDISASSEMBLER_H
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#define CS_M68KDISASSEMBLER_H
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@ -18,6 +18,8 @@ typedef struct m68k_info {
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unsigned int type;
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unsigned int address_mask; /* Address mask to simulate address lines */
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cs_m68k extension;
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uint8_t groups[8];
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uint8_t groups_count;
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} m68k_info;
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bool M68K_getInstruction(csh ud, const uint8_t* code, size_t code_len, MCInst* instr, uint16_t* size, uint64_t address, void* info);
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@ -1,5 +1,5 @@
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/* Capstone Disassembly Engine */
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/* M68K Backend by Daniel Collin <daniel@collin.com> 2015 */
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/* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
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#ifdef _MSC_VER
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// Disable security warnings for strcat & sprintf
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@ -34,7 +34,7 @@ static const char* s_reg_names[] = {
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"caar", "msp", "isp", "tc", "itt0", "itt1", "dtt0",
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"dtt1", "mmusr", "urp", "srp",
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"fpcr", "fpsr", "fpiar",
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"fpcr", "fpsr", "fpiar",
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};
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static const char* s_instruction_names[] = {
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@ -49,15 +49,15 @@ static const char* s_instruction_names[] = {
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"fcosh", "fdbf", "fdbeq", "fdbogt", "fdboge", "fdbolt", "fdbole", "fdbogl", "fdbor", "fdbun", "fdbueq", "fdbugt", "fdbuge", "fdbult", "fdbule", "fdbne",
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"fdbt", "fdbsf", "fdbseq", "fdbgt", "fdbge", "fdblt", "fdble", "fdbgl", "fdbgle", "fdbngle", "fdbngl", "fdbnle", "fdbnlt", "fdbnge", "fdbngt", "fdbsne",
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"fdbst", "fdiv", "fsdiv", "fddiv", "fetox", "fetoxm1", "fgetexp", "fgetman", "fint", "fintrz", "flog10", "flog2", "flogn", "flognp1", "fmod", "fmove",
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"fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv",
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"fsmove", "fdmove", "fmovecr", "fmovem", "fmul", "fsmul", "fdmul", "fneg", "fsneg", "fdneg", "fnop", "frem", "frestore", "fsave", "fscale", "fsgldiv",
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"fsglmul", "fsin", "fsincos", "fsinh", "fsqrt", "fssqrt", "fdsqrt", "fsf", "fseq", "fsogt", "fsoge", "fsolt", "fsole", "fsogl", "fsor", "fsun", "fsueq",
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"fsugt", "fsuge", "fsult", "fsule", "fsne", "fst", "fssf", "fsseq", "fsgt", "fsge", "fslt", "fsle", "fsgl", "fsgle", "fsngle",
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"fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt",
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"ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt",
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"ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge",
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"ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec",
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"movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha",
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"pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror",
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"fsngl", "fsnle", "fsnlt", "fsnge", "fsngt", "fssne", "fsst", "fsub", "fssub", "fdsub", "ftan", "ftanh", "ftentox", "ftrapf", "ftrapeq", "ftrapogt",
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"ftrapoge", "ftrapolt", "ftrapole", "ftrapogl", "ftrapor", "ftrapun", "ftrapueq", "ftrapugt", "ftrapuge", "ftrapult", "ftrapule", "ftrapne", "ftrapt",
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"ftrapsf", "ftrapseq", "ftrapgt", "ftrapge", "ftraplt", "ftraple", "ftrapgl", "ftrapgle", "ftrapngle", "ftrapngl", "ftrapnle", "ftrapnlt", "ftrapnge",
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"ftrapngt", "ftrapsne", "ftrapst", "ftst", "ftwotox", "halt", "illegal", "jmp", "jsr", "lea", "link", "lpstop", "lsl", "lsr", "move", "movea", "movec",
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"movem", "movep", "moveq", "moves", "move16", "muls", "mulu", "nbcd", "neg", "negx", "nop", "not", "or", "ori", "pack", "pea", "pflush", "pflusha",
|
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"pflushan", "pflushn", "ploadr", "ploadw", "plpar", "plpaw", "pmove", "pmovefd", "ptestr", "ptestw", "pulse", "rems", "remu", "reset", "rol", "ror",
|
||||
"roxl", "roxr", "rtd", "rte", "rtm", "rtr", "rts", "sbcd", "st", "sf", "shi", "sls", "scc", "shs", "scs", "slo", "sne", "seq", "svc", "svs", "spl", "smi",
|
||||
"sge", "slt", "sgt", "sle", "stop", "sub", "suba", "subi", "subq", "subx", "swap", "tas", "trap", "trapv", "trapt", "trapf", "traphi", "trapls",
|
||||
"trapcc", "traphs", "trapcs", "traplo", "trapne", "trapeq", "trapvc", "trapvs", "trappl", "trapmi", "trapge", "traplt", "trapgt", "traple", "tst", "unlk", "unpk",
|
||||
|
|
@ -100,7 +100,7 @@ static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix)
|
|||
static void registerBits(SStream* O, const cs_m68k_op* op)
|
||||
{
|
||||
char buffer[128];
|
||||
unsigned int data = op->register_bits;
|
||||
unsigned int data = op->register_bits;
|
||||
|
||||
buffer[0] = 0;
|
||||
|
||||
|
|
@ -113,7 +113,7 @@ static void registerBits(SStream* O, const cs_m68k_op* op)
|
|||
|
||||
static void registerPair(SStream* O, const cs_m68k_op* op)
|
||||
{
|
||||
SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + (op->register_bits >> 4)],
|
||||
SStream_concat(O, "%s:%s", s_reg_names[M68K_REG_D0 + (op->register_bits >> 4)],
|
||||
s_reg_names[M68K_REG_D0 + (op->register_bits & 0xf)]);
|
||||
}
|
||||
|
||||
|
|
@ -143,8 +143,8 @@ void printAddressingMode(SStream* O, const cs_m68k* inst, const cs_m68k_op* op)
|
|||
case M68K_AM_REGI_ADDR_PRE_DEC: SStream_concat(O, "-(a%d)", (op->reg - M68K_REG_A0)); break;
|
||||
case M68K_AM_REGI_ADDR_DISP: SStream_concat(O, "$%x(a%d)", op->mem.disp, (op->reg - M68K_REG_A0)); break;
|
||||
case M68K_AM_PCI_DISP: SStream_concat(O, "$%x(pc)", op->mem.disp); break;
|
||||
case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break;
|
||||
case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break;
|
||||
case M68K_AM_ABSOLUTE_DATA_SHORT: SStream_concat(O, "$%x.w", op->imm); break;
|
||||
case M68K_AM_ABSOLUTE_DATA_LONG: SStream_concat(O, "$%x.l", op->imm); break;
|
||||
case M68K_AM_IMMIDIATE:
|
||||
if (inst->op_size.type == M68K_SIZE_TYPE_FPU) {
|
||||
if (inst->op_size.fpu_size == M68K_FPU_SIZE_SINGLE)
|
||||
|
|
@ -161,7 +161,7 @@ void printAddressingMode(SStream* O, const cs_m68k* inst, const cs_m68k_op* op)
|
|||
SStream_concat(O, "$%x(pc,%s%s.%c)", op->mem.disp, s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
|
||||
break;
|
||||
case M68K_AM_AREGI_INDEX_8_BIT_DISP:
|
||||
SStream_concat(O, "$%x(%s,%s%s.%c)", op->mem.disp, getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
|
||||
SStream_concat(O, "$%x(%s,%s%s.%c)", op->mem.disp, getRegName(op->mem.base_reg), s_spacing, getRegName(op->mem.index_reg), op->mem.index_size ? 'l' : 'w');
|
||||
break;
|
||||
case M68K_AM_PCI_INDEX_BASE_DISP:
|
||||
case M68K_AM_AREGI_INDEX_BASE_DISP:
|
||||
|
|
@ -196,9 +196,9 @@ void printAddressingMode(SStream* O, const cs_m68k* inst, const cs_m68k_op* op)
|
|||
|
||||
if (op->mem.base_reg != M68K_REG_INVALID) {
|
||||
if (op->mem.in_disp > 0)
|
||||
SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg));
|
||||
SStream_concat(O, ",%s%s", s_spacing, getRegName(op->mem.base_reg));
|
||||
else
|
||||
SStream_concat(O, "%s", getRegName(op->mem.base_reg));
|
||||
SStream_concat(O, "%s", getRegName(op->mem.base_reg));
|
||||
}
|
||||
|
||||
if (op->address_mode == M68K_AM_MEMI_POST_INDEX || op->address_mode == M68K_AM_PC_MEMI_POST_INDEX)
|
||||
|
|
@ -238,9 +238,10 @@ void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo)
|
|||
detail = MI->flat_insn->detail;
|
||||
if (detail) {
|
||||
memcpy(&detail->m68k, ext, sizeof(cs_m68k));
|
||||
memcpy(&detail->groups, &info->groups, info->groups_count);
|
||||
detail->groups_count = info->groups_count;
|
||||
detail->regs_read_count = 0;
|
||||
detail->regs_write_count = 0;
|
||||
detail->groups_count = 0;
|
||||
}
|
||||
|
||||
if (MI->Opcode == M68K_INS_INVALID) {
|
||||
|
|
@ -262,7 +263,7 @@ void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo)
|
|||
case M68K_CPU_SIZE_BYTE: SStream_concat0(O, ".b"); break;
|
||||
case M68K_CPU_SIZE_WORD: SStream_concat0(O, ".w"); break;
|
||||
case M68K_CPU_SIZE_LONG: SStream_concat0(O, ".l"); break;
|
||||
case M68K_CPU_SIZE_NONE: break;
|
||||
case M68K_CPU_SIZE_NONE: break;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -271,14 +272,14 @@ void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo)
|
|||
case M68K_FPU_SIZE_SINGLE: SStream_concat0(O, ".s"); break;
|
||||
case M68K_FPU_SIZE_DOUBLE: SStream_concat0(O, ".d"); break;
|
||||
case M68K_FPU_SIZE_EXTENDED: SStream_concat0(O, ".x"); break;
|
||||
case M68K_FPU_SIZE_NONE: break;
|
||||
case M68K_FPU_SIZE_NONE: break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
SStream_concat0(O, " ");
|
||||
|
||||
// this one is a bit spacial so we do spacial things
|
||||
// this one is a bit spacial so we do special things
|
||||
|
||||
if (MI->Opcode == M68K_INS_CAS2) {
|
||||
int reg_value_0, reg_value_1;
|
||||
|
|
@ -286,7 +287,7 @@ void M68K_printInst(MCInst* MI, SStream* O, void* PrinterInfo)
|
|||
printAddressingMode(O, ext, &ext->operands[1]); SStream_concat0(O, ",");
|
||||
reg_value_0 = ext->operands[2].register_bits >> 4;
|
||||
reg_value_1 = ext->operands[2].register_bits & 0xf;
|
||||
SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]);
|
||||
SStream_concat(O, "(%s):(%s)", s_reg_names[M68K_REG_D0 + reg_value_0], s_reg_names[M68K_REG_D0 + reg_value_1]);
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -321,9 +322,21 @@ const char* M68K_insn_name(csh handle, unsigned int id)
|
|||
#endif
|
||||
}
|
||||
|
||||
const char* M68K_group_name(csh handle, unsigned int id)
|
||||
#ifndef CAPSTONE_DIET
|
||||
static name_map group_name_maps[] = {
|
||||
{ M68K_GRP_INVALID , NULL },
|
||||
{ M68K_GRP_JUMP, "jump" },
|
||||
{ M68K_GRP_RET , "ret" },
|
||||
{ M68K_GRP_IRET, "iret" },
|
||||
};
|
||||
#endif
|
||||
|
||||
const char *M68K_group_name(csh handle, unsigned int id)
|
||||
{
|
||||
// TODO: Implement group names in m68k
|
||||
#ifndef CAPSTONE_DIET
|
||||
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
|
||||
#else
|
||||
return NULL;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
#define CAPSTONE_M68K_H
|
||||
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Daniel Collin <daniel@collin.com>, 2015 */
|
||||
/* By Daniel Collin <daniel@collin.com>, 2015-2016 */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
|
|
@ -78,7 +78,7 @@ typedef enum m68k_reg {
|
|||
|
||||
//> M68K Addressing Modes
|
||||
typedef enum m68k_adress_mode {
|
||||
M68K_AM_NONE = 0, // No address mode.
|
||||
M68K_AM_NONE = 0, // No address mode.
|
||||
|
||||
M68K_AM_REG_DIRECT_DATA, // Register Direct - Data
|
||||
M68K_AM_REG_DIRECT_ADDR, // Register Direct - Address
|
||||
|
|
@ -105,7 +105,7 @@ typedef enum m68k_adress_mode {
|
|||
M68K_AM_ABSOLUTE_DATA_SHORT, // Absolute Data Addressing - Short
|
||||
M68K_AM_ABSOLUTE_DATA_LONG, // Absolute Data Addressing - Long
|
||||
M68K_AM_IMMIDIATE, // Immidate value
|
||||
} m68k_adress_mode;
|
||||
} m68k_adress_mode;
|
||||
|
||||
//> Operand type for instruction's operands
|
||||
typedef enum m68k_op_type {
|
||||
|
|
@ -115,7 +115,7 @@ typedef enum m68k_op_type {
|
|||
M68K_OP_MEM, // = CS_OP_MEM (Memory operand).
|
||||
M68K_OP_FP, // = CS_OP_FP (Floating-Point operand)
|
||||
M68K_OP_REG_BITS, // Registes bits movem
|
||||
M68K_OP_REG_PAIR, // Register pair in the same op (upper 4 bits for first reg, lower for second)
|
||||
M68K_OP_REG_PAIR, // Register pair in the same op (upper 4 bits for first reg, lower for second)
|
||||
} m68k_op_type;
|
||||
|
||||
// Instruction's operand referring to memory
|
||||
|
|
@ -124,12 +124,12 @@ typedef struct m68k_op_mem {
|
|||
m68k_reg base_reg; // base register (or M68K_REG_INVALID if irrelevant)
|
||||
m68k_reg index_reg; // index register (or M68K_REG_INVALID if irrelevant)
|
||||
m68k_reg in_base_reg; // indirect base register (or M68K_REG_INVALID if irrelevant)
|
||||
uint32_t in_disp; // indirect displacement
|
||||
uint32_t out_disp; // outher displacement
|
||||
uint32_t in_disp; // indirect displacement
|
||||
uint32_t out_disp; // outher displacement
|
||||
uint16_t disp; // displacement value
|
||||
uint8_t scale; // scale for index register
|
||||
uint8_t bitfield; // set to true if the two values bellow should be used
|
||||
uint8_t width; // used for bf* instructions
|
||||
uint8_t bitfield; // set to true if the two values bellow should be used
|
||||
uint8_t width; // used for bf* instructions
|
||||
uint8_t offset; // used for bf* instructions
|
||||
uint8_t index_size; // 0 = w, 1 = l
|
||||
} m68k_op_mem;
|
||||
|
|
@ -145,10 +145,10 @@ typedef struct cs_m68k_op {
|
|||
uint32_t register_bits; // register bits for movem/cas2/etc (always in d0-d7, a0-a7, fp0 - fp7 order)
|
||||
};
|
||||
m68k_op_type type;
|
||||
m68k_adress_mode address_mode; // M68K addressing mode for this op
|
||||
m68k_adress_mode address_mode; // M68K addressing mode for this op
|
||||
} cs_m68k_op;
|
||||
|
||||
// Operation size of the CPU instructions
|
||||
// Operation size of the CPU instructions
|
||||
typedef enum m68k_cpu_size {
|
||||
M68K_CPU_SIZE_NONE = 0, // unsized or unspecified
|
||||
M68K_CPU_SIZE_BYTE = 1, // 1 byte in size
|
||||
|
|
@ -159,8 +159,8 @@ typedef enum m68k_cpu_size {
|
|||
// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)
|
||||
typedef enum m68k_fpu_size {
|
||||
M68K_FPU_SIZE_NONE = 0, // unsized like fsave/frestore
|
||||
M68K_FPU_SIZE_SINGLE = 4, // 4 byte in size (single float)
|
||||
M68K_FPU_SIZE_DOUBLE = 8, // 8 byte in size (double)
|
||||
M68K_FPU_SIZE_SINGLE = 4, // 4 byte in size (single float)
|
||||
M68K_FPU_SIZE_DOUBLE = 8, // 8 byte in size (double)
|
||||
M68K_FPU_SIZE_EXTENDED = 12, // 12 byte in size (extended real format)
|
||||
} m68k_fpu_size;
|
||||
|
||||
|
|
@ -569,6 +569,16 @@ typedef enum m68k_insn {
|
|||
M68K_INS_UNPK,
|
||||
} m68k_insn;
|
||||
|
||||
//> Group of M68K instructions
|
||||
typedef enum m68k_group_type {
|
||||
M68K_GRP_INVALID = 0, // CS_GRUP_INVALID
|
||||
M68K_GRP_JUMP, // = CS_GRP_JUMP
|
||||
M68K_GRP_RET = 3, // = CS_GRP_RET
|
||||
M68K_GRP_IRET, // = CS_GRP_IRET
|
||||
|
||||
M68K_GRP_ENDING,
|
||||
} m68k_group_type;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -56,21 +56,25 @@ const char* s_addressing_modes[] = {
|
|||
"Absolute Data Addressing - Short",
|
||||
"Absolute Data Addressing - Long",
|
||||
"Immidate value",
|
||||
};
|
||||
};
|
||||
|
||||
static void print_insn_detail(cs_insn *ins)
|
||||
{
|
||||
cs_m68k* m68k;
|
||||
cs_detail* detail;
|
||||
int i;
|
||||
|
||||
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
|
||||
if (ins->detail == NULL)
|
||||
return;
|
||||
|
||||
m68k = &(ins->detail->m68k);
|
||||
detail = ins->detail;
|
||||
m68k = &detail->m68k;
|
||||
if (m68k->op_count)
|
||||
printf("\top_count: %u\n", m68k->op_count);
|
||||
|
||||
printf("\tgroups_count: %u\n", detail->groups_count);
|
||||
|
||||
for (i = 0; i < m68k->op_count; i++) {
|
||||
cs_m68k_op* op = &(m68k->operands[i]);
|
||||
|
||||
|
|
@ -121,7 +125,7 @@ static void print_insn_detail(cs_insn *ins)
|
|||
|
||||
static void test()
|
||||
{
|
||||
#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28"
|
||||
#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
|
||||
|
||||
struct platform platforms[] = {
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue