systemz: support accesss register operand
This commit is contained in:
parent
4321468245
commit
da1e833c8c
|
@ -29,23 +29,6 @@
|
|||
|
||||
static const char *getRegisterName(unsigned RegNo);
|
||||
|
||||
static void set_mem_access(MCInst *MI, bool status)
|
||||
{
|
||||
if (MI->csh->detail != CS_OPT_ON)
|
||||
return;
|
||||
|
||||
MI->csh->doing_mem = status;
|
||||
|
||||
if (status) {
|
||||
MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_MEM;
|
||||
MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.base = SYSZ_REG_INVALID;
|
||||
MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].mem.disp = 0;
|
||||
} else {
|
||||
// done, create the next operand slot
|
||||
MI->flat_insn.sysz.op_count++;
|
||||
}
|
||||
}
|
||||
|
||||
void SystemZ_post_printer(csh ud, cs_insn *insn, char *insn_asm)
|
||||
{
|
||||
/*
|
||||
|
@ -59,7 +42,7 @@ static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index
|
|||
if (Disp >= 0) {
|
||||
if (Disp > HEX_THRESHOLD)
|
||||
SStream_concat(O, "0x%"PRIx64, Disp);
|
||||
else if (Disp) // do not print Zero offset
|
||||
else
|
||||
SStream_concat(O, "%"PRIu64, Disp);
|
||||
} else {
|
||||
if (Disp < -HEX_THRESHOLD)
|
||||
|
@ -233,13 +216,11 @@ static void printAccessRegOperand(MCInst *MI, int OpNum, SStream *O)
|
|||
// assert(Value < 16 && "Invalid access register number");
|
||||
SStream_concat(O, "%%a%u", (unsigned int)Value);
|
||||
|
||||
/*
|
||||
if (MI->csh->detail) {
|
||||
MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_IMM;
|
||||
MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].imm = Value;
|
||||
MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].type = SYSZ_OP_ACREG;
|
||||
MI->flat_insn.sysz.operands[MI->flat_insn.sysz.op_count].reg = (unsigned int)Value;
|
||||
MI->flat_insn.sysz.op_count++;
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
static void printPCRelOperand(MCInst *MI, int OpNum, SStream *O)
|
||||
|
|
|
@ -39,6 +39,7 @@ typedef enum sysz_cc {
|
|||
typedef enum sysz_op_type {
|
||||
SYSZ_OP_INVALID = 0, // Uninitialized.
|
||||
SYSZ_OP_REG, // Register operand.
|
||||
SYSZ_OP_ACREG, // Access register operand.
|
||||
SYSZ_OP_IMM, // Immediate operand.
|
||||
SYSZ_OP_MEM, // Memory operand
|
||||
} sysz_op_type;
|
||||
|
|
|
@ -49,9 +49,9 @@ static void test()
|
|||
#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
|
||||
#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
|
||||
#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
|
||||
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
|
||||
|
||||
// #CHECK: afi %r0, -2147483648 # encoding: [0xc2,0x09,0x80,0x00,0x00,0x00]
|
||||
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24"
|
||||
|
||||
struct platform platforms[] = {
|
||||
{
|
||||
|
|
|
@ -55,7 +55,7 @@ static void test()
|
|||
#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
|
||||
#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
|
||||
#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
|
||||
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24"
|
||||
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
|
||||
|
||||
struct platform platforms[] = {
|
||||
{
|
||||
|
|
|
@ -44,6 +44,9 @@ static void print_insn_detail(cs_insn *ins)
|
|||
case SYSZ_OP_REG:
|
||||
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
|
||||
break;
|
||||
case SYSZ_OP_ACREG:
|
||||
printf("\t\toperands[%u].type: ACREG = %u\n", i, op->reg);
|
||||
break;
|
||||
case SYSZ_OP_IMM:
|
||||
printf("\t\toperands[%u].type: IMM = 0x%"PRIx64"\n", i, op->imm);
|
||||
break;
|
||||
|
@ -70,8 +73,7 @@ static void print_insn_detail(cs_insn *ins)
|
|||
|
||||
static void test()
|
||||
{
|
||||
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24"
|
||||
//#define SYSZ_CODE "\xeb\x00\xf0\x00\x00\x24"
|
||||
#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
|
||||
|
||||
struct platform platforms[] = {
|
||||
{
|
||||
|
|
Loading…
Reference in New Issue