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ppc & x86: add third dummy MRI argument to printInstruction() to make it consistent with other archs

This commit is contained in:
Nguyen Anh Quynh 2014-01-12 20:27:54 +08:00
parent 56774a158c
commit e51e227409
6 changed files with 9 additions and 8 deletions
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2
arch/PowerPC/PPCGenAsmWriter.inc
View File

@ -14,7 +14,7 @@
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
static void printInstruction(MCInst *MI, SStream *O)
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
static const uint32_t OpInfo[] = {
0U, // PHI

4
arch/PowerPC/PPCInstPrinter.c
View File

@ -31,7 +31,7 @@
static const char *getRegisterName(unsigned RegNo);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printInstruction(MCInst *MI, SStream *O);
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
static void printAbsBranchOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void set_mem_access(MCInst *MI, bool status)
@ -139,7 +139,7 @@ void PPC_printInst(MCInst *MI, SStream *O, void *Info)
//if (MCInst_getOpcode(MI) == TargetOpcode_COPY_TO_REGCLASS)
// return;
printInstruction(MI, O);
printInstruction(MI, O, NULL);
}

2
arch/X86/X86ATTInstPrinter.c
View File

@ -455,7 +455,7 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info)
MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem)));
cs_mem_free(mnem);
} else
printInstruction(MI, OS);
printInstruction(MI, OS, NULL);
if (MI->csh->detail) {
// first op can be embedded in the asm by llvm.

2
arch/X86/X86GenAsmWriter.inc
View File

@ -11,7 +11,7 @@
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
static void printInstruction(MCInst *MI, SStream *O)
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
static const uint32_t OpInfo[] = {
0U, // PHI

2
arch/X86/X86GenAsmWriter1.inc
View File

@ -11,7 +11,7 @@
/// printInstruction - This method is automatically generated by tablegen
/// from the instruction set description.
static void printInstruction(MCInst *MI, SStream *O)
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI)
{
static const uint32_t OpInfo[] = {
0U, // PHI

5
arch/X86/X86IntelInstPrinter.c
View File

@ -24,6 +24,7 @@
#include "../../utils.h"
#include "../../MCInst.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "mapping.h"
@ -216,7 +217,7 @@ static bool get_first_op(char *buffer, char *firstop)
}
static bool printAliasInstr(MCInst *MI, SStream *OS);
static void printInstruction(MCInst *MI, SStream *O);
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
{
//if (TSFlags & X86II::LOCK)
@ -231,7 +232,7 @@ void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info)
MCInst_setOpcode(MI, X86_get_insn_id2(X86_map_insn(mnem)));
cs_mem_free(mnem);
} else
printInstruction(MI, O);
printInstruction(MI, O, NULL);
if (MI->csh->detail) {
char tmp[64];