From 1781e589f2e8f3215b57fbf1e5cc095b6abb703d Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Sun, 16 Dec 2018 21:53:56 +0800 Subject: [PATCH 1/6] HACK.TXT: add TMS320C64x --- HACK.TXT | 1 + 1 file changed, 1 insertion(+) diff --git a/HACK.TXT b/HACK.TXT index f4f0e20d..e593c30d 100644 --- a/HACK.TXT +++ b/HACK.TXT @@ -12,6 +12,7 @@ Capstone source is organized as followings. │   ├── PowerPC <- PowerPC engine │   ├── Sparc <- Sparc engine │   ├── SystemZ <- SystemZ engine +│   ├── TMS320C64x <- TMS320C64x engine │   ├── X86 <- X86 engine │   └── XCore <- XCore engine ├── bindings <- all bindings are under this dir From 57d9bda493e29a910115aa6c72d6c9a39449b5c2 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Mon, 17 Dec 2018 19:10:31 +0800 Subject: [PATCH 2/6] fix ChangeLog --- ChangeLog | 101 ------------------------------------------------------ 1 file changed, 101 deletions(-) diff --git a/ChangeLog b/ChangeLog index 4fce31ab..2bfee9da 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,106 +1,5 @@ This file details the changelog of Capstone. -[ Arm ] - -- Fix a bug where Arm.Operand is wrongly calculated for the second and - following operands -- Fix a bug where Arm.OpInfo.memBarrier and Arm.OpInfo.op is wrongly - calculated - -[ Bindings ] - -- Java; add Capstone.strerror() and CsInsn.regsAccess(). - ---------------------------------- -Version 3.0.2: March 11th, 2015 - - -[ Library ] - -- On *nix, only export symbols that are part of the API (instead of all - the internal symbols). - - -[ X86 ] - -- Do not consider 0xF2 as REPNE prefix if it is a part of instruction encoding. -- Fix implicit registers read/written & instruction groups of some instructions. -- More flexible on the order of prefixes, so better handle some tricky - instructions. -- REPNE prefix can go with STOS & MOVS instructions. -- Fix a compilation bug for X86_REDUCE mode. -- Fix operand size of instructions with operand PTR [] - - -[ Arm ] - -- Fix a bug where arm_op_mem.disp is wrongly calculated (in DETAIL mode). -- Fix a bug on handling the If-Then block. - - -[ Mips ] - -- Sanity check for the input size for MIPS64 mode. - - -[ MSVC ] - -- Compile capstone.dll with static runtime MSVCR built in. - - -[ Python binding ] - -- Fix a compiling issue of Cython binding with gcc 4.9. - ---------------------------------- -Version 3.0.1: February 03rd, 2015 - -[ X86 ] - -- Properly handle LOCK, REP, REPE & REPNE prefixes. -- Handle undocumented immediates for SSE's (V)CMPPS/PD/SS/SD instructions. -- Print LJUMP/LCALL without * as prefix for Intel syntax. -- Handle REX prefix properly for segment/MMX related instructions (x86_64). -- Instruction with length > 15 is consider invalid. -- Handle some tricky encodings for instructions MOVSXD, FXCH, FCOM, FCOMP, - FSTP, FSTPNCE, NOP. -- Handle some tricky code for some X86_64 instructions with REX prefix. -- Add missing operands in detail mode for PUSH , POP , IN/OUT reg, reg -- MOV32ms & MOV32sm should reference word rather than dword. - - -[ Arm64 ] - -- BL & BLR instructions do not read SP register. -- Print absolute (rather than relative) address for instructions B, BL, - CBNZ, ADR. - - -[ Arm ] - -- Instructions ADC & SBC do not update flags. -- BL & BLX do not read SP, but PC register. -- Alias LDR instruction with operands [sp], 4 to POP. -- Print immediate operand of MVN instruction in positive hexadecimal form. - - -[ PowerPC ] - -- Fix some compilation bugs when DIET mode is enable. -- Populate SLWI/SRWI instruction details with SH operand. - - -[ Python binding ] - -- Fix a Cython bug when CsInsn.bytes returns a shorten array of bytes. -- Fixed a memory leak for Cython disasm functions when we immaturely quit - the enumeration of disassembled instructions. -- Fix a NULL memory access issue when SKIPDATA & Detail modes are enable - at the same time. -- Fix a memory leaking bug when when we stop enumeration over the disassembled - instructions prematurely. -- Export generic operand types & groups (CS_OP_xxx & CS_GRP_xxx). - --------------------------------- Version 3.0.5: July 18th, 2018 From a0cdd0bfbe724ec5ff58eff495219d1ee5b67284 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Tue, 18 Dec 2018 22:25:39 +0800 Subject: [PATCH 3/6] ChangeLog for v4.0 --- ChangeLog | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/ChangeLog b/ChangeLog index 2bfee9da..7dbd3d11 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,5 +1,56 @@ This file details the changelog of Capstone. +--------------------------------- +Version 4.0: December 18th, 2018 + + +[ Core ] + +- New APIs: cs_regs_access() +- Add new options for cs_option(): CS_OPT_MNEMONIC & CS_OPT_UNSIGNED & CS_OPT_SYNTAX_MASM. +- Various updates & bugfixes for all architectures. +- Add 4 new architectures: EVM, M68K, M680X & TMS320C64x. +- Add new group types: CS_GRP_PRIVILEGE & CS_GRP_BRANCH_RELATIVE. +- Add new error types: CS_ERR_X86_MASM. + + +[ X86 ] + +- Add XOP code condition type in x86_xop_cc. +- Add some info on encoding to cs_x86 in cs_x86_encoding. +- Add register flags update in cs_x86.{eflags, fpu_flags} +- Change cs_x86.disp type from int32_t to int64_t. +- Add new groups: X86_GRP_VM & X86_GRP_FPU. +- Lots of new instructions (AVX) + + +[ ARM64 ] + +- Add instruction ARM64_INS_NEGS & ARM64_INS_NGCS. + + +[ Mips ] + +- Add mode CS_MODE_MIPS2. + + +[ PPC ] + +- Change cs_ppc_op.imm type from int32_t to int64_t. +- Add new groups: PPC_GRP_ICBT, PPC_GRP_P8ALTIVEC, PPC_GRP_P8VECTOR & PPC_GRP_QPX. +- Lots of new instructions (QPX among them) + + +[ Sparc ] + +- Change cs_sparc_op.imm type from int32_t to int64_t. + + +[ Binding ] + +- New bindings: PowerShell & VB6 + + --------------------------------- Version 3.0.5: July 18th, 2018 From 31b7acde26dff013f366ab32f06b30807b738f33 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Tue, 18 Dec 2018 22:33:00 +0800 Subject: [PATCH 4/6] M680X: lowercase for instruction mnemonics & group names --- arch/M680X/M680XInstPrinter.c | 138 +++++++++++++++++----------------- 1 file changed, 69 insertions(+), 69 deletions(-) diff --git a/arch/M680X/M680XInstPrinter.c b/arch/M680X/M680XInstPrinter.c index 23f4cb5d..fc4e910d 100644 --- a/arch/M680X/M680XInstPrinter.c +++ b/arch/M680X/M680XInstPrinter.c @@ -22,79 +22,79 @@ static const char s_reg_names[][10] = { }; static const char s_instruction_names[][6] = { - "INVLD", "ABA", "ABX", "ABY", "ADC", "ADCA", "ADCB", "ADCD", "ADCR", - "ADD", "ADDA", "ADDB", "ADDD", "ADDE", "ADDF", "ADDR", "ADDW", - "AIM", "AIS", "AIX", "AND", "ANDA", "ANDB", "ANDCC", "ANDD", "ANDR", - "ASL", "ASLA", "ASLB", "ASLD", - "ASR", "ASRA", "ASRB", "ASRD", "ASRX", - "BAND", - "BCC", "BCLR", "BCS", "BEOR", "BEQ", "BGE", "BGND", "BGT", "BHCC", - "BHCS", "BHI", - "BIAND", "BIEOR", "BIH", "BIL", - "BIOR", "BIT", "BITA", "BITB", "BITD", "BITMD", "BLE", "BLS", "BLT", - "BMC", - "BMI", "BMS", - "BNE", "BOR", "BPL", "BRCLR", "BRSET", "BRA", "BRN", "BSET", "BSR", - "BVC", "BVS", - "CALL", "CBA", "CBEQ", "CBEQA", "CBEQX", "CLC", "CLI", - "CLR", "CLRA", "CLRB", "CLRD", "CLRE", "CLRF", "CLRH", "CLRW", "CLRX", - "CLV", "CMP", - "CMPA", "CMPB", "CMPD", "CMPE", "CMPF", "CMPR", "CMPS", "CMPU", "CMPW", - "CMPX", "CMPY", - "COM", "COMA", "COMB", "COMD", "COME", "COMF", "COMW", "COMX", "CPD", - "CPHX", "CPS", "CPX", "CPY", - "CWAI", "DAA", "DBEQ", "DBNE", "DBNZ", "DBNZA", "DBNZX", - "DEC", "DECA", "DECB", "DECD", "DECE", "DECF", "DECW", - "DECX", "DES", "DEX", "DEY", - "DIV", "DIVD", "DIVQ", "EDIV", "EDIVS", "EIM", "EMACS", "EMAXD", - "EMAXM", "EMIND", "EMINM", "EMUL", "EMULS", - "EOR", "EORA", "EORB", "EORD", "EORR", "ETBL", - "EXG", "FDIV", "IBEQ", "IBNE", "IDIV", "IDIVS", "ILLGL", - "INC", "INCA", "INCB", "INCD", "INCE", "INCF", "INCW", "INCX", - "INS", "INX", "INY", - "JMP", "JSR", - "LBCC", "LBCS", "LBEQ", "LBGE", "LBGT", "LBHI", "LBLE", "LBLS", "LBLT", - "LBMI", "LBNE", "LBPL", "LBRA", "LBRN", "LBSR", "LBVC", "LBVS", - "LDA", "LDAA", "LDAB", "LDB", "LDBT", "LDD", "LDE", "LDF", "LDHX", - "LDMD", - "LDQ", "LDS", "LDU", "LDW", "LDX", "LDY", - "LEAS", "LEAU", "LEAX", "LEAY", - "LSL", "LSLA", "LSLB", "LSLD", "LSLX", - "LSR", "LSRA", "LSRB", "LSRD", "LSRW", "LSRX", - "MAXA", "MAXM", "MEM", "MINA", "MINM", "MOV", "MOVB", "MOVW", "MUL", - "MULD", - "NEG", "NEGA", "NEGB", "NEGD", "NEGX", - "NOP", "NSA", "OIM", "ORA", "ORAA", "ORAB", "ORB", "ORCC", "ORD", "ORR", - "PSHA", "PSHB", "PSHC", "PSHD", "PSHH", "PSHS", "PSHSW", "PSHU", - "PSHUW", "PSHX", "PSHY", - "PULA", "PULB", "PULC", "PULD", "PULH", "PULS", "PULSW", "PULU", - "PULUW", "PULX", "PULY", "REV", "REVW", - "ROL", "ROLA", "ROLB", "ROLD", "ROLW", "ROLX", - "ROR", "RORA", "RORB", "RORD", "RORW", "RORX", - "RSP", "RTC", "RTI", "RTS", "SBA", "SBC", "SBCA", "SBCB", "SBCD", - "SBCR", - "SEC", "SEI", "SEV", "SEX", "SEXW", "SLP", "STA", "STAA", "STAB", "STB", - "STBT", "STD", "STE", "STF", "STOP", "STHX", - "STQ", "STS", "STU", "STW", "STX", "STY", - "SUB", "SUBA", "SUBB", "SUBD", "SUBE", "SUBF", "SUBR", "SUBW", - "SWI", "SWI2", "SWI3", - "SYNC", "TAB", "TAP", "TAX", "TBA", "TBEQ", "TBL", "TBNE", "TEST", - "TFM", "TFR", - "TIM", "TPA", - "TST", "TSTA", "TSTB", "TSTD", "TSTE", "TSTF", "TSTW", "TSTX", - "TSX", "TSY", "TXA", "TXS", "TYS", "WAI", "WAIT", "WAV", "WAVR", - "XGDX", "XGDY", + "invld", "aba", "abx", "aby", "adc", "adca", "adcb", "adcd", "adcr", + "add", "adda", "addb", "addd", "adde", "addf", "addr", "addw", + "aim", "ais", "aix", "and", "anda", "andb", "andcc", "andd", "andr", + "asl", "asla", "aslb", "asld", + "asr", "asra", "asrb", "asrd", "asrx", + "band", + "bcc", "bclr", "bcs", "beor", "beq", "bge", "bgnd", "bgt", "bhcc", + "bhcs", "bhi", + "biand", "bieor", "bih", "bil", + "bior", "bit", "bita", "bitb", "bitd", "bitmd", "ble", "bls", "blt", + "bmc", + "bmi", "bms", + "bne", "bor", "bpl", "brclr", "brset", "bra", "brn", "bset", "bsr", + "bvc", "bvs", + "call", "cba", "cbeq", "cbeqa", "cbeqx", "clc", "cli", + "clr", "clra", "clrb", "clrd", "clre", "clrf", "clrh", "clrw", "clrx", + "clv", "cmp", + "cmpa", "cmpb", "cmpd", "cmpe", "cmpf", "cmpr", "cmps", "cmpu", "cmpw", + "cmpx", "cmpy", + "com", "coma", "comb", "comd", "come", "comf", "comw", "comx", "cpd", + "cphx", "cps", "cpx", "cpy", + "cwai", "daa", "dbeq", "dbne", "dbnz", "dbnza", "dbnzx", + "dec", "deca", "decb", "decd", "dece", "decf", "decw", + "decx", "des", "dex", "dey", + "div", "divd", "divq", "ediv", "edivs", "eim", "emacs", "emaxd", + "emaxm", "emind", "eminm", "emul", "emuls", + "eor", "eora", "eorb", "eord", "eorr", "etbl", + "exg", "fdiv", "ibeq", "ibne", "idiv", "idivs", "illgl", + "inc", "inca", "incb", "incd", "ince", "incf", "incw", "incx", + "ins", "inx", "iny", + "jmp", "jsr", + "lbcc", "lbcs", "lbeq", "lbge", "lbgt", "lbhi", "lble", "lbls", "lblt", + "lbmi", "lbne", "lbpl", "lbra", "lbrn", "lbsr", "lbvc", "lbvs", + "lda", "ldaa", "ldab", "ldb", "ldbt", "ldd", "lde", "ldf", "ldhx", + "ldmd", + "ldq", "lds", "ldu", "ldw", "ldx", "ldy", + "leas", "leau", "leax", "leay", + "lsl", "lsla", "lslb", "lsld", "lslx", + "lsr", "lsra", "lsrb", "lsrd", "lsrw", "lsrx", + "maxa", "maxm", "mem", "mina", "minm", "mov", "movb", "movw", "mul", + "muld", + "neg", "nega", "negb", "negd", "negx", + "nop", "nsa", "oim", "ora", "oraa", "orab", "orb", "orcc", "ord", "orr", + "psha", "pshb", "pshc", "pshd", "pshh", "pshs", "pshsw", "pshu", + "pshuw", "pshx", "pshy", + "pula", "pulb", "pulc", "puld", "pulh", "puls", "pulsw", "pulu", + "puluw", "pulx", "puly", "rev", "revw", + "rol", "rola", "rolb", "rold", "rolw", "rolx", + "ror", "rora", "rorb", "rord", "rorw", "rorx", + "rsp", "rtc", "rti", "rts", "sba", "sbc", "sbca", "sbcb", "sbcd", + "sbcr", + "sec", "sei", "sev", "sex", "sexw", "slp", "sta", "staa", "stab", "stb", + "stbt", "std", "ste", "stf", "stop", "sthx", + "stq", "sts", "stu", "stw", "stx", "sty", + "sub", "suba", "subb", "subd", "sube", "subf", "subr", "subw", + "swi", "swi2", "swi3", + "sync", "tab", "tap", "tax", "tba", "tbeq", "tbl", "tbne", "test", + "tfm", "tfr", + "tim", "tpa", + "tst", "tsta", "tstb", "tstd", "tste", "tstf", "tstw", "tstx", + "tsx", "tsy", "txa", "txs", "tys", "wai", "wait", "wav", "wavr", + "xgdx", "xgdy", }; static name_map s_group_names[] = { { M680X_GRP_INVALID, "" }, - { M680X_GRP_JUMP, "JUMP" }, - { M680X_GRP_CALL, "CALL" }, - { M680X_GRP_RET, "RETURN" }, - { M680X_GRP_INT, "INTERRUPT" }, - { M680X_GRP_IRET, "INTERRUPT_RETURN" }, - { M680X_GRP_PRIV, "PRIVILEGED" }, - { M680X_GRP_BRAREL, "BRANCH_RELATIVE" }, + { M680X_GRP_JUMP, "jump" }, + { M680X_GRP_CALL, "call" }, + { M680X_GRP_RET, "return" }, + { M680X_GRP_INT, "interrupt" }, + { M680X_GRP_IRET, "interrupt_return" }, + { M680X_GRP_PRIV, "privileged" }, + { M680X_GRP_BRAREL, "branch_relative" }, }; #endif From 290828fc31df2ef60edd489df40af895907bae21 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Tue, 18 Dec 2018 22:40:31 +0800 Subject: [PATCH 5/6] TMS320C64x: lowercase for instruction mnemonics, registers & group names --- arch/TMS320C64x/TMS320C64xGenAsmWriter.inc | 434 ++++++++++----------- arch/TMS320C64x/TMS320C64xMapping.c | 178 ++++----- 2 files changed, 306 insertions(+), 306 deletions(-) diff --git a/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc b/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc index bc5456b7..70dd72a7 100644 --- a/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc +++ b/arch/TMS320C64x/TMS320C64xGenAsmWriter.inc @@ -296,137 +296,137 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { }; static char AsmStrs[] = { - /* 0 */ 'N', 'O', 'P', 9, 9, 0, - /* 6 */ 'S', 'U', 'B', '2', 9, 0, - /* 12 */ 'S', 'A', 'D', 'D', '2', 9, 0, - /* 19 */ 'X', 'P', 'N', 'D', '2', 9, 0, - /* 26 */ 'A', 'V', 'G', '2', 9, 0, - /* 32 */ 'P', 'A', 'C', 'K', 'H', '2', 9, 0, - /* 40 */ 'P', 'A', 'C', 'K', 'L', 'H', '2', 9, 0, - /* 49 */ 'S', 'P', 'A', 'C', 'K', '2', 9, 0, - /* 57 */ 'P', 'A', 'C', 'K', 'H', 'L', '2', 9, 0, - /* 66 */ 'M', 'I', 'N', '2', 9, 0, - /* 72 */ 'D', 'O', 'T', 'P', 'N', '2', 9, 0, - /* 80 */ 'D', 'O', 'T', 'P', '2', 9, 0, - /* 87 */ 'C', 'M', 'P', 'E', 'Q', '2', 9, 0, - /* 95 */ 'S', 'H', 'R', '2', 9, 0, - /* 101 */ 'A', 'B', 'S', '2', 9, 0, - /* 107 */ 'S', 'A', 'D', 'D', 'U', 'S', '2', 9, 0, - /* 116 */ 'C', 'M', 'P', 'G', 'T', '2', 9, 0, - /* 124 */ 'S', 'H', 'R', 'U', '2', 9, 0, - /* 131 */ 'D', 'O', 'T', 'P', 'N', 'R', 'S', 'U', '2', 9, 0, - /* 142 */ 'D', 'O', 'T', 'P', 'R', 'S', 'U', '2', 9, 0, - /* 152 */ 'M', 'A', 'X', '2', 9, 0, - /* 158 */ 'S', 'M', 'P', 'Y', '2', 9, 0, - /* 165 */ 'S', 'U', 'B', '4', 9, 0, - /* 171 */ 'B', 'I', 'T', 'C', '4', 9, 0, - /* 178 */ 'A', 'D', 'D', '4', 9, 0, - /* 184 */ 'X', 'P', 'N', 'D', '4', 9, 0, - /* 191 */ 'P', 'A', 'C', 'K', 'H', '4', 9, 0, - /* 199 */ 'P', 'A', 'C', 'K', 'L', '4', 9, 0, - /* 207 */ 'S', 'W', 'A', 'P', '4', 9, 0, - /* 214 */ 'C', 'M', 'P', 'E', 'Q', '4', 9, 0, - /* 222 */ 'S', 'U', 'B', 'A', 'B', 'S', '4', 9, 0, - /* 231 */ 'S', 'A', 'D', 'D', 'U', '4', 9, 0, - /* 239 */ 'A', 'V', 'G', 'U', '4', 9, 0, - /* 246 */ 'U', 'N', 'P', 'K', 'H', 'U', '4', 9, 0, - /* 255 */ 'S', 'P', 'A', 'C', 'K', 'U', '4', 9, 0, - /* 264 */ 'U', 'N', 'P', 'K', 'L', 'U', '4', 9, 0, - /* 273 */ 'M', 'I', 'N', 'U', '4', 9, 0, - /* 280 */ 'D', 'O', 'T', 'P', 'U', '4', 9, 0, - /* 288 */ 'D', 'O', 'T', 'P', 'S', 'U', '4', 9, 0, - /* 297 */ 'M', 'P', 'Y', 'S', 'U', '4', 9, 0, - /* 305 */ 'C', 'M', 'P', 'G', 'T', 'U', '4', 9, 0, - /* 314 */ 'M', 'A', 'X', 'U', '4', 9, 0, - /* 321 */ 'M', 'P', 'Y', 'U', '4', 9, 0, - /* 328 */ 'G', 'M', 'P', 'Y', '4', 9, 0, - /* 335 */ 'S', 'U', 'B', 'A', 'B', 9, 0, - /* 342 */ 'A', 'D', 'D', 'A', 'B', 9, 0, - /* 349 */ 'L', 'D', 'B', 9, 0, - /* 354 */ 'S', 'H', 'L', 'M', 'B', 9, 0, - /* 361 */ 'S', 'H', 'R', 'M', 'B', 9, 0, - /* 368 */ 'S', 'T', 'B', 9, 0, - /* 373 */ 'S', 'S', 'U', 'B', 9, 0, - /* 379 */ 'S', 'U', 'B', 'C', 9, 0, - /* 385 */ 'B', 'D', 'E', 'C', 9, 0, - /* 391 */ 'A', 'D', 'D', 'K', 'P', 'C', 9, 0, - /* 399 */ 'M', 'V', 'C', 9, 0, - /* 404 */ 'A', 'D', 'D', 'A', 'D', 9, 0, - /* 411 */ 'L', 'M', 'B', 'D', 9, 0, - /* 417 */ 'S', 'A', 'D', 'D', 9, 0, - /* 423 */ 'A', 'N', 'D', 9, 0, - /* 428 */ 'M', 'V', 'D', 9, 0, - /* 433 */ 'S', 'U', 'B', 'A', 'H', 9, 0, - /* 440 */ 'A', 'D', 'D', 'A', 'H', 9, 0, - /* 447 */ 'L', 'D', 'H', 9, 0, - /* 452 */ 'M', 'V', 'K', 'L', 'H', 9, 0, - /* 459 */ 'S', 'M', 'P', 'Y', 'L', 'H', 9, 0, - /* 467 */ 'S', 'T', 'H', 9, 0, - /* 472 */ 'S', 'M', 'P', 'Y', 'H', 9, 0, - /* 479 */ 'M', 'P', 'Y', 'H', 'I', 9, 0, - /* 486 */ 'M', 'P', 'Y', 'L', 'I', 9, 0, - /* 493 */ 'A', 'D', 'D', 'K', 9, 0, - /* 499 */ 'M', 'V', 'K', 9, 0, - /* 504 */ 'D', 'E', 'A', 'L', 9, 0, - /* 510 */ 'S', 'H', 'F', 'L', 9, 0, - /* 516 */ 'S', 'S', 'H', 'L', 9, 0, - /* 522 */ 'S', 'M', 'P', 'Y', 'H', 'L', 9, 0, - /* 530 */ 'R', 'O', 'T', 'L', 9, 0, - /* 536 */ 'S', 'S', 'H', 'V', 'L', 9, 0, - /* 543 */ 'N', 'O', 'R', 'M', 9, 0, - /* 549 */ 'A', 'N', 'D', 'N', 9, 0, - /* 555 */ 'B', 'N', 'O', 'P', 9, 0, - /* 561 */ 'C', 'M', 'P', 'E', 'Q', 9, 0, - /* 568 */ 'S', 'H', 'R', 9, 0, - /* 573 */ 'M', 'P', 'Y', 'H', 'I', 'R', 9, 0, - /* 581 */ 'M', 'P', 'Y', 'L', 'I', 'R', 9, 0, - /* 589 */ 'C', 'L', 'R', 9, 0, - /* 594 */ 'X', 'O', 'R', 9, 0, - /* 599 */ 'S', 'S', 'H', 'V', 'R', 9, 0, - /* 606 */ 'A', 'B', 'S', 9, 0, - /* 611 */ 'M', 'P', 'Y', 'L', 'U', 'H', 'S', 9, 0, - /* 620 */ 'M', 'P', 'Y', 'H', 'U', 'L', 'S', 9, 0, - /* 629 */ 'B', 'P', 'O', 'S', 9, 0, - /* 635 */ 'M', 'P', 'Y', 'H', 'U', 'S', 9, 0, - /* 643 */ 'M', 'P', 'Y', 'U', 'S', 9, 0, - /* 650 */ 'S', 'A', 'T', 9, 0, - /* 655 */ 'S', 'E', 'T', 9, 0, - /* 660 */ 'C', 'M', 'P', 'G', 'T', 9, 0, - /* 667 */ 'C', 'M', 'P', 'L', 'T', 9, 0, - /* 674 */ 'E', 'X', 'T', 9, 0, - /* 679 */ 'L', 'D', 'B', 'U', 9, 0, - /* 685 */ 'S', 'U', 'B', 'U', 9, 0, - /* 691 */ 'A', 'D', 'D', 'U', 9, 0, - /* 697 */ 'L', 'D', 'H', 'U', 9, 0, - /* 703 */ 'M', 'P', 'Y', 'L', 'H', 'U', 9, 0, - /* 711 */ 'M', 'P', 'Y', 'L', 'S', 'H', 'U', 9, 0, - /* 720 */ 'M', 'P', 'Y', 'H', 'U', 9, 0, - /* 727 */ 'M', 'P', 'Y', 'H', 'L', 'U', 9, 0, - /* 735 */ 'M', 'P', 'Y', 'H', 'S', 'L', 'U', 9, 0, - /* 744 */ 'S', 'H', 'R', 'U', 9, 0, - /* 750 */ 'M', 'P', 'Y', 'H', 'S', 'U', 9, 0, - /* 758 */ 'M', 'P', 'Y', 'S', 'U', 9, 0, - /* 765 */ 'C', 'M', 'P', 'G', 'T', 'U', 9, 0, - /* 773 */ 'C', 'M', 'P', 'L', 'T', 'U', 9, 0, - /* 781 */ 'E', 'X', 'T', 'U', 9, 0, - /* 787 */ 'M', 'P', 'Y', 'U', 9, 0, - /* 793 */ 'S', 'U', 'B', 'A', 'W', 9, 0, - /* 800 */ 'A', 'D', 'D', 'A', 'W', 9, 0, - /* 807 */ 'L', 'D', 'D', 'W', 9, 0, - /* 813 */ 'L', 'D', 'W', 9, 0, - /* 818 */ 'L', 'D', 'N', 'D', 'W', 9, 0, - /* 825 */ 'S', 'T', 'N', 'D', 'W', 9, 0, - /* 832 */ 'S', 'T', 'D', 'W', 9, 0, - /* 838 */ 'L', 'D', 'N', 'W', 9, 0, - /* 844 */ 'S', 'T', 'N', 'W', 9, 0, - /* 850 */ 'S', 'T', 'W', 9, 0, - /* 855 */ 'S', 'M', 'P', 'Y', 9, 0, - /* 861 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'E', 'N', 'D', 0, - /* 874 */ 'B', 'U', 'N', 'D', 'L', 'E', 0, - /* 881 */ 'D', 'B', 'G', '_', 'V', 'A', 'L', 'U', 'E', 0, - /* 891 */ 'B', 9, 'I', 'R', 'P', 0, - /* 897 */ 'B', 9, 'N', 'R', 'P', 0, - /* 903 */ 'L', 'I', 'F', 'E', 'T', 'I', 'M', 'E', '_', 'S', 'T', 'A', 'R', 'T', 0, + /* 0 */ 'n', 'o', 'p', 9, 9, 0, + /* 6 */ 's', 'u', 'b', '2', 9, 0, + /* 12 */ 's', 'a', 'd', 'd', '2', 9, 0, + /* 19 */ 'x', 'p', 'n', 'd', '2', 9, 0, + /* 26 */ 'a', 'v', 'g', '2', 9, 0, + /* 32 */ 'p', 'a', 'c', 'k', 'h', '2', 9, 0, + /* 40 */ 'p', 'a', 'c', 'k', 'l', 'h', '2', 9, 0, + /* 49 */ 's', 'p', 'a', 'c', 'k', '2', 9, 0, + /* 57 */ 'p', 'a', 'c', 'k', 'h', 'l', '2', 9, 0, + /* 66 */ 'm', 'i', 'n', '2', 9, 0, + /* 72 */ 'd', 'o', 't', 'p', 'n', '2', 9, 0, + /* 80 */ 'd', 'o', 't', 'p', '2', 9, 0, + /* 87 */ 'c', 'm', 'p', 'e', 'q', '2', 9, 0, + /* 95 */ 's', 'h', 'r', '2', 9, 0, + /* 101 */ 'a', 'b', 's', '2', 9, 0, + /* 107 */ 's', 'a', 'd', 'd', 'u', 's', '2', 9, 0, + /* 116 */ 'c', 'm', 'p', 'g', 't', '2', 9, 0, + /* 124 */ 's', 'h', 'r', 'u', '2', 9, 0, + /* 131 */ 'd', 'o', 't', 'p', 'n', 'r', 's', 'u', '2', 9, 0, + /* 142 */ 'd', 'o', 't', 'p', 'r', 's', 'u', '2', 9, 0, + /* 152 */ 'm', 'a', 'x', '2', 9, 0, + /* 158 */ 's', 'm', 'p', 'y', '2', 9, 0, + /* 165 */ 's', 'u', 'b', '4', 9, 0, + /* 171 */ 'b', 'i', 't', 'c', '4', 9, 0, + /* 178 */ 'a', 'd', 'd', '4', 9, 0, + /* 184 */ 'x', 'p', 'n', 'd', '4', 9, 0, + /* 191 */ 'p', 'a', 'c', 'k', 'h', '4', 9, 0, + /* 199 */ 'p', 'a', 'c', 'k', 'l', '4', 9, 0, + /* 207 */ 's', 'w', 'a', 'p', '4', 9, 0, + /* 214 */ 'c', 'm', 'p', 'e', 'q', '4', 9, 0, + /* 222 */ 's', 'u', 'b', 'a', 'b', 's', '4', 9, 0, + /* 231 */ 's', 'a', 'd', 'd', 'u', '4', 9, 0, + /* 239 */ 'a', 'v', 'g', 'u', '4', 9, 0, + /* 246 */ 'u', 'n', 'p', 'k', 'h', 'u', '4', 9, 0, + /* 255 */ 's', 'p', 'a', 'c', 'k', 'u', '4', 9, 0, + /* 264 */ 'u', 'n', 'p', 'k', 'l', 'u', '4', 9, 0, + /* 273 */ 'm', 'i', 'n', 'u', '4', 9, 0, + /* 280 */ 'd', 'o', 't', 'p', 'u', '4', 9, 0, + /* 288 */ 'd', 'o', 't', 'p', 's', 'u', '4', 9, 0, + /* 297 */ 'm', 'p', 'y', 's', 'u', '4', 9, 0, + /* 305 */ 'c', 'm', 'p', 'g', 't', 'u', '4', 9, 0, + /* 314 */ 'm', 'a', 'x', 'u', '4', 9, 0, + /* 321 */ 'm', 'p', 'y', 'u', '4', 9, 0, + /* 328 */ 'g', 'm', 'p', 'y', '4', 9, 0, + /* 335 */ 's', 'u', 'b', 'a', 'b', 9, 0, + /* 342 */ 'a', 'd', 'd', 'a', 'b', 9, 0, + /* 349 */ 'l', 'd', 'b', 9, 0, + /* 354 */ 's', 'h', 'l', 'm', 'b', 9, 0, + /* 361 */ 's', 'h', 'r', 'm', 'b', 9, 0, + /* 368 */ 's', 't', 'b', 9, 0, + /* 373 */ 's', 's', 'u', 'b', 9, 0, + /* 379 */ 's', 'u', 'b', 'c', 9, 0, + /* 385 */ 'b', 'd', 'e', 'c', 9, 0, + /* 391 */ 'a', 'd', 'd', 'k', 'p', 'c', 9, 0, + /* 399 */ 'm', 'v', 'c', 9, 0, + /* 404 */ 'a', 'd', 'd', 'a', 'd', 9, 0, + /* 411 */ 'l', 'm', 'b', 'd', 9, 0, + /* 417 */ 's', 'a', 'd', 'd', 9, 0, + /* 423 */ 'a', 'n', 'd', 9, 0, + /* 428 */ 'm', 'v', 'd', 9, 0, + /* 433 */ 's', 'u', 'b', 'a', 'h', 9, 0, + /* 440 */ 'a', 'd', 'd', 'a', 'h', 9, 0, + /* 447 */ 'l', 'd', 'h', 9, 0, + /* 452 */ 'm', 'v', 'k', 'l', 'h', 9, 0, + /* 459 */ 's', 'm', 'p', 'y', 'l', 'h', 9, 0, + /* 467 */ 's', 't', 'h', 9, 0, + /* 472 */ 's', 'm', 'p', 'y', 'h', 9, 0, + /* 479 */ 'm', 'p', 'y', 'h', 'i', 9, 0, + /* 486 */ 'm', 'p', 'y', 'l', 'i', 9, 0, + /* 493 */ 'a', 'd', 'd', 'k', 9, 0, + /* 499 */ 'm', 'v', 'k', 9, 0, + /* 504 */ 'd', 'e', 'a', 'l', 9, 0, + /* 510 */ 's', 'h', 'f', 'l', 9, 0, + /* 516 */ 's', 's', 'h', 'l', 9, 0, + /* 522 */ 's', 'm', 'p', 'y', 'h', 'l', 9, 0, + /* 530 */ 'r', 'o', 't', 'l', 9, 0, + /* 536 */ 's', 's', 'h', 'v', 'l', 9, 0, + /* 543 */ 'n', 'o', 'r', 'm', 9, 0, + /* 549 */ 'a', 'n', 'd', 'n', 9, 0, + /* 555 */ 'b', 'n', 'o', 'p', 9, 0, + /* 561 */ 'c', 'm', 'p', 'e', 'q', 9, 0, + /* 568 */ 's', 'h', 'r', 9, 0, + /* 573 */ 'm', 'p', 'y', 'h', 'i', 'r', 9, 0, + /* 581 */ 'm', 'p', 'y', 'l', 'i', 'r', 9, 0, + /* 589 */ 'c', 'l', 'r', 9, 0, + /* 594 */ 'x', 'o', 'r', 9, 0, + /* 599 */ 's', 's', 'h', 'v', 'r', 9, 0, + /* 606 */ 'a', 'b', 's', 9, 0, + /* 611 */ 'm', 'p', 'y', 'l', 'u', 'h', 's', 9, 0, + /* 620 */ 'm', 'p', 'y', 'h', 'u', 'l', 's', 9, 0, + /* 629 */ 'b', 'p', 'o', 's', 9, 0, + /* 635 */ 'm', 'p', 'y', 'h', 'u', 's', 9, 0, + /* 643 */ 'm', 'p', 'y', 'u', 's', 9, 0, + /* 650 */ 's', 'a', 't', 9, 0, + /* 655 */ 's', 'e', 't', 9, 0, + /* 660 */ 'c', 'm', 'p', 'g', 't', 9, 0, + /* 667 */ 'c', 'm', 'p', 'l', 't', 9, 0, + /* 674 */ 'e', 'x', 't', 9, 0, + /* 679 */ 'l', 'd', 'b', 'u', 9, 0, + /* 685 */ 's', 'u', 'b', 'u', 9, 0, + /* 691 */ 'a', 'd', 'd', 'u', 9, 0, + /* 697 */ 'l', 'd', 'h', 'u', 9, 0, + /* 703 */ 'm', 'p', 'y', 'l', 'h', 'u', 9, 0, + /* 711 */ 'm', 'p', 'y', 'l', 's', 'h', 'u', 9, 0, + /* 720 */ 'm', 'p', 'y', 'h', 'u', 9, 0, + /* 727 */ 'm', 'p', 'y', 'h', 'l', 'u', 9, 0, + /* 735 */ 'm', 'p', 'y', 'h', 's', 'l', 'u', 9, 0, + /* 744 */ 's', 'h', 'r', 'u', 9, 0, + /* 750 */ 'm', 'p', 'y', 'h', 's', 'u', 9, 0, + /* 758 */ 'm', 'p', 'y', 's', 'u', 9, 0, + /* 765 */ 'c', 'm', 'p', 'g', 't', 'u', 9, 0, + /* 773 */ 'c', 'm', 'p', 'l', 't', 'u', 9, 0, + /* 781 */ 'e', 'x', 't', 'u', 9, 0, + /* 787 */ 'm', 'p', 'y', 'u', 9, 0, + /* 793 */ 's', 'u', 'b', 'a', 'w', 9, 0, + /* 800 */ 'a', 'd', 'd', 'a', 'w', 9, 0, + /* 807 */ 'l', 'd', 'd', 'w', 9, 0, + /* 813 */ 'l', 'd', 'w', 9, 0, + /* 818 */ 'l', 'd', 'n', 'd', 'w', 9, 0, + /* 825 */ 's', 't', 'n', 'd', 'w', 9, 0, + /* 832 */ 's', 't', 'd', 'w', 9, 0, + /* 838 */ 'l', 'd', 'n', 'w', 9, 0, + /* 844 */ 's', 't', 'n', 'w', 9, 0, + /* 850 */ 's', 't', 'w', 9, 0, + /* 855 */ 's', 'm', 'p', 'y', 9, 0, + /* 861 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 'e', 'n', 'd', 0, + /* 874 */ 'b', 'u', 'n', 'd', 'l', 'e', 0, + /* 881 */ 'd', 'b', 'g', '_', 'v', 'a', 'l', 'u', 'e', 0, + /* 891 */ 'b', 9, 'i', 'r', 'p', 0, + /* 897 */ 'b', 9, 'n', 'r', 'p', 0, + /* 903 */ 'l', 'i', 'f', 'e', 't', 'i', 'm', 'e', '_', 's', 't', 'a', 'r', 't', 0, }; // Emit the opcode for the instruction. @@ -579,92 +579,92 @@ static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI) { static char *getRegisterName(unsigned RegNo) { #ifndef CAPSTONE_DIET static char AsmStrs[] = { - /* 0 */ 'A', '1', '0', 0, - /* 4 */ 'B', '1', '0', 0, - /* 8 */ 'A', '2', '0', 0, - /* 12 */ 'B', '2', '0', 0, - /* 16 */ 'A', '3', '0', 0, - /* 20 */ 'B', '3', '0', 0, - /* 24 */ 'A', '0', 0, - /* 27 */ 'B', '0', 0, - /* 30 */ 'A', '1', '1', 0, - /* 34 */ 'B', '1', '1', 0, - /* 38 */ 'A', '2', '1', 0, - /* 42 */ 'B', '2', '1', 0, - /* 46 */ 'A', '3', '1', 0, - /* 50 */ 'B', '3', '1', 0, - /* 54 */ 'A', '1', 0, - /* 57 */ 'B', '1', 0, - /* 60 */ 'P', 'C', 'E', '1', 0, - /* 65 */ 'A', '1', '2', 0, - /* 69 */ 'B', '1', '2', 0, - /* 73 */ 'A', '2', '2', 0, - /* 77 */ 'B', '2', '2', 0, - /* 81 */ 'A', '2', 0, - /* 84 */ 'B', '2', 0, - /* 87 */ 'A', '1', '3', 0, - /* 91 */ 'B', '1', '3', 0, - /* 95 */ 'A', '2', '3', 0, - /* 99 */ 'B', '2', '3', 0, - /* 103 */ 'A', '3', 0, - /* 106 */ 'B', '3', 0, - /* 109 */ 'A', '1', '4', 0, - /* 113 */ 'B', '1', '4', 0, - /* 117 */ 'A', '2', '4', 0, - /* 121 */ 'B', '2', '4', 0, - /* 125 */ 'A', '4', 0, - /* 128 */ 'B', '4', 0, - /* 131 */ 'A', '1', '5', 0, - /* 135 */ 'B', '1', '5', 0, - /* 139 */ 'A', '2', '5', 0, - /* 143 */ 'B', '2', '5', 0, - /* 147 */ 'A', '5', 0, - /* 150 */ 'B', '5', 0, - /* 153 */ 'A', '1', '6', 0, - /* 157 */ 'B', '1', '6', 0, - /* 161 */ 'A', '2', '6', 0, - /* 165 */ 'B', '2', '6', 0, - /* 169 */ 'A', '6', 0, - /* 172 */ 'B', '6', 0, - /* 175 */ 'A', '1', '7', 0, - /* 179 */ 'B', '1', '7', 0, - /* 183 */ 'A', '2', '7', 0, - /* 187 */ 'B', '2', '7', 0, - /* 191 */ 'A', '7', 0, - /* 194 */ 'B', '7', 0, - /* 197 */ 'A', '1', '8', 0, - /* 201 */ 'B', '1', '8', 0, - /* 205 */ 'A', '2', '8', 0, - /* 209 */ 'B', '2', '8', 0, - /* 213 */ 'A', '8', 0, - /* 216 */ 'B', '8', 0, - /* 219 */ 'A', '1', '9', 0, - /* 223 */ 'B', '1', '9', 0, - /* 227 */ 'A', '2', '9', 0, - /* 231 */ 'B', '2', '9', 0, - /* 235 */ 'A', '9', 0, - /* 238 */ 'B', '9', 0, - /* 241 */ 'G', 'P', 'L', 'Y', 'A', 0, - /* 247 */ 'G', 'P', 'L', 'Y', 'B', 0, - /* 253 */ 'R', 'I', 'L', 'C', 0, - /* 258 */ 'T', 'S', 'C', 'H', 0, - /* 263 */ 'T', 'S', 'C', 'L', 0, - /* 268 */ 'D', 'N', 'U', 'M', 0, - /* 273 */ 'R', 'E', 'P', 0, - /* 277 */ 'I', 'R', 'P', 0, - /* 281 */ 'N', 'R', 'P', 0, - /* 285 */ 'I', 'S', 'T', 'P', 0, - /* 290 */ 'E', 'C', 'R', 0, - /* 294 */ 'I', 'C', 'R', 0, - /* 298 */ 'D', 'I', 'E', 'R', 0, - /* 303 */ 'G', 'F', 'P', 'G', 'F', 'R', 0, - /* 310 */ 'A', 'M', 'R', 0, - /* 314 */ 'I', 'E', 'R', 'R', 0, - /* 319 */ 'C', 'S', 'R', 0, - /* 323 */ 'I', 'S', 'R', 0, - /* 327 */ 'S', 'S', 'R', 0, - /* 331 */ 'I', 'T', 'S', 'R', 0, - /* 336 */ 'N', 'T', 'S', 'R', 0, + /* 0 */ 'a', '1', '0', 0, + /* 4 */ 'b', '1', '0', 0, + /* 8 */ 'a', '2', '0', 0, + /* 12 */ 'b', '2', '0', 0, + /* 16 */ 'a', '3', '0', 0, + /* 20 */ 'b', '3', '0', 0, + /* 24 */ 'a', '0', 0, + /* 27 */ 'b', '0', 0, + /* 30 */ 'a', '1', '1', 0, + /* 34 */ 'b', '1', '1', 0, + /* 38 */ 'a', '2', '1', 0, + /* 42 */ 'b', '2', '1', 0, + /* 46 */ 'a', '3', '1', 0, + /* 50 */ 'b', '3', '1', 0, + /* 54 */ 'a', '1', 0, + /* 57 */ 'b', '1', 0, + /* 60 */ 'p', 'c', 'e', '1', 0, + /* 65 */ 'a', '1', '2', 0, + /* 69 */ 'b', '1', '2', 0, + /* 73 */ 'a', '2', '2', 0, + /* 77 */ 'b', '2', '2', 0, + /* 81 */ 'a', '2', 0, + /* 84 */ 'b', '2', 0, + /* 87 */ 'a', '1', '3', 0, + /* 91 */ 'b', '1', '3', 0, + /* 95 */ 'a', '2', '3', 0, + /* 99 */ 'b', '2', '3', 0, + /* 103 */ 'a', '3', 0, + /* 106 */ 'b', '3', 0, + /* 109 */ 'a', '1', '4', 0, + /* 113 */ 'b', '1', '4', 0, + /* 117 */ 'a', '2', '4', 0, + /* 121 */ 'b', '2', '4', 0, + /* 125 */ 'a', '4', 0, + /* 128 */ 'b', '4', 0, + /* 131 */ 'a', '1', '5', 0, + /* 135 */ 'b', '1', '5', 0, + /* 139 */ 'a', '2', '5', 0, + /* 143 */ 'b', '2', '5', 0, + /* 147 */ 'a', '5', 0, + /* 150 */ 'b', '5', 0, + /* 153 */ 'a', '1', '6', 0, + /* 157 */ 'b', '1', '6', 0, + /* 161 */ 'a', '2', '6', 0, + /* 165 */ 'b', '2', '6', 0, + /* 169 */ 'a', '6', 0, + /* 172 */ 'b', '6', 0, + /* 175 */ 'a', '1', '7', 0, + /* 179 */ 'b', '1', '7', 0, + /* 183 */ 'a', '2', '7', 0, + /* 187 */ 'b', '2', '7', 0, + /* 191 */ 'a', '7', 0, + /* 194 */ 'b', '7', 0, + /* 197 */ 'a', '1', '8', 0, + /* 201 */ 'b', '1', '8', 0, + /* 205 */ 'a', '2', '8', 0, + /* 209 */ 'b', '2', '8', 0, + /* 213 */ 'a', '8', 0, + /* 216 */ 'b', '8', 0, + /* 219 */ 'a', '1', '9', 0, + /* 223 */ 'b', '1', '9', 0, + /* 227 */ 'a', '2', '9', 0, + /* 231 */ 'b', '2', '9', 0, + /* 235 */ 'a', '9', 0, + /* 238 */ 'b', '9', 0, + /* 241 */ 'g', 'p', 'l', 'y', 'a', 0, + /* 247 */ 'g', 'p', 'l', 'y', 'b', 0, + /* 253 */ 'r', 'i', 'l', 'c', 0, + /* 258 */ 't', 's', 'c', 'h', 0, + /* 263 */ 't', 's', 'c', 'l', 0, + /* 268 */ 'd', 'n', 'u', 'm', 0, + /* 273 */ 'r', 'e', 'p', 0, + /* 277 */ 'i', 'r', 'p', 0, + /* 281 */ 'n', 'r', 'p', 0, + /* 285 */ 'i', 's', 't', 'p', 0, + /* 290 */ 'e', 'c', 'r', 0, + /* 294 */ 'i', 'c', 'r', 0, + /* 298 */ 'd', 'i', 'e', 'r', 0, + /* 303 */ 'g', 'f', 'p', 'g', 'f', 'r', 0, + /* 310 */ 'a', 'm', 'r', 0, + /* 314 */ 'i', 'e', 'r', 'r', 0, + /* 319 */ 'c', 's', 'r', 0, + /* 323 */ 'i', 's', 'r', 0, + /* 327 */ 's', 's', 'r', 0, + /* 331 */ 'i', 't', 's', 'r', 0, + /* 336 */ 'n', 't', 's', 'r', 0, }; static const uint16_t RegAsmOffset[] = { diff --git a/arch/TMS320C64x/TMS320C64xMapping.c b/arch/TMS320C64x/TMS320C64xMapping.c index 3a0223f4..26c89047 100644 --- a/arch/TMS320C64x/TMS320C64xMapping.c +++ b/arch/TMS320C64x/TMS320C64xMapping.c @@ -16,95 +16,95 @@ static name_map reg_name_maps[] = { { TMS320C64X_REG_INVALID, NULL }, - { TMS320C64X_REG_AMR, "AMR" }, - { TMS320C64X_REG_CSR, "CSR" }, - { TMS320C64X_REG_DIER, "DIER" }, - { TMS320C64X_REG_DNUM, "DNUM" }, - { TMS320C64X_REG_ECR, "ECR" }, - { TMS320C64X_REG_GFPGFR, "GFPGFR" }, - { TMS320C64X_REG_GPLYA, "GPLYA" }, - { TMS320C64X_REG_GPLYB, "GPLYB" }, - { TMS320C64X_REG_ICR, "ICR" }, - { TMS320C64X_REG_IER, "IER" }, - { TMS320C64X_REG_IERR, "IERR" }, - { TMS320C64X_REG_ILC, "ILC" }, - { TMS320C64X_REG_IRP, "IRP" }, - { TMS320C64X_REG_ISR, "ISR" }, - { TMS320C64X_REG_ISTP, "ISTP" }, - { TMS320C64X_REG_ITSR, "ITSR" }, - { TMS320C64X_REG_NRP, "NRP" }, - { TMS320C64X_REG_NTSR, "NTSR" }, - { TMS320C64X_REG_REP, "REP" }, - { TMS320C64X_REG_RILC, "RILC" }, - { TMS320C64X_REG_SSR, "SSR" }, - { TMS320C64X_REG_TSCH, "TSCH" }, - { TMS320C64X_REG_TSCL, "TSCL" }, - { TMS320C64X_REG_TSR, "TSR" }, - { TMS320C64X_REG_A0, "A0" }, - { TMS320C64X_REG_A1, "A1" }, - { TMS320C64X_REG_A2, "A2" }, - { TMS320C64X_REG_A3, "A3" }, - { TMS320C64X_REG_A4, "A4" }, - { TMS320C64X_REG_A5, "A5" }, - { TMS320C64X_REG_A6, "A6" }, - { TMS320C64X_REG_A7, "A7" }, - { TMS320C64X_REG_A8, "A8" }, - { TMS320C64X_REG_A9, "A9" }, - { TMS320C64X_REG_A10, "A10" }, - { TMS320C64X_REG_A11, "A11" }, - { TMS320C64X_REG_A12, "A12" }, - { TMS320C64X_REG_A13, "A13" }, - { TMS320C64X_REG_A14, "A14" }, - { TMS320C64X_REG_A15, "A15" }, - { TMS320C64X_REG_A16, "A16" }, - { TMS320C64X_REG_A17, "A17" }, - { TMS320C64X_REG_A18, "A18" }, - { TMS320C64X_REG_A19, "A19" }, - { TMS320C64X_REG_A20, "A20" }, - { TMS320C64X_REG_A21, "A21" }, - { TMS320C64X_REG_A22, "A22" }, - { TMS320C64X_REG_A23, "A23" }, - { TMS320C64X_REG_A24, "A24" }, - { TMS320C64X_REG_A25, "A25" }, - { TMS320C64X_REG_A26, "A26" }, - { TMS320C64X_REG_A27, "A27" }, - { TMS320C64X_REG_A28, "A28" }, - { TMS320C64X_REG_A29, "A29" }, - { TMS320C64X_REG_A30, "A30" }, - { TMS320C64X_REG_A31, "A31" }, - { TMS320C64X_REG_B0, "B0" }, - { TMS320C64X_REG_B1, "B1" }, - { TMS320C64X_REG_B2, "B2" }, - { TMS320C64X_REG_B3, "B3" }, - { TMS320C64X_REG_B4, "B4" }, - { TMS320C64X_REG_B5, "B5" }, - { TMS320C64X_REG_B6, "B6" }, - { TMS320C64X_REG_B7, "B7" }, - { TMS320C64X_REG_B8, "B8" }, - { TMS320C64X_REG_B9, "B9" }, - { TMS320C64X_REG_B10, "B10" }, - { TMS320C64X_REG_B11, "B11" }, - { TMS320C64X_REG_B12, "B12" }, - { TMS320C64X_REG_B13, "B13" }, - { TMS320C64X_REG_B14, "B14" }, - { TMS320C64X_REG_B15, "B15" }, - { TMS320C64X_REG_B16, "B16" }, - { TMS320C64X_REG_B17, "B17" }, - { TMS320C64X_REG_B18, "B18" }, - { TMS320C64X_REG_B19, "B19" }, - { TMS320C64X_REG_B20, "B20" }, - { TMS320C64X_REG_B21, "B21" }, - { TMS320C64X_REG_B22, "B22" }, - { TMS320C64X_REG_B23, "B23" }, - { TMS320C64X_REG_B24, "B24" }, - { TMS320C64X_REG_B25, "B25" }, - { TMS320C64X_REG_B26, "B26" }, - { TMS320C64X_REG_B27, "B27" }, - { TMS320C64X_REG_B28, "B28" }, - { TMS320C64X_REG_B29, "B29" }, - { TMS320C64X_REG_B30, "B30" }, - { TMS320C64X_REG_B31, "B31" }, - { TMS320C64X_REG_PCE1, "PCE1" }, + { TMS320C64X_REG_AMR, "amr" }, + { TMS320C64X_REG_CSR, "csr" }, + { TMS320C64X_REG_DIER, "dier" }, + { TMS320C64X_REG_DNUM, "dnum" }, + { TMS320C64X_REG_ECR, "ecr" }, + { TMS320C64X_REG_GFPGFR, "gfpgfr" }, + { TMS320C64X_REG_GPLYA, "gplya" }, + { TMS320C64X_REG_GPLYB, "gplyb" }, + { TMS320C64X_REG_ICR, "icr" }, + { TMS320C64X_REG_IER, "ier" }, + { TMS320C64X_REG_IERR, "ierr" }, + { TMS320C64X_REG_ILC, "ilc" }, + { TMS320C64X_REG_IRP, "irp" }, + { TMS320C64X_REG_ISR, "isr" }, + { TMS320C64X_REG_ISTP, "istp" }, + { TMS320C64X_REG_ITSR, "itsr" }, + { TMS320C64X_REG_NRP, "nrp" }, + { TMS320C64X_REG_NTSR, "ntsr" }, + { TMS320C64X_REG_REP, "rep" }, + { TMS320C64X_REG_RILC, "rilc" }, + { TMS320C64X_REG_SSR, "ssr" }, + { TMS320C64X_REG_TSCH, "tsch" }, + { TMS320C64X_REG_TSCL, "tscl" }, + { TMS320C64X_REG_TSR, "tsr" }, + { TMS320C64X_REG_A0, "a0" }, + { TMS320C64X_REG_A1, "a1" }, + { TMS320C64X_REG_A2, "a2" }, + { TMS320C64X_REG_A3, "a3" }, + { TMS320C64X_REG_A4, "a4" }, + { TMS320C64X_REG_A5, "a5" }, + { TMS320C64X_REG_A6, "a6" }, + { TMS320C64X_REG_A7, "a7" }, + { TMS320C64X_REG_A8, "a8" }, + { TMS320C64X_REG_A9, "a9" }, + { TMS320C64X_REG_A10, "a10" }, + { TMS320C64X_REG_A11, "a11" }, + { TMS320C64X_REG_A12, "a12" }, + { TMS320C64X_REG_A13, "a13" }, + { TMS320C64X_REG_A14, "a14" }, + { TMS320C64X_REG_A15, "a15" }, + { TMS320C64X_REG_A16, "a16" }, + { TMS320C64X_REG_A17, "a17" }, + { TMS320C64X_REG_A18, "a18" }, + { TMS320C64X_REG_A19, "a19" }, + { TMS320C64X_REG_A20, "a20" }, + { TMS320C64X_REG_A21, "a21" }, + { TMS320C64X_REG_A22, "a22" }, + { TMS320C64X_REG_A23, "a23" }, + { TMS320C64X_REG_A24, "a24" }, + { TMS320C64X_REG_A25, "a25" }, + { TMS320C64X_REG_A26, "a26" }, + { TMS320C64X_REG_A27, "a27" }, + { TMS320C64X_REG_A28, "a28" }, + { TMS320C64X_REG_A29, "a29" }, + { TMS320C64X_REG_A30, "a30" }, + { TMS320C64X_REG_A31, "a31" }, + { TMS320C64X_REG_B0, "b0" }, + { TMS320C64X_REG_B1, "b1" }, + { TMS320C64X_REG_B2, "b2" }, + { TMS320C64X_REG_B3, "b3" }, + { TMS320C64X_REG_B4, "b4" }, + { TMS320C64X_REG_B5, "b5" }, + { TMS320C64X_REG_B6, "b6" }, + { TMS320C64X_REG_B7, "b7" }, + { TMS320C64X_REG_B8, "b8" }, + { TMS320C64X_REG_B9, "b9" }, + { TMS320C64X_REG_B10, "b10" }, + { TMS320C64X_REG_B11, "b11" }, + { TMS320C64X_REG_B12, "b12" }, + { TMS320C64X_REG_B13, "b13" }, + { TMS320C64X_REG_B14, "b14" }, + { TMS320C64X_REG_B15, "b15" }, + { TMS320C64X_REG_B16, "b16" }, + { TMS320C64X_REG_B17, "b17" }, + { TMS320C64X_REG_B18, "b18" }, + { TMS320C64X_REG_B19, "b19" }, + { TMS320C64X_REG_B20, "b20" }, + { TMS320C64X_REG_B21, "b21" }, + { TMS320C64X_REG_B22, "b22" }, + { TMS320C64X_REG_B23, "b23" }, + { TMS320C64X_REG_B24, "b24" }, + { TMS320C64X_REG_B25, "b25" }, + { TMS320C64X_REG_B26, "b26" }, + { TMS320C64X_REG_B27, "b27" }, + { TMS320C64X_REG_B28, "b28" }, + { TMS320C64X_REG_B29, "b29" }, + { TMS320C64X_REG_B30, "b30" }, + { TMS320C64X_REG_B31, "b31" }, + { TMS320C64X_REG_PCE1, "pce1" }, }; const char *TMS320C64x_reg_name(csh handle, unsigned int reg) From cc8da331d36ae6f6565057d467bc829bc3316317 Mon Sep 17 00:00:00 2001 From: Nguyen Anh Quynh Date: Tue, 18 Dec 2018 22:44:12 +0800 Subject: [PATCH 6/6] M680X: lowercase for registers & FCB instruction --- arch/M680X/M680XInstPrinter.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/M680X/M680XInstPrinter.c b/arch/M680X/M680XInstPrinter.c index fc4e910d..3c3356b8 100644 --- a/arch/M680X/M680XInstPrinter.c +++ b/arch/M680X/M680XInstPrinter.c @@ -17,8 +17,8 @@ #ifndef CAPSTONE_DIET static const char s_reg_names[][10] = { - "", "A", "B", "E", "F", "0", "D", "W", "CC", "DP", "MD", - "HX", "H", "X", "Y", "S", "U", "V", "Q", "PC", "TMP2", "TMP3", + "", "a", "b", "e", "f", "0", "d", "w", "cc", "dp", "md", + "hx", "h", "x", "y", "s", "u", "v", "q", "pc", "tmp2", "tmp3", }; static const char s_instruction_names[][6] = { @@ -269,9 +269,9 @@ void M680X_printInst(MCInst *MI, SStream *O, void *PrinterInfo) if (info->insn == M680X_INS_INVLD || info->insn == M680X_INS_ILLGL) { if (m680x->op_count) - SStream_concat(O, "FCB $%02X", m680x->operands[0].imm); + SStream_concat(O, "fcb $%02X", m680x->operands[0].imm); else - SStream_concat(O, "FCB $"); + SStream_concat(O, "fcb $"); return; }