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Bugfix : setting all fields to insns cache (#899) 

* Bugfix : setting all fields to insns cache

* Bugfix
Fixing root cause, not setting opcode to 0 in default case

* Not resetting opcode to 0 in this case as well

* Finalizing bugfix
This commit is contained in:
Simorfo 2017-04-21 15:20:17 +02:00 committed by Nguyen Anh Quynh
parent 2bf26fe448
commit f88ef5fe37
1 changed files with 6 additions and 2 deletions
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4
arch/X86/X86Disassembler.c
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@ -230,8 +230,10 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break; case X86_CMPSSrr: NewOpc = X86_CMPSSrr_alt; break;
} }
// Switch opcode to the one that doesn't get special printing. // Switch opcode to the one that doesn't get special printing.
if (NewOpc != 0) {
MCInst_setOpcode(mcInst, NewOpc); MCInst_setOpcode(mcInst, NewOpc);
} }
}
#endif #endif
} else if (type == TYPE_IMM5) { } else if (type == TYPE_IMM5) {
#ifndef CAPSTONE_X86_REDUCE #ifndef CAPSTONE_X86_REDUCE
@ -263,8 +265,10 @@ static void translateImmediate(MCInst *mcInst, uint64_t immediate,
case X86_VCMPSSZrr: NewOpc = X86_VCMPSSZrri_alt; break; case X86_VCMPSSZrr: NewOpc = X86_VCMPSSZrri_alt; break;
} }
// Switch opcode to the one that doesn't get special printing. // Switch opcode to the one that doesn't get special printing.
if (NewOpc != 0) {
MCInst_setOpcode(mcInst, NewOpc); MCInst_setOpcode(mcInst, NewOpc);
} }
}
#endif #endif
} }