From fc59da4d1ca41a6eaf501a6eefd07e7d412ae2a5 Mon Sep 17 00:00:00 2001
From: billow <billow.fun@gmail.com>
Date: Sun, 24 Nov 2024 22:21:05 +0800
Subject: [PATCH] =?UTF-8?q?fix=20xtensa=20DecodeMR23RegisterClass=20and=20?=
 =?UTF-8?q?add=20tests=20for=20MAC16=20instru=E2=80=A6=20(#2551)?=
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* fix xtensa `DecodeMR23RegisterClass` and add tests for `MAC16` instructions

* revert
---
 arch/Xtensa/XtensaDisassembler.c |  4 +-
 tests/MC/Xtensa/mac16.s.yaml     | 97 ++++++++++++++++++++++++++++++++
 2 files changed, 99 insertions(+), 2 deletions(-)
 create mode 100644 tests/MC/Xtensa/mac16.s.yaml

diff --git a/arch/Xtensa/XtensaDisassembler.c b/arch/Xtensa/XtensaDisassembler.c
index 0fb21675..935359c2 100644
--- a/arch/Xtensa/XtensaDisassembler.c
+++ b/arch/Xtensa/XtensaDisassembler.c
@@ -225,10 +225,10 @@ static DecodeStatus DecodeMR23RegisterClass(MCInst *Inst, uint64_t RegNo,
 					    uint64_t Address,
 					    const void *Decoder)
 {
-	if ((RegNo < 2) || (RegNo > 3))
+	if (RegNo >= ARR_SIZE(MR23DecoderTable))
 		return MCDisassembler_Fail;
 
-	unsigned Reg = MR23DecoderTable[RegNo - 2];
+	unsigned Reg = MR23DecoderTable[RegNo];
 	MCOperand_CreateReg0(Inst, (Reg));
 	return MCDisassembler_Success;
 }
diff --git a/tests/MC/Xtensa/mac16.s.yaml b/tests/MC/Xtensa/mac16.s.yaml
new file mode 100644
index 00000000..d4b9401e
--- /dev/null
+++ b/tests/MC/Xtensa/mac16.s.yaml
@@ -0,0 +1,97 @@
+test_cases:
+  - input:
+      bytes: [ 0x04,0x01,0x34 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mul.ad.ll	a1, m2"
+  - input:
+      bytes: [ 0x14,0x02,0x74 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mul.aa.ll a2, a1"
+  - input:
+      bytes: [ 0x14,0x00,0x64 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mul.da.ll m0, a1"
+  - input:
+      bytes: [ 0x04,0x00,0x24 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mul.dd.ll m0, m2"
+  - input:
+      bytes: [ 0x04,0x01,0x38 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.ad.ll	a1, m2"
+  - input:
+      bytes: [ 0x14,0x02,0x78 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.aa.ll a2, a1"
+  - input:
+      bytes: [ 0x14,0x00,0x68 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.da.ll m0, a1"
+  - input:
+      bytes: [ 0x04,0x00,0x28 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.dd.ll m0, m2"
+  - input:
+      bytes: [ 0x14,0x00,0x58 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.da.ll.lddec m0, a0, m0, a1"
+  - input:
+      bytes: [ 0x14,0x00,0x48 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.da.ll.ldinc m0, a0, m0, a1"
+  - input:
+      bytes: [ 0x04,0x00,0x18 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.dd.ll.lddec m0, a0, m0, m2"
+  - input:
+      bytes: [ 0x04,0x00,0x08 ]
+      arch: "xtensa"
+      options: [ ]
+      address: 0x0
+    expected:
+      insns:
+        - asm_text: "mula.dd.ll.ldinc m0, a0, m0, m2"
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