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1334 Commits

Author SHA1 Message Date
Mike Frysinger dcb1c10540 update capstone-engine.org URIs to https:// 2023-01-17 00:01:24 -05:00
veritas501 c72fc8185e
fix inconsistent behavior of Mips_option() (#1744) 2021-06-13 21:34:40 +08:00
StalkR 71f5c64c43
ppc: fix registers overflow (#1687) 
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=22236
 2021-03-20 07:35:11 +08:00
Hauke Jürgen Mönck c59d62f735
MSVC tooling updates (#1651) 
* Update solution, remove non-existent test_basic

* Add property sheet to set platform toolset correctly

* use property sheet in all projects

* cast explicitly to avoid warnings

* make property sheet optional

* Conflcting options "Edit and continue" and "optref" caused warnings

Co-authored-by: Hauke Mönck <>
 2021-03-07 21:59:02 +08:00
notyourusualaccountname 63accbdc3f
Fix bug introduced in 0932f167fd (#1681) 
Co-authored-by: Raffaele Meyer <Raffaele Meyer>
 2021-03-07 21:58:01 +08:00
Nguyen Anh Quynh 8984920722 code style fix 2020-12-03 15:32:37 +08:00
Michal Schulz cb3c3548e9
Honour direction bit in fmove instruction (#1709) 
Co-authored-by: Michal Schulz <michal@Michals-iMac-Pro.local>
 2020-12-03 15:30:35 +08:00
Nicolas Derumigny e7d2715ba5 Bug solved: SSE variant of MOVSD incorrectly decoded as REPNE MOVSD (#1540) 2020-02-21 10:00:13 +08:00
meme 18b8002bbb Add missing ENDBR32, ENDBR64 in reduce (#1555) 2019-12-23 20:33:20 +08:00
hasherezade 5d3ceeb88c Fixed backward compatibility with C90 (#1572) 2019-12-16 00:35:00 +08:00
Jiayi Zhao 9c84eff616 systemz: fix base/index printing (#1561) 
- In cases where base is 0 but index is not, Capstone doesn't print anything
 2019-11-05 11:49:53 +08:00
Ammar 11746da3ed x86: fix call/jmp access mode of mem operand (#1479) 
sets CS_AC_READ for memory operand of call and jmp instructions
 2019-05-14 22:10:28 +07:00
Sebastian Macke 472845db9c MOS65XX: Use same output style as other archs (#1445) 
Signed-off-by: Sebastian Macke <sebastian@macke.de>
 2019-03-24 11:39:28 +08:00
hal-jones 4156eefd32 AArch64: Fix register access flags for memory instructions (#1423) 
* AArch64: fixes register access flags for loads

* AArch64: fixes register access flags for ORR

* AArch64: fixes register access flags for stores
 2019-03-17 00:37:55 +08:00
ceeac 4f3db553cf Fix #1420: Capstone 4 fails to build when targeting UWP (#1421) 2019-03-14 23:27:38 +08:00
Catena cyber 119edad22b Avoids type confusion in cpu12 for M680X (#1417) 2019-03-05 10:20:25 +08:00
Nguyen Anh Quynh d689d951d9 thumb: delete redundant code in _Thumb_getInstruction() 2019-03-04 21:44:00 +08:00
z 40b8bfa397 fix SystemZRegDesc&SystemZMCRegisterClasses number of SystemZ InitMCRegisterInfo (#1405) 2019-03-01 09:54:14 +08:00
Sebastian Macke 9baa0751ca MOS65XX: Fix instruction length for indirect addressing modes (#1402) 
Signed-off-by: Sebastian Macke <sebastian@macke.de>
 2019-02-28 06:12:52 +08:00
Nguyen Anh Quynh de952a3e5a X86: X86_insn_reg_att uses a wrong mapping array of Intel syntax 2019-02-21 15:32:00 +08:00
Nguyen Anh Quynh 6a69f43f74 x86: 8bit Imm operand has size = 1. this fixes issue #1389 2019-02-18 17:27:04 +08:00
Catena cyber 16f4c801df Fixes more undefined left shift of negative values (#1384) 2019-02-16 10:34:57 +08:00
Catena cyber 50123f1aaf Avoids overflow in getRegisterName for TMS320C64x (#1375) 
* Avoids overflow in getRegisterName for TMS320C64x

* Revert "Avoids overflow in getRegisterName for TMS320C64x"

This reverts commit 18acee60cd4206f4340f5e8ad3ddd67eab1691f3.

* Checks register in DecodeMemOperandSc
 2019-02-16 10:34:46 +08:00
Catena cyber 09fc20d626 Multiply signed integer instead of left shift (#1382) 2019-02-15 22:36:29 +08:00
Nguyen Anh Quynh cf04470e78 arm64: fix CS_OPT_UNSIGNED option on memory operand offset 2019-02-13 22:12:00 +08:00
Nguyen Anh Quynh 5a6a714bc4 x86: print imm with proper size for CS_OPT_UNSIGNED - ATT syntax 2019-02-13 22:01:39 +08:00
Nguyen Anh Quynh 5f9c0336c4 x86: print imm with proper size for CS_OPT_UNSIGNED 2019-02-13 21:48:38 +08:00
Nguyen Anh Quynh 7b251189b2 x86: ATT syntax print unsigned imm with 0x prefix 2019-02-13 01:26:04 +08:00
Nguyen Anh Quynh 92c1e1b38b x86: do not print prefix 0 for memory operand for ATT syntax 2019-02-13 01:04:57 +08:00
Nguyen Anh Quynh 36f5961435 arm: lowercase for APSR_nzcv 2019-02-13 00:43:22 +08:00
Nguyen Anh Quynh aebd183c82 arm64: support CS_OPT_UNSIGNED 2019-02-12 23:27:29 +08:00
Nguyen Anh Quynh 6bcfefb95c x86: support CS_OPT_UNSIGNED for ATT syntax 2019-02-12 23:14:30 +08:00
Nguyen Anh Quynh f24009c8f3 TMS320C64x: remove unused variable 2019-02-10 18:03:30 +08:00
Catena cyber 16e20e6333 TMS320C64x instruction names (#1373) 
* TMS320C64x instruction names

* Fix undefined shift in TMS320C64xDisassembler.c

* Adding spaces

* remove TMS320C64X_INS_ENDING naming
 2019-02-07 22:37:46 +08:00
david942j ce45730223 Fixed m68k has wrong type of read_imm_64 (#1369) 2019-02-06 00:05:21 +08:00
david942j 92242b9135 Fixed TMS320C64x failed to print instructions (#1367) 2019-02-05 23:34:33 +08:00
Nguyen Anh Quynh 45bec1a691 arm: update writeback for STR_POST_REG (issue #1296) 2019-01-28 16:34:44 +08:00
Nguyen Anh Quynh be87f94303 arm: fix issue #746 for arm mode. reported by @HarDToBelieve 2019-01-27 22:37:13 +08:00
Nguyen Anh Quynh 93f6257e8b MOS65XX: fix missing prototype for ‘MOS65XX_global_init' 2019-01-22 15:23:22 +08:00
JNA a529f4e165 fix cmovcc eflags (#1349) 2019-01-22 14:13:05 +08:00
JNA 067ca50f1e fix cmovcc eflags (#1349) 2019-01-22 13:11:34 +07:00
Marius Melzer 838b9aebd1 Fix missing-prototypes warnings (#1348) 2019-01-22 09:01:13 +08:00
Nguyen Anh Quynh 1d1bc8ff8a X86: turn some print functions to static. see #1342 2019-01-22 09:01:13 +08:00
Marius Melzer b5050df0ea Fix missing-prototypes warnings (#1348) 2019-01-22 07:39:44 +07:00
Nguyen Anh Quynh 9cd94caa90 X86: turn some print functions to static. see #1342 2019-01-21 20:21:18 +08:00
Erik Hemming 5fdc7de0d9 Fix a couple of corner-cases with rarely used m68k instructions. (#1344) 
* Bump the "cs_insn.bytes[]" size to 24 (from 16) to support M680x0 instructions with full EA (maximum 11 words)
Added a test for this in test_m68k.s

* Bump the "cs_detail.regs_read[]" size to 16 (from 12) to support M680x0 instructions with full REG_BITS (Dn+An = 16)

* m68k: use immediate mode syntax (#$0) for movem/fmovem instructions with empty register list

* update bindings to match changes to cs_insn and cs_detail
 2019-01-21 17:42:28 +08:00
Erik Hemming a8559cfb78 Fix a couple of corner-cases with rarely used m68k instructions. (#1344) 
* Bump the "cs_insn.bytes[]" size to 24 (from 16) to support M680x0 instructions with full EA (maximum 11 words)
Added a test for this in test_m68k.s

* Bump the "cs_detail.regs_read[]" size to 16 (from 12) to support M680x0 instructions with full REG_BITS (Dn+An = 16)

* m68k: use immediate mode syntax (#$0) for movem/fmovem instructions with empty register list

* update bindings to match changes to cs_insn and cs_detail
 2019-01-21 16:55:05 +08:00
Nguyen Anh Quynh 0ff8220ade Merge branch 'master' into v4.1 2019-01-04 17:23:50 +08:00
Wolfgang Schwotzer 36c61a0541 M680X: Fix clang-analyzer issue #1329. (#1334) 2019-01-03 07:48:55 +08:00
radare 31ce0b3285 Add default case in MOS65XX instruction length helper (#1333) 2019-01-03 07:48:18 +08:00