* Replace asserts with macros for AArch64, Alpha, LoongArch, Mips, SystemZ inc files.
* Add missing clearing of MCInst
* Ensure correct dir name is used.
* Replace asserts in inc files for PPC, ARM, TriCore
* Replace all asserts in modules with CS_ASSERT.
Also enable the CS_ASSERTs if CMAKE_BUILD_TYPE=Debug
* Formatting
* Run clang-format
* Remove arm.h header from AArch64 files
* Update all AArch64 module files to LLVM-18.
* Add check if the differs save file is up-to-date with the current files.
* Add new generator for MC test trnaslation.
* Fix warnings
* Update generated AsmWriter files
* Remove unused variable
* Change MCPhysReg type to int16_t as LLVM 18 dictates.
With LLVM 18 the MCPhysReg value's type is changed to int16_t.
If we update modules to LLVM 18, they will generate
compiler warnings that uint16_t* should not be casted to int16_t*.
This makes changing the all tables to int16_t necessary, because the alternative is
to duplicate all MCPhysReg related code. Which is even worse.
* Assign enum values to raw_struct member
* Add printAdrAdrpLabel def
* Add header to regression test files.
* Write files to build dir and ignore more parsing errors.
* Fix parsing of MC test files.
* Reset parser after every block
* Add write and patch header step.
* Add and update MC tests for AArch64
* Fix clang-tidy warnings
* Don't warn about padding issues.
They break automatically initialized structs we can not change easily.
* Fix: Incorrect access of LLVM instruction descriptions.
* Initialize DecoderComplete flag
* Add more mapping and flag details
* Add function to get MCInstDesc from table
* Fix incorrect memory operand access types.
* Fix test where memory was not written, ut only read.
* Attempt to fix Windows build
* Fix 2268
The enum values were different and hence lead to different decoding.
* Refactor SME operands.
- Splits SME operands in Matrix and Predicate operands.
- Fixes general problems of incorrect detections with
the vector select/index operands of predicate registers.
- Simplifies code.
* Fix up typo in WRITE
* Print actual path to struct fields
* Add Registers of SME operands to the reg-read list
* Add tests for SME operands.
* Use Capstone reg enum for comparison
* Fix tests: 'Vector arra...' to 'operands[x].vas'
* Add the developer fuzz option.
* Fix Python bindings for SME operands
* Fix variable shadowing.
* Fix clang-tidy warnings
* Add missing break.
* Fix varg usage
* Brackets for case
* Handle AArch64_OP_GROUP_AdrAdrpLabel
* Fix endian issue with fuzzing start bytes
* Move previous sme.pred to it's own operand type.
* Fix calculation for imm ranges
* Print list member flag
* Fix up operand strings for cstest
* Do only a shallow clone of the cmocka stable branch
* Fix: Don't categorize ZT0 as a SME matrix operand.
* Remove unused code.
* Add flag to distinguish Vn and Qn registers.
* Add all registers to detail struct, even if emitted in the asm text
* Fix: Increment op count after each list member is added.
* Remove implicit write to NZCV for MSR Imm instructions.
* Handle several alias operands.
* Add details for zero alias with za0.h
* Add SME tile to write list if written
* Add write access flags to operands which are zeroed.
* Add SME tests of #2285
* Fix tests with latest syntax changes.
* Fix segfault if memory operand is only a label without register.
* Fix python bindings
* Attempt to fix clang-tidy warning for some configurations.
* Add missing test file (accidentially blocked by gitignore.)
* Print clang-tidy version before linting.
* Update differ save file
* Formatting
* Use clang-tidy-15 as if possible.
* Remove search patterns for MC tests, since they need to be reworked anyways.
* Enum to upper case change
* Add information to read the OSS fuzz result.
* Fix special case of SVE2 operands.
Apparently ZT0 registers can an index attached,
get which is BOUND to it. We have no "index for reg" field.
So it is simply saved as an immediate.
* Handle LLVM expressions without asserts.
* Ensure choices are always saved.
* OP_GROUP enums can't be all upper case because they contain type information.
* Fix compatibility header patching
* Update saved_choices.json
* Allow mode == None in test_corpus
There is a compiler bug in latest MSVC, which at the time of writing is
19.36.32535: given `switch (x)`, where `x` is 64 bits wide, the compiler
generates code that computes an incorrect jump table index. E.g. if
`x` is zero, it ends up reading the table entry at index -1.
* Add auto-sync updater.
* Update Capstone core with auto-sync changes.
* Update ARM via auto-sync.
* Make changes to arch modules which are introduced by auto-sync.
* Update tests for ARM.
* Fix build warnings for make
* Remove meson.build
* Print shift amount in decimal
* Patch non LLVM register alias.
* Change type of immediate operand to unsiged (due to: #771)
* Replace all occurances of a register with its alias.
* Fix printing of signed imms
* Print rotate amount in decimal
* CHange imm type to int64_t to match LLVM imm type.
* Fix search for register names, by completing string first.
* Print ModImm operands always in decimal
* Use number format of previous capstone version.
* Correct implicit writes and update_flags according to SBit.
* Add missing test for RegImmShift
* Reverse incorrect comparision.
* Set shift information for move instructions.
* Set mem access for all memory operands
* Set subtracted flag if offset is negative.
* Add flag for post-index memory operands.
* Add detail op for BX_RET and MOVPCLR
* Use instruction post_index operand.
* Add VPOP and VPUSH as unique CS IDs.
* Add shifting info for MOVsr.
* Add TODOs.
* Add in LLVM hardcoded operands to detail.
* Move detail editing from InstPrinter to Mapping
* Formatting
* Add removed check.
* Add writeback register and constraints to RFEI instructions.
* Translate shift immediate
* Print negative immediates
* Remove duplicate invalid entry
* Add CS groups to instructions
* Fix write attriutes of stores.
* Add missing names of added instructions
* Fix LLVM bug
* Add more post_index flags
* http -> https
* Make generated functions static
* Remove tab prefix for alias instructions.
* Set ValidateMCOperand to NULL.
* Fix AddrMode3Operand operands
* Allow getting system and banked register name via API
* Add writeback to STC/LDC instructions.
* Fix (hopefully) last case where disp is negative and subtracted = true
* Remove accidentially introduced regressions
* Constify registerinfo.py output
Remove two conditionals separating identical bits of code.
Add "const" markup to MCRegisterDesc and MCRegisterClass.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify instrinfo-arch.py output
In this case, do not actively strip const.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the AArch64 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the EVM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M680X backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify M68K backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Mips backend
The Mips backend has not been regenerated from LLVM recently,
and there are more fixups required than I'd like. Just apply
the fixes to the tables by hand for now.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the Sparc backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the TMS320C64x backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the X86 backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the XCore backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify systemregister.py output
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the ARM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the PowerPC backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the MOS65XX backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the SystemZ backend
The mapping of system register to indexes is easy to
generate read-only. Since we know the indexes are
between 0 and 31, use uint8_t instead of unsigned.
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the WASM backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify cs.c
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Constify the BPF backend
Signed-off-by: Richard Henderson <rth@twiddle.net>
* Update init of cs_detail for AArch64
as @aquynh requested in #1125
* Update init of cs_detail for ARM
as @aquynh requested in #1125
* Update init of cs_detail for EVM
as @aquynh requested in #1125
* Update init of cs_detail for M680X
as @aquynh requested in #1125
* Update init of cs_detail for M68K
as @aquynh requested in #1125
* Update init of cs_detail for Mips
as @aquynh requested in #1125
* Update init of cs_detail for PowerPC
as @aquynh requested in #1125
* Update init of cs_detail for Sparc
as @aquynh requested in #1125
* Update init of cs_detail for SystemZ
as @aquynh requested in #1125
* Update init of cs_detail for TMS320C64x
as @aquynh requested in #1125
* Update init of cs_detail for XCore
as @aquynh requested in #1125
* Comment on init of cs_detail
* wrap long lines
* Declare global arch arrays with contents (#1171)
This eliminates the need for archs_enable() and eliminates the racey
initialization.
This makes the architecture-specific init and option functions
non-static so that they may be called from a different file.
Cherry-picked 853a2870
* Add cs_arch_disallowed_mode_mask global
Cherry-pick 94bce437:
mips: CS_MODE_MIPS32R6 implies CS_MODE_32
Cherry-pick 8998a3a1:
ppc: fix endian check (#1029)
Fixes bug where endianness could not be set for ppc.
Remove `big_endian` field of `cs_struct`.
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.
Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`. The checks use a new global array
`cs_arch_disallowed_mode_mask[]`.
* Make global arrays static
Make all_arch uint32_t to guarantee a certain number of bits (with
adequate room for growth).
This eliminates the need for archs_enable() and eliminates the racey
initialization.
This makes the architecture-specific init, option, and destroy functions
non-static so that they may be called from a different file.
* Fix undefined shifts
Found by oss-fuzz
uint8_t gets promoted to integer
and integers shift cannot overflow on sign bit
* Fix undefined shifts
shifting 31 bits the sign bit
* Fix undefined shifts
uint8 gets promoted to signed integer
in ARM, MIPS, Sparc
in AArch64, PPC and Xcore
* fix undefined shift in powerpc
* Fix undefined shift in Mips
use mulitply instead
* Remove `big_endian` field of `cs_struct`
Added a helper macro `MODE_IS_BIG_ENDIAN()` to check if
`CS_MODE_BIG_ENDIAN` is set.
Refactored `cs_open()` check for valid mode out of arch-specific code
into arch-independent code. Also added a valid mode check to
`cs_option()`. The checks use a new global array
`arch_disallowed_mode_mask[]`, which is initialized in the arch-specific
`*_enable()` functions.
Fixes bug where endianness could not be set for ppc.
* Fix Mac OS brew for Travis CI
* Fix selection of mips disasm handler
handle->disasm was incorrectly set to Mips64_getInstruction if CS_MODE_MIPS32R6
was set but CS_MODE_32 was not set. Now, CS_MODE_32 is set automatically if
CS_MODE_MIPS32R6 is set.
* Align with current style
* Add a new group for relative branching instructions
* x86: Add relative branch group to appropiate instructions
* Rename RELATIVE_BRANCH to BRANCH_RELATIVE
* aarch64: Add relative branch group to appropiate instructions
* arm: Add relative branch group to appropiate instructions
* m68k: Add relative branch group to appropiate instructions
* mips: Add relative branch group to appropiate instructions
Giovanni